Random number generation circuit, circuit control method and storage and calculation integrated chip

Abstract

The invention relates to a random number generation circuit, a circuit control method and a storage and calculation integrated chip. The random number generation circuit comprises a memristor circuit, a capacitor array circuit and a random number output circuit, the memristor circuit is connected with the random number output circuit, and the capacitor array circuit is arranged between the memristor circuit and the random number output circuit; the capacitor array circuit comprises a plurality of capacitor sub-circuits which are connected in parallel; the first end of at least one capacitor sub-circuit in the capacitor array circuit is configured to be connected with the memristor circuit, the first ends of the other capacitor sub-circuits are configured to be disconnected with the memristor circuit, and at least one capacitor sub-circuit is matched with the current resistance state of the memristor circuit; the random number output circuit is used for outputting a target random number. By adopting the random number generation circuit, the area of the storage and calculation integrated chip can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic circuit technology, and in particular to a random number generation circuit, a circuit control method, and a storage-computing integrated chip. Background Art

[0002] True Random Number Generator (TRNG) uses unpredictable physical processes such as thermal noise to generate a truly random bit stream and is an important security module in the chip. In related technologies, the randomness of ion movement in Resistive Random-Access Memory (RRAM) is used as the entropy source device of TRANG. Among them, memristor is a new type of memory with characteristics such as non-volatility and adjustable resistance analog; the cross-array structure based on memristor can realize a storage and computing integrated structure.

[0003] However, applying the random number generation circuit using memristors as TRNG entropy source devices to storage and computing integrated chips has the problem of large chip area. Summary of the invention

[0004] Based on this, it is necessary to provide a random number generation circuit, a circuit control method and a storage-computing integrated chip that can reduce the storage-computing integrated chip in order to address the above technical problems.

[0005] In a first aspect, a random number generation circuit is provided, comprising:

[0006] The random number generation circuit includes: a memristor circuit, a capacitor array circuit and a random number output circuit, wherein:

[0007] The memristor circuit is connected to the random number output circuit, and the capacitor array circuit is arranged between the memristor circuit and the random number output circuit;

[0008] The capacitor array circuit includes a plurality of capacitor subcircuits connected in parallel, at least one capacitor subcircuit in the capacitor array circuit is configured to be connected to the memristor circuit, and the remaining capacitor subcircuits are configured to be disconnected from the memristor circuit, wherein at least one capacitor subcircuit matches a current resistance state of the memristor circuit;

[0009] The random number output circuit is used to output a target random number.

[0010] In one embodiment, the capacitor subcircuit includes a charging switch, a charging capacitor and a discharging switch, wherein:

[0011] A first end of the charging switch is connected to the memristor circuit, and a second end of the charging switch is connected to a first end of the charging capacitor;

[0012] The first end of the charging capacitor is also connected to the first end of the discharging switch, and the second end of the charging capacitor is grounded and connected to the second end of the discharging switch.

[0013] In one embodiment, the capacitance values ​​of the charging capacitors included in each capacitor subcircuit are different.

[0014] In one embodiment, the random number output circuit includes: a comparison circuit and a trigger circuit, wherein:

[0015] A first terminal of the comparison circuit is connected to the memristor circuit, a second terminal of the comparison circuit is configured to input an entropy source reference voltage, and a third terminal of the comparison circuit is connected to a first terminal of the trigger circuit;

[0016] The second end of the trigger circuit is used to obtain a clock signal, and the third end of the trigger circuit is used to output a target random number according to the change of the clock signal and the output value of the comparison circuit.

[0017] In one of the embodiments, the random number generation circuit further includes a current output circuit;

[0018] The current output circuit is connected to the memristor circuit and is used for outputting the current value corresponding to the memristor circuit.

[0019] In one embodiment, the random number generation circuit further includes a current output circuit; the current output circuit includes a digital-to-analog conversion circuit and a successive approximation circuit, wherein:

[0020] In the current reading mode, the first terminal of the digital-to-analog conversion circuit is connected to the first terminal of the successive approximation circuit, and the second terminal of the digital-to-analog conversion circuit is connected to the second terminal of the comparison circuit;

[0021] The third terminal of the comparison circuit is connected to the second terminal of the successive approximation circuit in the current reading mode;

[0022] The third terminal of the successive approximation circuit is used to output the current value of the memristor circuit.

[0023] In a second aspect, a circuit control method is provided for controlling the random number generation circuit provided in the first aspect, the method comprising:

[0024] According to the current resistance state of the memristor circuit, controlling at least one capacitor subcircuit in the capacitor array circuit to be connected to the memristor circuit, and controlling the remaining capacitor subcircuits to be disconnected from the memristor circuit;

[0025] A first reading voltage is input to the memristor circuit, and a target random number is output through the random number output circuit.

[0026] In one embodiment, the method further comprises:

[0027] In the current reading mode, a second reading voltage is input to the memristor circuit, and a current current value corresponding to the memristor circuit is output through the current output circuit.

[0028] In one embodiment, according to the current resistance state of the memristor circuit, controlling at least one capacitor subcircuit in the capacitor array circuit to be connected to the memristor circuit includes:

[0029] Determining a current resistance state of the memristor circuit according to a current current value corresponding to the memristor circuit;

[0030] determining at least one capacitor subcircuit from the capacitor array circuit according to the current resistance state;

[0031] At least one capacitor subcircuit is controlled to be connected to the memristor circuit.

[0032] In a third aspect, a storage-computing integrated chip is provided. The storage-computing integrated chip includes the random number generation circuit provided in the first aspect; the storage-computing integrated chip also includes a processor and a memory, the memory stores a computer program, and when the processor executes the computer program, the circuit control method provided in the second aspect is implemented.

[0033] The above-mentioned random number generation circuit, circuit control method and storage-computing integrated chip, wherein the random number generation circuit includes a memristor circuit, a capacitor array circuit and a random number output circuit, wherein the memristor circuit is connected to the random number output circuit, and the capacitor array circuit is arranged between the memristor circuit and the random number output circuit; the capacitor array circuit includes a plurality of capacitor subcircuits connected in parallel; the first end of at least one capacitor subcircuit in the capacitor array circuit is configured to be connected to the memristor circuit, and the first ends of the remaining capacitor subcircuits are configured to be disconnected from the memristor circuit, wherein at least one capacitor subcircuit matches the current resistance state of the memristor circuit; the random number output circuit is used to output a target random number; in this way , the random number generation circuit is applied to a storage-computing integrated chip using a memristor, and at least one capacitor subcircuit is determined from the capacitor array circuit to be connected to the memristor circuit according to the current resistance state of the memristor circuit, so as to achieve the same or similar random number generation speed under different resistance states of the memristor circuit, so that the memristor circuit as the entropy source device of the random number generation circuit can continue to be used as the storage-computing structure in the storage-computing integrated chip, which means that there is no need to add a special device as the entropy source device of the random number generation circuit in the storage-computing integrated chip, but the memristor circuit in the storage-computing integrated chip can be directly used, and the memristor circuit can be reused as the storage-computing integrated structure and the entropy source for random number generation. Therefore, the random number generation circuit provided by the above embodiment can reduce the area of ​​the storage-computing integrated chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 A schematic diagram of the structure of a random number generating circuit in one embodiment;

[0036] Figure 2 is a schematic structural diagram of a random number generating circuit in another embodiment;

[0037] Figure 3 An exemplary schematic diagram of a voltage change timing of a positive input terminal V1 of a comparison circuit, a third terminal V2 of a comparison circuit 310 and a second terminal V3 of a trigger circuit during a charging process according to an embodiment;

[0038] Figure 4 is a schematic structural diagram of a random number generating circuit in another embodiment;

[0039] Figure 5 is a schematic structural diagram of a random number generating circuit in another embodiment;

[0040] Figure 6 A schematic diagram of simulation results of random number generation in a low-resistance state in one embodiment;

[0041] Figure 7 A schematic diagram of simulation results of random number generation in a high impedance state in one embodiment;

[0042] Figure 8 A schematic flow chart of a circuit control method provided in one embodiment;

[0043] Fig. 9 A schematic flow chart of a circuit control solution provided in another embodiment.

[0044] Reference numerals:

[0045] 100, memristor circuit; 110, memristor element; 120, switch element; 200, capacitor array circuit; 300, random number output circuit; 310, comparison circuit; 320, trigger circuit; 400, current output circuit; 410, digital-to-analog conversion circuit; 420, successive approximation circuit. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0048] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0049] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0051] In an exemplary embodiment, please refer to Figure 1 , a random number generation circuit is provided, including: a memristor circuit 100, a capacitor array circuit 200 and a random number output circuit 300; the memristor circuit 100 and the random number output circuit 300 are connected, and the capacitor array circuit 200 is arranged between the memristor circuit 100 and the random number output circuit 300.

[0052] Among them, the resistance value of the memristor circuit 100 can be dynamically adjusted within a certain range by controlling the magnitude and duration of the applied voltage. After power failure, the memristor circuit 100 can maintain its previous resistance state to achieve the function of data storage. After the memristor circuit 100 is applied with voltage, the random movement of ions produces randomness, also known as "read noise".

[0053] The first end of the memristor circuit 100 is used to be applied with a reading voltage V_READ, and the second end of the memristor circuit 100 is used to output a reading current I_SL according to the reading voltage V_READ. Figure 2 The memristor circuit 100 includes a memristor element 110 and a switch element 120. The switch element 120 may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulate-Gate Bipolar Transistor) or other three-terminal switch elements.

[0054] Among them, when the memristor circuit 100 is used as a storage and calculation structure, the first end of the memristor circuit 100 is also used to obtain the first applied voltage or ground, and the third end of the memristor circuit 100 is also used to ground or obtain the second applied voltage. According to the positive and negative and magnitude of the first applied voltage and the second applied voltage, the resistance of the memristor element is in different resistance states, corresponding to different resistance ranges; exemplarily, when the memristor element is in a high resistance state, corresponding to bit 0, the current resistance range of the memristor element is 200KΩ (kilo-ohm) ~ 600KΩ, and when the memristor element is in a low resistance state, corresponding to bit 1, the resistance range of the memristor element is 20KΩ ~ 30KΩ; then a reading voltage is applied to the first end of the memristor circuit 100, and the reading current output from the second end of the memristor circuit 100 is read, thereby obtaining the resistance state of the memristor element and determining the data stored in the memristor element. In another exemplary embodiment, the memristor element can include not only the two resistance states of low resistance state and high resistance state, but also multiple resistance states, corresponding to the storage of multiple different values.

[0055] The capacitor array circuit 200 includes multiple capacitor sub-circuits connected in parallel, at least one capacitor sub-circuit in the capacitor array circuit 200 is configured to be connected to the memristor circuit 100, and the remaining capacitor sub-circuits are configured to be disconnected from the memristor circuit 100, wherein the at least one capacitor sub-circuit matches the current resistance state of the memristor circuit 100.

[0056] In the related art, when the memristor circuit 100 is used as an entropy source device, a reading voltage is applied to the memristor circuit 100, and the randomness of the read noise in the memristor circuit 100 is digitized through the capacitor and the random number output circuit 300 to generate a true random number. Through the simultaneous operation of multiple random number generation circuits, the one-bit random array generated by the multiple random number generation circuits is synthesized into the final required true random number, wherein the charging time of the capacitor is proportional to R×C, wherein R is the current resistance value of the memristor circuit 100, and C is the capacitance value of the charging capacitor, that is, if the resistance value corresponding to the memristor circuit 100 in the multiple random number generation circuits is dynamically changed, then the speed at which each random number generation circuit generates a random number cannot be guaranteed. Therefore, the resistance value corresponding to the memristor circuit in the related art is within a specific range, but in this way, the memristor circuit cannot be used as a storage and calculation structure. In the storage and calculation integrated chip, both the memristor circuit as an entropy source device and the memristor circuit as a storage and calculation structure must be set, resulting in a larger area of ​​the storage and calculation integrated chip.

[0057] In the embodiment of the present application, a capacitor array circuit 200 is used. In the random number generation mode, at least one capacitor sub-circuit is determined from the capacitor array circuit 200 to be connected to the memristor circuit 100 according to the current resistance value of the memristor circuit 100, and the remaining capacitor sub-circuits are disconnected from the memristor circuit 100. This can make the multiple random number generation currents provided by the present embodiment the same or similar at the time corresponding to the generation of true random numbers. Therefore, the memristor circuit 100 as an entropy source device can be in different resistance state ranges.

[0058] The random number output circuit 300 is used to output a target random number. The random number output circuit 300 outputs the target random number according to the time when the charging of at least one capacitor subcircuit in the capacitor array circuit 200 configured to be connected to the memristor circuit 100 is completed.

[0059] The random number generation circuit provided in the above embodiment includes a memristor circuit 100, a capacitor array circuit 200 and a random number output circuit 300, wherein the memristor circuit 100 is connected to the random number output circuit 300, and the capacitor array circuit 200 is arranged between the memristor circuit 100 and the random number output circuit 300; the capacitor array circuit 200 includes a plurality of capacitor subcircuits connected in parallel; a first end of at least one capacitor subcircuit in the capacitor array circuit 200 is configured to be connected to the memristor circuit 100, and a first end of the remaining capacitor subcircuits is configured to be disconnected from the memristor circuit 100, wherein at least one capacitor subcircuit matches the current resistance state of the memristor circuit 100; the random number output circuit 300 is used to output a target random number; In this way, the random number generation circuit is applied to a storage-computation integrated chip using a memristor, and at least one capacitor subcircuit is determined from the capacitor array circuit 200 to be connected to the memristor circuit 100 according to the current resistance state of the memristor circuit 100, so as to achieve the same or similar random number generation speed under different resistance states of the memristor circuit 100, so that the memristor circuit 100 as an entropy source device of the random number generation circuit can continue to be used as a storage-computation structure in the storage-computation integrated chip, which means that there is no need to add a special device as an entropy source device of the random number generation circuit in the storage-computation integrated chip, but the memristor circuit 100 in the storage-computation integrated chip can be directly used, and the memristor circuit 100 can be reused as a storage-computation integrated structure and an entropy source for random number generation. Therefore, the random number generation circuit provided by the above embodiment can reduce the area of ​​the storage-computation integrated chip.

[0060] In an exemplary embodiment, the capacitor subcircuit in the random number generation circuit provided includes a charging switch, a charging capacitor and a discharging switch. The first end of the charging switch is connected to the memristor circuit 100, and the second end of the charging switch is connected to the first end of the charging capacitor; the first end of the charging capacitor is also connected to the first end of the discharging switch, and the second end of the charging capacitor is grounded and connected to the second end of the discharging switch.

[0061] Please refer to Figure 2 The random number generating circuit shown in the figure, wherein the capacitor array circuit 200 includes two capacitor sub-circuits, and there are at least two resistance state ranges corresponding to the memristor circuit 100; one of the capacitor sub-circuits (for the convenience of describing this solution, the capacitor sub-circuit is referred to as the capacitor sub-circuit A1) includes a charging switch S4_1, a charging capacitor C1 and a discharging switch S5_1, and the other capacitor sub-circuit (for the convenience of describing, the resistor sub-circuit is referred to as the capacitor sub-circuit A2) includes a charging switch S4_2, a charging capacitor C2 and a discharging switch S5_2.

[0062] Exemplarily, the capacitance of the charging capacitor C1 is greater than the capacitance of the charging capacitor C2. For example, the resistance of the charging capacitor C1 is 7fF (femtofarad), and the resistance of the charging capacitor C2 is 500fF. Correspondingly, exemplary, the memristor circuit 100 has two resistance states, a high resistance state and a low resistance state. When the current resistance state of the memristor circuit 100 is the high resistance state, the capacitor subcircuit A1 is controlled to be connected to the memristor circuit 100, that is, the charging switch S4_1 is closed, and the discharge switch S5_1 is disconnected, so that the charging capacitor C1 is connected to the memristor circuit 100. At the same time, the capacitor subcircuit A2 is controlled to be disconnected from the memristor circuit 100, that is, the charging switch S4_2 is opened, and the random number output circuit 30 is turned on. 0 outputs the target random number, controls the discharge switch S5_1 to be closed, so that both ends of the charging capacitor C1 are grounded, so that the charging capacitor C1 is discharged; when the current resistance state of the memristor circuit 100 is the low resistance state, controls the capacitor sub-circuit A2 to be connected to the memristor circuit 100, that is, closes the charging switch S4_2, disconnects the discharge switch S5_2, so that the charging capacitor C2 is connected to the memristor circuit 100, and controls the capacitor sub-circuit A1 to be disconnected from the memristor circuit 100, that is, opens the charging switch S4_1, and after the random number output circuit 300 outputs the target random number, controls the discharge switch S5_2 to be closed, so that both ends of the charging capacitor C2 are grounded, so that the charging capacitor C2 is discharged.

[0063] Exemplarily, when the capacitor array circuit 200 includes two capacitor sub-circuits, there are three resistance state ranges corresponding to the memristor circuit 100, wherein the first resistance state range corresponds to the charging capacitor C1, the second resistance state range corresponds to the charging capacitor C2, and the third resistance state range corresponds to the charging capacitor C1 and the charging capacitor C2 being connected to the memristor circuit 100 at the same time.

[0064] In a possible implementation, each capacitor subcircuit includes a charging capacitor with a different capacitance value. Exemplarily, each capacitor subcircuit corresponds to a resistance state range of the memristor circuit 100 .

[0065] In another possible implementation, the capacitance of the charging capacitor in at least two capacitor subcircuits in each capacitor subcircuit is the same. Exemplarily, the capacitor array circuit 200 includes two capacitor subcircuits with a charging capacitance of 250fF and one capacitor subcircuit with a charging capacitance of 7fF, wherein, when a charging capacitor of 250fF is needed to match the resistance of the memristor circuit 100, any one of the two capacitor subcircuits with a charging capacitance of 250fF can be connected to the memristor circuit 100; when a charging capacitor of 500fF is needed to match the resistance of the memristor circuit 100, both of the two capacitor subcircuits with a charging capacitance of 250fF are connected to the memristor circuit 100; when a charging capacitor of 7fF is needed to match the resistance of the memristor circuit 100, the capacitor subcircuit with a charging capacitance of 7fF is connected to the memristor circuit 100. In this embodiment, the memristor circuit 100 having three resistance state ranges may be used as an entropy source in the random number generation circuit.

[0066] In specific applications, the number and capacitance of the capacitor sub-circuits in the capacitor array circuit 200 are determined according to the resistance state range and resistance state type corresponding to the memristor circuit 100 in the actual application scenario.

[0067] In an exemplary embodiment, the random number output circuit 300 includes a comparison circuit 310 and a trigger circuit 320, wherein the first end of the comparison circuit 310 is connected to the memristor circuit 100, the second end of the comparison circuit 310 is configured to input the entropy source reference voltage, and the third end of the comparison circuit 310 is connected to the first end of the trigger circuit 320; the second end of the trigger circuit 320 is used to obtain a clock signal, and the third end of the trigger circuit 320 is used to output a target random number according to the clock signal and the output value of the comparison circuit 310. The first end of the comparison circuit 310 is connected to the memristor circuit 100, which is equivalent to the first end of the comparison circuit 310 being connected to the first end of the capacitor array circuit 200, wherein the second end of the capacitor array circuit 200 is grounded.

[0068] Please refer to Figure 2 In a possible implementation, the first terminal of the comparison circuit 310 is a positive input terminal, and the second terminal of the comparison circuit 310 is a negative input terminal. The amplitude of the entropy source reference voltage VREF_TRNG is slightly smaller than the amplitude of the reading voltage V_READ input to the memristor circuit 100; illustratively, the amplitude of the reading voltage V_READ is 200 mV (millivolts), and the amplitude of the input entropy source reference voltage VREF_TRNG is 170 mV.

[0069] Combination Figure 2, according to the current resistance state of the memristor circuit 100, control at least one capacitor subcircuit in the capacitor array circuit 200 to be connected to the memristor circuit 100, and control the remaining capacitor subcircuits to be disconnected from the memristor circuit 100; apply a reading voltage V_READ to the memristor circuit 100, and under the action of the reading voltage V_READ, the memristor circuit 100 outputs a reading current I_SL to charge the charging capacitor in the above-mentioned at least one capacitor subcircuit; please refer to Figure 3 , is an exemplary schematic diagram of the voltage change timing of the positive input terminal V1 of the comparison circuit 310, the third terminal V2 of the comparison circuit 310 and the second terminal V3 of the trigger circuit 320 during the charging process; at the beginning of charging, the voltage of the positive input terminal V1 of the comparison circuit 310 is less than the entropy source reference voltage VREF_TRNG, and the third terminal V2 of the comparison circuit 310 outputs a low level. When charging makes the voltage of the positive input terminal V1 of the comparison circuit 310 greater than the entropy source reference voltage VREF_TRNG, the output of the third terminal V2 of the comparison circuit 310 flips from a low level to a high level, that is, a rising edge signal is generated, and the trigger circuit 320 triggers the rising edge signal at the time t corresponding to the rising edge signal. C is triggered, the clock signal CLK_TRNG at the second terminal D3 of the trigger circuit 320 is sampled, and the clock signal CLK_TRNG is randomly sampled as a high level or a low level and output from the third terminal of the trigger circuit 320; wherein, the voltage at the positive input terminal V1 of the comparison circuit 310 is greater than the entropy source reference voltage VREF_TRNG at the time t C Affected by the read noise of the memristor circuit 100 , it has strong randomness, that is, the third terminal output of the trigger circuit 320 is high level or low level with strong randomness.

[0070] Exemplarily, the trigger circuit 320 may be implemented using a D trigger circuit 320 .

[0071] In another possible implementation, the first terminal of the comparison circuit 310 is a negative input terminal, and the second terminal of the comparison circuit 310 is a positive input terminal.

[0072] In this embodiment, the frequency of the clock signal CLK_TRNG obtained by the trigger circuit 320 is relatively high, which further ensures the randomness of the output of the trigger circuit 320. Optionally, the frequency of the clock signal CLK_TRNG ranges from 1 GHz (gigahertz) to 20 GHz, and illustratively, the frequency of the clock signal CLK_TRNG is 10 GHz.

[0073] Please refer to Figure 2In a possible implementation, a switch S1 is provided at the second end of the memristor circuit 100. When the random number generation circuit does not need to work, the switch S1 is opened to apply a calculation voltage to the memristor circuit 100, so as to avoid the current generated by the calculation voltage causing voltage stress risk to the random number output circuit 300 and the components in the capacitor array circuit 200. When the random number generation circuit is working, the switch S1 is closed.

[0074] In an exemplary embodiment, please refer to Figure 4 The provided random number generation circuit also includes a current output circuit, wherein the current output circuit is connected to the memristor circuit 100 and is used to output a current current value corresponding to the memristor circuit 100 in a current reading mode.

[0075] Exemplarily, the current output circuit can be an ADC (analog to digital converter) circuit based on a successive approximation circuit 420, which is used to output a corresponding reading current when a reading voltage is applied to the memristor circuit 100, so that the storage and computing chip can determine the value stored in the memristor circuit 100 based on the reading current.

[0076] In this embodiment, the random number output circuit 300 and the capacitor array circuit 200 as a whole can be independent of the current output circuit. In a possible implementation, the capacitor array circuit 200 and the memristor circuit 100, and the current output circuit and the memristor are disconnected by switches, respectively. When the random number generation circuit is in the random number generation mode, the current output circuit is disconnected from the memristor circuit 100; when the random number generation circuit is in the current reading mode, the capacitor array circuit 200 and the memristor circuit 100 are disconnected to avoid affecting the reading timeliness and accuracy of the current output circuit.

[0077] In an exemplary embodiment, please refer to Figure 5, the random number generation circuit provided also includes a current output circuit, wherein the current output circuit includes a digital-to-analog conversion circuit 410 and a successive approximation circuit 420, wherein, when the random number generation circuit is in a current reading mode, the first end of the digital-to-analog conversion circuit 410 is connected to the first end of the successive approximation circuit 420, and the second end of the digital-to-analog conversion circuit 410 is connected to the second end of the comparison circuit 310; the third end of the comparison circuit 310 is connected to the second end of the successive approximation circuit 420 in the current reading mode; the third end of the successive approximation circuit 420 is used to output the current current value of the memristor circuit 100. Exemplarily, the digital-to-analog conversion circuit 410 uses a DAC (Digital to Analog converter, digital-to-analog converter), and again exemplary, the successive approximation circuit 420 uses a SAR (successive approximation register, successive approximation register) logic.

[0078] For example, Figure 5 As shown, a single-pole double-throw switch S2 is set at the second end of the comparison circuit 310, and a single-pole double-throw switch S3 is set at the third end of the comparison circuit 310; when the random number generation circuit is in the random number generation mode, the single-pole double-throw switch S2 is connected to the circuit that outputs the entropy source reference voltage, and the single-pole double-throw switch S3 is connected to the first end of the trigger circuit 320; when the random number generation circuit is in the current reading mode, the single-pole double-throw switch S2 is connected to the second end of the digital-to-analog conversion circuit 410, and the single-pole double-throw switch S3 is connected to the successive approximation circuit 420.

[0079] Please refer to Figure 5 In the current reading mode, the switch S1 is closed. In each comparison cycle, the digital-to-analog conversion circuit 410 outputs different voltage signals under the control of the successive approximation circuit 420. The reading current I_SL is connected to the first terminal of the comparison circuit 310 and compared with the output voltage of the digital-to-analog conversion circuit 410. The comparison circuit 310 outputs a comparison result according to the voltage magnitudes of the first terminal and the second terminal. The comparison result is fed back to the successive approximation circuit for current state judgment and guidance of subsequent approximation steps. By continuously adjusting the output voltage of the digital-to-analog conversion circuit 410, it gradually compares the input voltage of the first terminal of the circuit 310 until the entire sampling cycle is completed, thereby generating an accurate digital output signal, i.e., the value of the reading current I_SL.

[0080] In one possible implementation of this embodiment, when the provided random number generation circuit is in current reading mode, each capacitor sub-circuit in the capacitor array circuit 200 is configured to be disconnected from the memristor circuit 100 to avoid affecting the reading timeliness and accuracy of the current output circuit.

[0081] The current output circuit in the random number generation circuit provided in this embodiment reduces the area of ​​the storage and computing integrated chip by multiplexing the comparison circuit 310 in the random number output circuit 300.

[0082] In an exemplary embodiment, please refer to Figure 5 The random number generation circuit provided includes: a memristor circuit 100, a capacitor array circuit 200, a comparison circuit 310, a trigger circuit 320, a digital-to-analog conversion circuit 410 and a successive approximation circuit 420, wherein:

[0083] The first end of the memristor circuit 100 is configured to input a reading voltage, the second end of the memristor circuit 100 is connected to the first end of the comparison circuit 310, and the capacitor array circuit 200 is arranged between the second end of the memristor circuit 100 and the first end of the comparison circuit 310; the capacitor array circuit 200 includes a plurality of capacitor subcircuits connected in parallel, and in a random number output mode, at least one capacitor subcircuit in the capacitor array circuit 200 is configured to be connected to the memristor circuit 100, and the remaining capacitor subcircuits are configured to be disconnected from the memristor circuit 100, wherein at least one capacitor subcircuit matches the current resistance state of the memristor circuit 100, and in a current reading mode, each capacitor subcircuit is configured to be disconnected from the memristor circuit 100; in a random number output mode, the comparison circuit 310 is connected to ... The second end of the circuit 310 is configured to input an entropy source reference voltage, the third end of the comparison circuit 310 is configured to be connected to the first end of the division circuit, and in the current reading mode, the second end of the comparison circuit 310 is configured to be connected to the second end of the digital-to-analog conversion circuit 410, and the third end of the comparison circuit 310 is configured to be linked to the second end of the successive approximation circuit 420, wherein the first end of the digital-to-analog conversion circuit 410 is connected to the first end of the successive approximation circuit 420; the second end of the trigger circuit 320 is used to obtain a clock signal, the third end of the trigger circuit 320 is used to output a target random number according to the clock signal and the output value of the third end of the comparison circuit 310 when it changes, and the third end of the successive approximation circuit 420 is used to output the current current value of the memristor circuit 100.

[0084] Among them, the capacitor subcircuit includes a charging switch, a charging capacitor and a discharging switch, the first end of the charging switch is connected to the memristor circuit 100, and the second end of the charging switch is connected to the first end of the charging capacitor; the first end of the charging capacitor is also connected to the first end of the discharging switch, and the second end of the charging capacitor is grounded and connected to the second end of the discharging switch; the capacitance of the charging capacitor included in each capacitor subcircuit is different.

[0085] The random number generation circuit provided in the above embodiment can generate random numbers regardless of the resistance value of the memristor resistor. At the same time, the random number generation circuit can be used as a storage and computing structure in a storage and computing integrated chip, and can output the current current of the memristor circuit 100 in the current reading mode, thereby increasing the function of outputting random numbers for the traditional storage and computing integrated chip with a small circuit area overhead.

[0086] For example, please refer to Figure 6 and Figure 7 , the simulation results of random number generation in low-resistance state and high-resistance state are given as examples. Figure 6 The corresponding random number generation simulation results in the low-resistance state are: Figure 6 (a) in FIG. 1 shows the change of the read resistance of a memristor circuit 100 in a low resistance state after 1000 reads. Figure 6 (b) in FIG. 1 shows the distribution of read resistance of 10 randomly selected memristor circuits 100 in a low resistance state. Figure 6 (c) in the above corresponds to Figure 6 (a) shows the random number generation simulation result of the memristor circuit 100 under Cadence software. Figure 7 The corresponding random number generation simulation results in high impedance state, Figure 7 (a) in FIG. 1 shows the change of the read resistance of a memristor circuit 100 in a high-resistance state after 1000 reads. Figure 7 (b) in FIG. 1 shows the distribution of read resistance of 10 randomly selected memristor circuits 100 in a high-resistance state. Figure 7 (c) in the above formula corresponds to Figure 7 (a) shows the random number generation simulation result of the memristor circuit 100 under Cadence software.

[0087] from Figure 6 and Figure 7 It can be seen that no matter the memristor circuit 100 is in a high-resistance state or a low-resistance state, the random number generated by the random number generation circuit will randomly jump between a value of 0 and a value of 1 according to the specific resistance value corresponding to the memristor circuit 100.

[0088] Figure 6 and Figure 7 The ordinate of each coordinate system is resistance, that is, the resistance value, and the unit is KΩ; Figure 6 (a) and Figure 7 The horizontal axis of the coordinate system in (a) represents the number of read cycles, Figure 6 (b) and Figure 7The horizontal axis of the coordinate system in (b) represents Devices, that is, the indexes corresponding to 10 different memristor circuits 100. Figure 6 (c) and Figure 7 The horizontal axis of the coordinate system in (c) represents TRNG output, that is, the true random value output by the random number generation circuit.

[0089] Based on the same inventive concept, the embodiment of the present application also provides a circuit control method for controlling the above-mentioned random number generation circuit. The implementation scheme for solving the problem provided by the method is similar to the implementation scheme recorded in the above-mentioned random number generation circuit embodiment, so the specific limitations in one or more circuit control method embodiments provided below can refer to the above-mentioned limitations on the random number generation circuit, and will not be repeated here.

[0090] In an exemplary embodiment, a circuit control method is provided for controlling the random number generation circuit provided in the above embodiments; the method can be used as an example for a processor in a storage-computing integrated chip. Figure 8 , the control method includes steps 802 to 804, wherein:

[0091] Step 802 , according to the current resistance state of the memristor circuit 100 , control at least one capacitor subcircuit in the capacitor array circuit 200 to be connected to the memristor circuit 100 , and control the remaining subcircuits to be disconnected from the memristor circuit 100 .

[0092] In a possible implementation, a flag is set to store the current resistance state of the memristor circuit 100 .

[0093] Step 804 , input a first reading voltage to the memristor circuit 100 , and output a target random number through the random number output circuit 300 .

[0094] In an exemplary embodiment, the provided circuit control method further includes: in the current reading mode, inputting a second reading voltage to the memristor circuit 100 , and outputting a current value corresponding to the memristor current through the current output circuit.

[0095] In a possible implementation, in the current reading mode, before the second reading voltage is input to the memristor circuit 100 , each capacitor sub-circuit in the capacitor array circuit 200 is controlled to be disconnected from the memristor circuit 100 .

[0096] The specific values ​​of the first reading voltage and the second reading voltage are set according to the application scenario, the hardware parameters of the memristor element, etc. In a possible implementation, the value range of the first reading voltage and the second reading voltage is 0.1V to 0.3V; exemplarily, the values ​​of the first reading voltage and the second reading voltage are the same, both 0.2V; and exemplarily, the values ​​of the first reading voltage and the second reading voltage are different.

[0097] In the current output mode, the second reading voltage is set between 0.1V and 0.3V, which can prevent the second reading voltage from being too large to change the resistance state of the memristor circuit 100, and can also prevent the second reading voltage from being too small to be difficult to measure.

[0098] In this embodiment, the random number generation circuit can be configured into two modes, one mode is a random number generation mode, and the other mode is a current reading mode; according to different modes, different data output circuits are called to obtain the output in the corresponding mode.

[0099] In an exemplary embodiment, the circuit control method provided involves a process of controlling how to control at least one capacitor subcircuit in a capacitor array circuit 200 to be connected to a memristor circuit 100, the process comprising: determining a current resistance state of the memristor circuit 100 according to a current current value corresponding to the memristor circuit 100, determining at least one capacitor subcircuit from the capacitor array circuit 200 according to the current resistance state, and controlling the at least one capacitor subcircuit to be connected to the memristor circuit 100.

[0100] In this embodiment, the current resistance state of the memristor circuit 100 is determined according to the current current value of the memristor circuit 100 corresponding to the current output circuit in the current reading mode, which simplifies the method for determining the current resistance state of the memristor circuit 100 and improves the speed of random number generation.

[0101] In an exemplary embodiment, in the circuit control method provided, at least one capacitor subcircuit is determined from the capacitor array circuit 200 according to the current current value corresponding to the memristor circuit 100, and the at least one capacitor subcircuit is controlled to be connected to the memristor circuit 100; wherein, based on the current current value corresponding to the memristor circuit 100, the current resistance value of the memristor circuit 100 can be determined, and based on the current resistance value of the memristor circuit 100, it can be determined which one or more capacitor subcircuits are selected to be connected to the memristor circuit 100 in the random number generation mode. Based on this, in this embodiment, a mapping relationship between the current current value corresponding to the memristor circuit 100 and the determination of which one or more capacitor subcircuits are selected in the random number generation mode is established, and at least one capacitor subcircuit is determined from the capacitor array circuit 200 directly based on the current current value.

[0102] In this embodiment, the current current value of the memristor circuit 100 corresponding to the current output circuit in the current reading mode is used to characterize the current resistance state of the memristor circuit 100, and at least one capacitor sub-circuit connected to the memristor circuit 100 in the random number generation mode is directly determined, thereby simplifying the process of determining at least one capacitor sub-circuit and improving the speed of random number generation.

[0103] In an exemplary embodiment, please refer to Fig. 9 , the circuit control method provided includes steps 902 to 910, wherein:

[0104] Step 902: Acquire a mode control signal.

[0105] Step 904, when the mode control signal corresponds to the random number generation mode, according to the current resistance state of the memristor circuit 100, control at least one capacitor subcircuit in the capacitor array circuit 200 to be connected to the memristor circuit 100, control the remaining capacitor subcircuits to be disconnected from the memristor circuit 100, control the second end of the comparison circuit 310 to input the entropy source reference voltage, and control the third end of the comparison circuit 310 to be connected to the first end of the trigger circuit 320.

[0106] Step 906 , input the first reading voltage to the memristor circuit 100 to obtain the target random number output by the third terminal of the trigger circuit 320 .

[0107] Step 908 , in the current reading mode corresponding to the mode control signal, the second terminal of the control comparison circuit 310 is connected to the second terminal of the digital-to-analog conversion circuit 410 , and the third terminal of the control comparison circuit 310 is connected to the second terminal of the successive approximation circuit 420 .

[0108] Step 910 , input a second reading voltage to the memristor circuit 100 to obtain a current value outputted by the third terminal of the successive approximation circuit 420 .

[0109] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0110] Based on the same inventive concept, an embodiment of the present application also provides a storage and computing integrated chip, including the random number generation circuit provided in the above embodiment, and also including a processor and a memory, wherein a computer program is stored in the memory, and the processor executes the computer program to implement the circuit control method provided in the above method embodiment.

[0111] In an exemplary embodiment, an electronic device is provided, which includes the storage and computing integrated chip provided in the above embodiment.

[0112] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A random number generating circuit, characterized in that: The random number generation circuit comprises: a memristor circuit, a capacitor array circuit and a random number output circuit, wherein: The memristor circuit is connected to the random number output circuit, and the capacitor array circuit is arranged between the memristor circuit and the random number output circuit; The capacitor array circuit includes a plurality of capacitor subcircuits connected in parallel, at least one capacitor subcircuit in the capacitor array circuit is configured to be connected to the memristor circuit, and the remaining capacitor subcircuits are configured to be disconnected from the memristor circuit, wherein the at least one capacitor subcircuit matches the current resistance state of the memristor circuit; The random number output circuit is used for outputting a target random number.

2. The random number generating circuit according to claim 1, characterized in that: The capacitor subcircuit includes a charging switch, a charging capacitor and a discharging switch, wherein: A first end of the charging switch is connected to the memristor circuit, and a second end of the charging switch is connected to a first end of the charging capacitor; The first end of the charging capacitor is also connected to the first end of the discharging switch, and the second end of the charging capacitor is grounded and connected to the second end of the discharging switch.

3. The random number generating circuit according to claim 2, characterized in that: The capacitance values ​​of the charging capacitors included in each of the capacitor subcircuits are different.

4. The random number generating circuit according to claim 1, characterized in that: The random number output circuit includes: a comparison circuit and a trigger circuit, wherein: A first terminal of the comparison circuit is connected to the memristor circuit, a second terminal of the comparison circuit is configured to input an entropy source reference voltage, and a third terminal of the comparison circuit is connected to a first terminal of the trigger circuit; The second end of the trigger circuit is used to obtain a clock signal, and the third end of the trigger circuit is used to output the target random number according to the change time of the clock signal and the output value of the comparison circuit.

5. The random number generating circuit according to any one of claims 1 to 4, characterized in that: The random number generation circuit also includes a current output circuit; The current output circuit is connected to the memristor circuit and is used to output a current current value corresponding to the memristor circuit.

6. The random number generating circuit according to claim 4, characterized in that: The random number generation circuit also includes a current output circuit; the current output circuit includes a digital-to-analog conversion circuit and a successive approximation circuit, wherein: In the current reading mode, the first end of the digital-to-analog conversion circuit is connected to the first end of the successive approximation circuit, and the second end of the digital-to-analog conversion circuit is connected to the second end of the comparison circuit; The third terminal of the comparison circuit is connected to the second terminal of the successive approximation circuit in the current reading mode; The third terminal of the successive approximation circuit is used to output the current value of the memristor circuit.

7. A circuit control method, characterized in that: The method is used to control the random number generation circuit according to any one of claims 1 to 6, and the method comprises: According to the current resistance state of the memristor circuit, controlling at least one capacitor subcircuit in the capacitor array circuit to be connected to the memristor circuit, and controlling the remaining capacitor subcircuits to be disconnected from the memristor circuit; A first reading voltage is input to the memristor circuit, and a target random number is output through the random number output circuit.

8. The circuit control method according to claim 7, characterized in that: The method further comprises: In the current reading mode, a second reading voltage is input to the memristor circuit, and a current current value corresponding to the memristor circuit is output through the current output circuit.

9. The circuit control method according to claim 8, characterized in that: According to the current resistance state of the memristor circuit, controlling at least one capacitor subcircuit in the capacitor array circuit to be connected to the memristor circuit comprises: Determining a current resistance state of the memristor circuit according to a current current value corresponding to the memristor circuit; Determining the at least one capacitor subcircuit from the capacitor array circuit according to the current resistance state; The at least one capacitor subcircuit is controlled to be connected to the memristor circuit.

10. A storage and computing integrated chip, characterized in that: The integrated storage and computing chip includes the random number generation circuit as described in any one of claims 1-6; the integrated storage and computing chip also includes a processor and a memory, a computer program is stored in the memory, and when the processor executes the computer program, it implements the circuit control method as described in any one of claims 7-9.

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