A channel management module based on embedded CPU

Abstract

The present invention relates to a channel management module based on an embedded CPU, comprising: an optical fiber interface for receiving component downlink optical fiber data; a system control unit for parsing data from multiple input optical fibers and packaging and sending the data to the embedded CPU in the form of an interrupt; the embedded CPU for receiving data transmitted from an FPGA according to an interrupt instruction and performing corresponding processing based on the system operating mode; a network interface for transmitting channel calibration results and component bit information (BITs) over the network according to the system operating mode; and embedded CPU software for receiving data transmitted from the FPGA according to an interrupt instruction, parsing the data, and determining the system operating mode. Leveraging the strong FPGA interface capabilities and flexible CPU processing, the present invention meets the functional requirements of channel management, encompassing tasks such as component bit information packaging and outbound transmission and channel calibration processing, meeting the application needs of various phased array antennas.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a channel management module based on an embedded CPU. Background Art

[0002] Phased array radar antennas consist of multiple antenna elements, which can be arranged in various configurations, such as linear, planar, spherical, cylindrical, and conformal surfaces, depending on the system design. By controlling the phase of the transmitted signal from each antenna element, energy can be transmitted in a specific direction. Similarly, by controlling the phase of the received signal from each antenna element, energy reflected from a specific direction can be received. The quality of each antenna element ultimately affects the quality of the transmit and receive lobes. To ensure the quality of these lobes, the operating conditions of each channel must be managed.

[0003] Phased array radar antennas vary in size, from as small as a few dozen antenna elements to as large as tens or even hundreds of thousands, depending on system requirements. Each antenna element corresponds to a single channel. The large number of antenna elements in large phased array radar antennas, and consequently, a large number of channels, poses challenges in channel management. Therefore, it is necessary to design a channel management module that can meet the requirements of managing tens to hundreds of thousands of channels and enable real-time monitoring of each channel's operating status. Summary of the Invention

[0004] In order to solve the existing technical problems, the present invention provides a channel management module based on an embedded CPU.

[0005] The specific content of the present invention is as follows: A channel management module based on an embedded CPU, comprising:

[0006] Optical fiber interface, receiving the downlink optical fiber data of the component;

[0007] The system control unit parses the data of multiple input optical fibers and sends them in the form of interrupts to the embedded CPU;

[0008] The embedded CPU receives data transmitted from the FPGA according to the interrupt instruction and completes the corresponding processing according to the system working mode;

[0009] The network interface completes the network transmission of channel calibration results and component BIT according to the system working mode;

[0010] The embedded CPU software receives data transmitted from the FPGA according to the interrupt instructions, completes data analysis, and determines the system working mode.

[0011] Furthermore, the optical fiber data includes timing, control words, channel data and component BIT data.

[0012] Furthermore, the embedded CPU completes the channel calibration processing of multiple channels and the packaging of channel calibration results in the channel calibration working mode; completes the real-time packaging of component BIT data of multiple components in the component BIT forwarding working mode; and completes the periodic packaging of component BIT data of multiple components in the normal system working mode.

[0013] Furthermore, the working process includes: determining the maximum number of receivable optical fibers of the optical fiber interface according to the bandwidth of the data to be processed and the transmission bandwidth of the network;

[0014] The optical fiber interface receives optical fiber data of multiple optical fibers input externally in real time. The system control unit parses the data of the multiple input optical fibers to obtain timing, control words, channel data, and component BIT data.

[0015] Furthermore, in the system channel calibration working mode, the system control unit intercepts a portion of the channel data of each input channel, and generates an interrupt signal based on the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

[0016] Furthermore, in the system component BIT forwarding working mode, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and component BIT data transmitted by the FPGA into the local memory, and re-packages the component BIT data before sending it; all packaged and sent data are output through the network interface.

[0017] Furthermore, in the normal operating mode of the system, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, and stores the control word and component BIT data transmitted by the FPGA into the local memory. The input is scheduled by frame, and the output is cyclical. There are multiple frames input in one cycle, and only the component BIT data of the last frame in the cycle is re-packaged and sent; all packaged and sent data are output through the network interface.

[0018] Furthermore, the output is performed with a period of 3 seconds.

[0019] The present invention's embedded CPU-based channel management module and method utilizes a designed channel management processing architecture. Leveraging the strong FPGA interface capabilities and flexible CPU processing, it fulfills the functional requirements of channel management, encompassing tasks such as component BIT packaging and outbound transmission and channel calibration. Flexible additions and subtractions can be made to meet the application requirements of various phased array antennas. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram of the channel management architecture based on the embedded CPU of the present invention;

[0022] Figure 2 This is the channel management software architecture of the embedded CPU of the present invention. DETAILED DESCRIPTION

[0023] Combine Figure 1 and Figure 2 The present invention provides a channel management module and method based on an embedded CPU, comprising:

[0024] Optical fiber interface 1 is used to receive the downlink optical fiber data of the component, which includes timing, control words, channel data, component BIT data, etc.

[0025] System control unit 2 completes the analysis of multiple input optical fiber data, parses the timing, control word, channel data, component BIT data, etc. from each optical fiber, and packages and sends them to the embedded CPU 3 in the form of interrupts;

[0026] Embedded CPU3 receives data transmitted from the FPGA based on interrupt instructions and performs corresponding processing based on the system operating mode. In channel calibration mode, it completes multi-channel channel calibration and packages the channel calibration results. In component BIT forwarding mode, it packages component BIT data from multiple components in real time. In normal system operation mode, it completes periodic packaging of component BIT data from multiple components.

[0027] Network interface 4, according to the system working mode, completes the network transmission of channel calibration results and component BIT;

[0028] Embedded CPU software 5, based on interrupt instructions, receives data transmitted from the FPGA, performs data parsing, and determines the system operating mode. In channel calibration mode, it completes multi-channel channel calibration and packages the channel calibration results. In component BIT forwarding mode, it packages component BIT data from multiple components in real time. In normal system operation mode, it completes periodic packaging of component BIT data from multiple components.

[0029] The implementation method and steps of this architecture are as follows:

[0030] The maximum number of optical fibers that can be received by the optical fiber interface 1 is determined according to the bandwidth of the data to be processed and the transmission bandwidth of the network.

[0031] The optical fiber interface 1 receives optical fiber data from multiple external optical fibers in real time (the number of optical fibers varies according to the array scale). The system control unit 2 parses the data from the multiple input optical fibers to extract timing, control words, channel data, and component BIT data.

[0032] In the system channel calibration working mode, the system control unit 2 intercepts a part of the channel data of each input channel, and generates an interrupt signal according to the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU3. The embedded CPU software 5 running in the embedded CPU3 receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

[0033] In the system component BIT forwarding mode, system control 2 generates an interrupt signal based on a timing signal, which packages the control word and component BIT data to embedded CPU 3 in the form of an interrupt. Embedded CPU software 5 running in embedded CPU 3 receives the interrupt command, stores the control word and component BIT data transmitted by the FPGA in local memory, and repackages the component BIT data before sending it. All packaged and transmitted data is output through network interface 4.

[0034] In normal system operation mode, the system control unit 2 generates an interrupt signal based on the timing signal, which packages the control word and component BIT data to the embedded CPU 3 in the form of an interrupt. Embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction and stores the control word and component BIT data transmitted by the FPGA in local memory. In this mode, input is scheduled on a frame basis, and output is performed in a 3-second cycle. Multiple frames may be input within a 3-second cycle, and only the component BIT data of the last frame within the 3-second cycle is repackaged and sent.

[0035] All data sent in packets are output via network interface 4.

[0036] In order to further illustrate the specific implementation of the present invention, an example of a channel management module and method based on an embedded CPU is given.

[0037] In this example, fiber optic interface 1 has 16 input fibers. The data packaged in these fibers includes control words, component bits, and channel data. Each input fiber packages 16 channels, for a total of 256 channels. The component bit data packaged in each input fiber is 64 x 32 bits. Fiber input data is scheduled in frames, with a frame period of 64 ms.

[0038] In channel calibration mode, fiber interface 1 receives data from 16 optical fibers. System control unit 2 parses each input fiber data, extracting control words, component bits, and channel data. After parsing a complete frame period of data, it generates an interrupt signal to embedded CPU 3 and sends the parsed control words and channel data to embedded CPU 3. Embedded CPU software 5, running within embedded CPU 3, receives the interrupt and stores the control words and channel data transmitted by system control 2 in local memory. Embedded CPU software 5 calibrates each channel according to the control requirements in the control words and then sends the calibration results to network interface 4 for transmission. The total amount of data transmitted is 16,384 x 32 bits.

[0039] In the component BIT forwarding mode, the fiber optic interface 1 receives data from 16 optical fibers, and the system control unit 2 parses each input fiber optic data to parse out the control word, component BIT, and channel data. After parsing a complete frame cycle of data, an interrupt signal is generated to the embedded CPU 3, and the parsed control word and component BIT data are sent to the embedded CPU 3. After the embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, it stores the control word and component BIT data sent by the system control unit 2 in the local memory. The embedded CPU software 5 packages the component BIT according to the control requirements in the control word and sends the component BIT data to the network interface 4 for transmission through the network interface 4. In the component BIT forwarding mode, data is scheduled by frame, and component BIT data is sent in each frame. The total amount of data sent in each frame is: 1024*32bit.

[0040] In the normal operating mode of the system, the optical fiber interface 1 receives data from 16 optical fibers, and the system control unit 2 parses each input optical fiber data to parse out the control word, component BIT, and channel data. After parsing the data of each complete frame period, an interrupt signal is generated to the embedded CPU 3, and the parsed control word and component BIT data are sent to the embedded CPU 3. After the embedded CPU software 5 running in the embedded CPU 3 receives the interrupt instruction, it stores the control word and channel data sent by the system control unit 2 into the local memory. The input in this mode is scheduled by frame, and the output is performed in a 3s cycle. There will be multiple frames input within a 3s cycle, and only the component BIT data of the last frame within the 3s cycle will be repackaged, and the repackaged component BIT data will be sent to the network interface 4 and sent through the network interface 4. The total amount of data sent each time is: 1024*32bit.

[0041] The channel management module of the present invention can be expanded according to demand, and the system is highly flexible, solving the engineering problem of channel management for large phased array antennas. It uses an FPGA with an embedded CPU, eliminating the need for additional hardware and effectively reducing design costs. It uses a standard gigabit network to send data, facilitating access by other systems.

[0042] In the above description, many specific details are set forth in order to fully understand the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A channel management module based on an embedded CPU, characterized by: include: Fiber optic interface, receiving downlink fiber optic data from components; fiber optic data includes timing, control words, channel data and component BIT data; The system control unit parses the data of multiple input optical fibers and sends them in the form of interrupts to the embedded CPU; The embedded CPU receives data transmitted from the FPGA according to the interrupt instruction and completes the corresponding processing according to the system working mode; The network interface completes the network transmission of channel calibration results and component BIT according to the system working mode; The embedded CPU software receives data transmitted from the FPGA according to the interrupt instructions, completes data analysis, and determines the system working mode; In the channel calibration working mode, the embedded CPU completes the channel calibration processing of multiple channels and the packaging of channel calibration results; in the component BIT forwarding working mode, it completes the real-time packaging of component BIT data of multiple components; in the normal working mode of the system, it completes the periodic packaging of component BIT data of multiple components.

2. The channel management module based on the embedded CPU according to claim 1, characterized in that: The working process includes: determining the maximum number of optical fibers that can be received by the optical fiber interface based on the bandwidth of the data to be processed and the transmission bandwidth of the network; The optical fiber interface receives optical fiber data of multiple optical fibers input externally in real time. The system control unit parses the data of the multiple input optical fibers to obtain timing, control words, channel data, and component BIT data.

3. The channel management module based on the embedded CPU according to claim 2, characterized in that: In the system channel calibration working mode, the system control unit intercepts a part of the channel data of each input channel, and generates an interrupt signal according to the timing signal, and packages the control word and the intercepted channel data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and channel data transmitted by the FPGA into the local memory, performs channel calibration on the channel data, and packages the channel calibration results and sends them.

4. The channel management module based on the embedded CPU according to claim 2, characterized in that: In the system component BIT forwarding working mode, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction, stores the control word and component BIT data transmitted by the FPGA into the local memory, and re-packages the component BIT data before sending it; all packaged and sent data are output through the network interface.

5. The channel management module based on the embedded CPU according to claim 2, characterized in that: In the normal working mode of the system, the system control unit generates an interrupt signal based on the timing signal, and packages the control word and component BIT data in the form of an interrupt and sends them to the embedded CPU. The embedded CPU software running in the embedded CPU receives the interrupt instruction and stores the control word and component BIT data sent by the FPGA into the local memory. The input is scheduled by frame and the output is cyclical. There are multiple frames input in one cycle, and only the component BIT data of the last frame in the cycle is re-packaged and sent; all packaged and sent data are output through the network interface.

6. The channel management module based on embedded CPU according to claim 5, characterized in that: The output is performed in a cycle of 3s.

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