Depletion type GaN device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly discloses a depletion type GaN device and a preparation method thereof.The depletion type GaN device comprises a source electrode, a drain electrode, a gate electrode, a plurality of gate structures, a field plate unit, a gate connecting assembly, a field plate connecting assembly, a gate driving resistor, a field plate driving resistor, a first dielectric layer and a second dielectric layer; the field plate unit comprises a plurality of field plates; one end of each of the plurality of gate structures is electrically connected with one end of the gate connecting assembly, and the other end of the gate connecting assembly is electrically connected with one end of the gate driving resistor; one end of each of a plurality of field plates of the field plate unit is connected with one end of the field plate connecting assembly, and the other end of the field plate connecting assembly is electrically connected with one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel with the gate electrode. According to the depletion type GaN device, the gate structure and the field plate unit are respectively provided with respective driving loops, so that voltage division adjustment is facilitated.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a depletion-mode GaN device and a preparation method thereof. Background Art

[0002] Cascaded GaN devices use depletion-mode GaN devices and low-voltage MOS for cascade connection. They have high reliability and are currently widely used in various types of switching power supplies. However, since the gate electrode of the depletion-mode GaN is often directly connected to the source electrode of the device during packaging, it is not easy to adjust. As a result, the device can only adjust the switching speed through the gate drive resistor of the low-voltage MOS in the application, and the adjustment ability is weak. Therefore, in practical applications, cascaded GaN devices are often prone to the problem of too fast switching speed, which makes it difficult to adjust electromagnetic interference EMI, and in severe cases, it will cause waveform oscillation and even crash.

[0003] In response to this problem, the industry has proposed designing a driving resistor at the GaN gate end to reduce the switching speed; or designing it as a two-way parallel connection, one is a diode and a relatively low resistor in series, and the other is a relatively high resistor, to achieve separate adjustment of the GaN turn-on and turn-off speeds. However, high-voltage depletion-mode GaN devices have gates and multiple field plates, which is equivalent to multiple depletion-mode devices with different thresholds connected in series, where the gates of each device are short-circuited together. When the driving resistance of the GaN device is increased, the charging and discharging speed of the capacitance of each series depletion-mode device will be reduced; but due to the difference in capacitance of each series device, the actual switching speed will be greatly different, which will further lead to hidden dangers such as uneven voltage division of several depletion-mode devices, excessive voltage division at the turn-off moment of low-voltage MOS devices, and large switching losses. Summary of the invention

[0004] In view of this, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a depletion-mode GaN device and a method for preparing the same, by designing respective drive circuits for the gate structure and the field plate unit to achieve refined adjustment of the switching speed and the shutdown speed, facilitate voltage division adjustment, and improve the reliability of the device.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: A depletion-mode GaN device, comprising a source electrode, a drain electrode, a gate electrode, a gate structure, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistor, a field plate drive resistor, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, wherein the gate structure is located in the first dielectric layer, the field plate unit is located in the second dielectric layer, a plurality of gate structures are provided, the field plate unit includes a plurality of field plates, and the number of field plates in the field plate unit is equal to the number of gate structures; One end of each of the plurality of gate structures is electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor; one end of each of the plurality of field plates in the field plate unit is electrically connected to one end of the field plate connection component, and the other end of the field plate connection component is electrically connected to one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel to the gate electrode.

[0006] According to some preferred implementation aspects of the present invention, the resistance of the gate driving resistor is less than or equal to the resistance of the field plate driving resistor.

[0007] According to some preferred embodiments of the present invention, the stacked structure includes a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer from bottom to top, and the barrier layer and the cap layer are provided with a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal and a fourth ohmic metal, the first ohmic metal and the second ohmic metal are respectively located on both sides of the gate drive resistor, and the third ohmic metal and the fourth ohmic metal are respectively located on both sides of the field plate drive resistor.

[0008] According to some preferred implementation aspects of the present invention, it also includes a fifth ohmic metal and a Schottky metal, the field plate driving resistor includes a first resistor portion and a second resistor portion connected to each other, the fifth ohmic metal and the Schottky metal are both located in the barrier layer and the cap layer, the fourth ohmic metal is located on the side of the first resistor portion away from the second resistor portion, the third ohmic metal is electrically connected to the fifth ohmic metal or the Schottky metal, the Schottky metal is used to form a diode, and the diode is connected in parallel with the second resistor portion. In some embodiments of the present invention, the first resistor portion is connected in series with the second resistor portion, the Schottky metal is used to form a diode structure, and the diode is connected in parallel with the second resistor portion. Such a setting makes it possible for the driving current of the field plate to flow through the second resistor portion of the field plate driving resistor when the depletion-type GaN device is turned on, and the driving current of the field plate flows through the diode when the device is turned off, which can make the turn-off speed faster and more suitable for flyback applications. In addition, in some other embodiments of the present invention, the direction of the diode can be set to be opposite, so that the device can be turned on faster and more suitable for high-power half-bridge circuits.

[0009] According to some preferred implementation aspects of the present invention, it further includes a gate drive circuit connection segment and a field plate drive circuit connection segment, and the source electrode, the drain electrode, the gate drive circuit connection segment and the field plate drive circuit connection segment are all located above the second dielectric layer.

[0010] According to some preferred implementation aspects of the present invention, a first metal connecting strip and a second metal connecting strip are provided in the first dielectric layer and the second dielectric layer, one end of the first metal connecting strip is connected to the source electrode, the other end of the first metal connecting strip is connected to the ohmic metal of the source electrode, one end of the second metal connecting strip is connected to the drain electrode, and the other end of the second metal connecting strip is connected to the ohmic metal of the drain electrode. In some embodiments of the present invention, the first metal connecting strip is electrically connected to the source electrode and the ohmic metal of the source electrode, and the second metal connecting strip is electrically connected to the drain electrode and the ohmic metal of the drain electrode.

[0011] According to some preferred implementation aspects of the present invention, the gate connection assembly includes a gate connection terminal, a gate connection segment and a plurality of first connection segments, one end of the gate connection segment is connected to the gate connection terminal, the plurality of first connection segments are respectively arranged in one-to-one correspondence with the plurality of gate structures, one end of each of the first connection segments is connected to a corresponding gate structure, the other end of each of the first connection segments is connected to the gate connection segment, and the gate connection segment and the plurality of first connection segments are used to connect the plurality of gate structures in parallel; The field plate connection assembly includes a field plate connection terminal, a field plate connection segment, and a plurality of second connection segments, one end of the field plate connection segment is connected to the field plate connection terminal, the plurality of second connection segments are respectively arranged in one-to-one correspondence with the plurality of field plates in the field plate unit, one end of each of the second connection segments is connected to a corresponding field plate, the other end of each of the second connection segments is connected to the field plate connection segment, and the field plate connection segment and the plurality of second connection segments are used to connect the plurality of field plates in the field plate unit in parallel.

[0012] According to some preferred implementation aspects of the present invention, the gate connection terminal is located in the first dielectric layer, and a third metal connection strip and a fourth metal connection strip are provided in the first dielectric layer and the second dielectric layer, one end of each of the third metal connection strip and the fourth metal connection strip is connected to the gate drive circuit connection segment, the other end of the third metal connection strip is connected to the gate connection terminal, and the other end of the fourth metal connection strip is connected to the first ohmic metal. In some embodiments of the present invention, the third metal connection strip is electrically connected to the gate drive circuit connection segment and the gate connection terminal, and the fourth metal connection strip is also electrically connected to the gate drive circuit connection segment and the first ohmic metal.

[0013] According to some preferred implementation aspects of the present invention, the field plate connection terminal is located in the second dielectric layer, and a fifth metal connection strip and a sixth metal connection strip are provided in the first dielectric layer and the second dielectric layer, one end of each of the fifth metal connection strip and the sixth metal connection strip is connected to the field plate drive circuit connection section, the other end of the fifth metal connection strip is connected to the field plate connection terminal, and the other end of the sixth metal connection strip is connected to the third ohmic metal. In some embodiments of the present invention, the fifth metal connection strip is electrically connected to the field plate drive circuit connection section and the field plate connection terminal, and the sixth metal connection strip is also electrically connected to the field plate drive circuit connection section and the third ohmic metal.

[0014] According to some preferred implementation aspects of the present invention, the first ohmic metal is located on a side of the gate drive resistor close to the gate connection terminal, the third ohmic metal is located on a side of the field plate drive resistor close to the field plate connection terminal, the second ohmic metal is provided with a first extension section at one end away from the gate drive resistor, the fourth ohmic metal is provided with a second extension section at one end away from the field plate drive resistor, and one end of the first extension section and the second extension section are both connected to the gate electrode. In some embodiments of the present invention, the second ohmic metal and the fourth ohmic metal are connected in parallel by providing the first extension section and the second extension section.

[0015] According to some preferred implementation aspects of the present invention, a plurality of field plate units are provided, a plurality of second dielectric layers are provided, and a field plate unit is provided in each second dielectric layer; the field plate driving resistor, the field plate connecting component and the field plate driving circuit connecting section are all provided in a one-to-one correspondence with the field plate units.

[0016] According to some preferred implementation aspects of the present invention, the resistance of the gate drive resistor is less than or equal to the resistance of the field plate drive resistor corresponding to the field plate unit located in a second dielectric layer close to the first dielectric layer, and the resistance of the field plate drive resistor corresponding to each field plate unit located in each layer of the second dielectric layer gradually increases from a second dielectric layer close to the first dielectric layer to a second dielectric layer away from the first dielectric layer.

[0017] The present invention also provides a method for preparing the above-mentioned depletion-mode GaN device, comprising the following steps: An active area, a gate drive resistor, and a field plate drive resistor are formed on the stacked structure through photoresist protection; or, an active area, a gate drive resistor, a field plate drive resistor, and a diode injection protection area are formed; wherein the diode injection protection area is provided for the subsequent formation of a Schottky metal equivalent to a diode.

[0018] Forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, and a fourth ohmic metal over the stacked structure; or forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, a fourth ohmic metal, a fifth ohmic metal, and a Schottky metal; Filling metal on the stacked structure and etching to form a gate structure and a gate connection component; depositing a first dielectric layer over the gate structure, and forming a field plate and a field plate connection assembly over the first dielectric layer; Depositing a second dielectric layer above the field plate, etching through holes downward from the second dielectric layer and filling them with metal to form a first metal connecting bar, a second metal connecting bar, a third metal connecting bar, a fourth metal connecting bar, a fifth metal connecting bar and a sixth metal connecting bar; A source electrode, a drain electrode, a gate drive circuit connection section and a field plate drive circuit connection section are formed on the second dielectric layer to obtain the depletion-mode GaN device. The gate drive circuit connection section is used to connect the third metal connection bar and the fourth metal connection bar; the field plate drive circuit connection section is used to connect the fifth metal connection bar and the sixth metal connection bar.

[0019] Due to the adoption of the above technical scheme, compared with the prior art, the benefits of the present invention are as follows: a depletion-type GaN device and a preparation method thereof of the present invention, by electrically connecting one end of the gate drive resistor to the gate structure, and connecting the other end of the gate drive resistor to the gate electrode; and electrically connecting one end of the field plate drive resistor to the field plate in the field plate unit, and connecting the other end of the field plate drive resistor to the gate electrode, and both the gate drive resistor and the field plate drive resistor are connected in parallel with the gate electrode. Such a structural design is equivalent to designing different drive circuits for the gate structure and the field plate unit respectively, which is convenient for voltage division adjustment, thereby facilitating the voltage division control of the low-voltage MOS device to a safe range, while extending the turn-on time and shortening the turn-off time, being particularly suitable for flyback circuits, etc., and is conducive to improving EMI without causing high turn-off losses, improving a series of problems caused by excessively fast switching in practical applications, and effectively improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 Schematic diagram of the top view of the depletion-mode GaN device in the first embodiment of the present invention; Figure 2 for Figure 1 A schematic cross-sectional view along the dotted line A; Figure 3 for Figure 1 A schematic cross-sectional view along the dashed line B; Figure 4 for Figure 1 A schematic cross-sectional view along the dashed line C; Figure 5 for Figure 1 A schematic cross-sectional view along the dashed line D; Figure 6 Schematic diagram of the top view of the depletion-mode GaN device in the second embodiment of the present invention; Figure 7 for Figure 6 A schematic cross-sectional view along the dashed line E; Figure 8 Schematic diagram of the top view of the depletion-mode GaN device in the third embodiment of the present invention; Fig. 9 for Figure 8 A schematic cross-sectional view along the dashed line F; Fig.10 is an equivalent circuit diagram of a depletion-mode GaN device in Embodiment 1 of the present invention; Fig.11 is an equivalent circuit diagram of a depletion-mode GaN device in Embodiment 2 of the present invention; Fig.12 is an equivalent circuit diagram of a depletion-mode GaN device in Embodiment 3 of the present invention; Fig.13 A diagram showing the relationship between the voltage division of each structure and the driving resistance in the first embodiment of the present invention; Wherein, the accompanying drawings are marked as follows: Substrate-1, stacked structure-2, nucleation layer-3, buffer layer-4, channel layer-5, barrier layer-6, cap layer-7, first dielectric layer-8, second dielectric layer-9, source electrode-10, gate electrode-11, gate structure-12, field plate-13, gate drive resistor-14, field plate drive resistor-15, source electrode ohmic metal-16, drain electrode ohmic metal-17, first ohmic metal-18, second ohmic metal-19, third ohmic metal-20, fourth ohmic metal-21, fifth ohmic metal-22, Schottky metal-23, first metal connecting strip-24, A third metal connecting strip-25, a fourth metal connecting strip-26, a fifth metal connecting strip-27, a sixth metal connecting strip-28, a gate drive circuit connecting section-29, a field plate drive circuit connecting section-30, a gate connecting terminal-31, a gate connecting section-32, a first connecting section-33, a field plate connecting terminal-34, a field plate connecting section-35, a second connecting section-36, a first extension section-37, a second extension section-38, a diode injection protection section-39, an active area-40, a second metal connecting strip-41, a drain electrode-42, a first resistor part-R1, and a second resistor part-R2. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] The depletion-mode GaN device of the present invention comprises a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistor 14, a field plate drive resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a gate drive loop connection section 29, a field plate drive loop connection section 30, a first metal connection bar 24, a second metal connection bar 41, a third metal connection bar 25, a fourth metal connection bar 26, a fifth metal connection bar 27, a sixth metal connection bar 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, a plurality of gate structures 12 are provided, and the plurality of gate structures 12 are all located in the first dielectric layer 8; the field plate unit is located in the second dielectric layer 9, and the field plate unit includes a plurality of field plates 13, and the number of field plates 13 in the field plate unit is equal to the number of gate structures 12. One end of each of the multiple gate structures 12 is electrically connected to one end of a gate connection component, and the other end of the gate connection component is electrically connected to one end of a gate driving resistor 14; one end of each of the multiple field plates 13 in the field plate unit is electrically connected to one end of a field plate connection component, and the other end of the field plate connection component is electrically connected to one end of a field plate driving resistor 15; and the gate driving resistor 14 and the field plate driving resistor 15 are both connected in parallel to the gate electrode 11.

[0024] Furthermore, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7 which are arranged in sequence from bottom to top. Among them, the source electrode 10, the drain electrode 42, the gate drive circuit connection section 29 and the field plate drive circuit connection section 30 are all located above the second dielectric layer 9, the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20 and the fourth ohmic metal 21 are all located in the barrier layer 6 and the cap layer 7; the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate drive resistor 14, and the third ohmic metal 20 and the fourth ohmic metal 21 are respectively located on both sides of the field plate drive resistor 15.

[0025] Furthermore, the gate connection component includes a gate connection terminal 31, a gate connection segment 32 and a plurality of first connection segments 33, the gate connection terminal 31 is located in the first dielectric layer 8, one end of the gate connection segment 32 is connected to the gate connection terminal 31, the plurality of first connection segments 33 are respectively arranged in a one-to-one correspondence with the plurality of gate structures 12, one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32, and the gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. The field plate connection assembly includes a field plate connection terminal 34, a field plate connection segment 35, and multiple second connection segments 36. The field plate connection terminal 34 is located in the second dielectric layer 9. One end of the field plate connection segment 35 is connected to the field plate connection terminal 34. The multiple second connection segments 36 are respectively arranged in a one-to-one correspondence with the multiple field plates 13 in the field plate unit. One end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to the field plate connection segment 35. The field plate connection segment 35 and the multiple second connection segments 36 are used to connect the multiple field plates 13 in the field plate unit in parallel. The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection terminal 31, the third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection terminal 34, the second ohmic metal 19 is provided with a first extension section 37 at one end away from the gate driving resistor 14, and the fourth ohmic metal 21 is provided with a second extension section 38 at one end away from the field plate driving resistor 15, and one end of the first extension section 37 and the second extension section 38 are both connected to the gate electrode 11.

[0026] In addition, the first metal connecting strip 24 and the second metal connecting strip 41 are both located in the first dielectric layer 8 and the second dielectric layer 9, and the first metal connecting strip 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connecting strip 24 is connected to the source electrode 10, and the other end of the first metal connecting strip 24 is connected to the source electrode ohmic metal 16; the second metal connecting strip 41 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the second metal connecting strip 41 is connected to the drain electrode 42, and the other end of the second metal connecting strip 41 is connected to the drain electrode ohmic metal 17. The third metal connecting strip 25 and the fourth metal connecting strip 26 are also located in the first dielectric layer 8 and the second dielectric layer 9, and the third metal connecting strip 25 is located between the gate drive circuit connection section 29 and the gate connection terminal 31, one end of the third metal connecting strip 25 is connected to the gate drive circuit connection section 29, and the other end of the third metal connecting strip 25 is connected to the gate connection terminal 31; the fourth metal connecting strip 26 is located between the gate drive circuit connection section 29 and the first ohmic metal 18, one end of the fourth metal connecting strip 26 is connected to the gate drive circuit connection section 29, and the other end of the fourth metal connecting strip 26 is connected to the first ohmic metal 18. The fifth metal connecting strip 27 is located in the second dielectric layer 9, the sixth metal connecting strip 28 is located in the first dielectric layer 8 and the second dielectric layer 9, the fifth metal connecting strip 27 is located between the field plate drive circuit connection section 30 and the field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate drive circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; the sixth metal connecting strip 28 is located between the field plate drive circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate drive circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20.

[0027] In some embodiments of the present invention, the field plate unit can be set to one or more. When the field plate unit is set to multiple, the second dielectric layer 9 is also provided with multiple layers, and a field plate unit is provided in each second dielectric layer 9, and the field plate driving resistor 15, the field plate connecting component and the field plate driving circuit connecting section 30 are all provided one-to-one with the field plate units.

[0028] In other embodiments of the present invention, regardless of whether one or more field plate units are provided, the depletion-mode GaN device may further include a fifth ohmic metal 22 and a Schottky metal 23, the Schottky metal 23 is used to form a diode structure, the diode is connected in parallel with the second resistor R2, and the field plate driving resistor 15 at this time may be configured to include a first resistor R1 and a second resistor R2 connected. The fifth ohmic metal 22 and the Schottky metal 23 are both located in the barrier layer 6 and the cap layer 7, the fourth ohmic metal 21 is located on the side of the first resistor R1 away from the second resistor R2, the third ohmic metal 20 is electrically connected to the fifth ohmic metal 22 or the Schottky metal 23, and the second resistor R2 is connected in parallel with the Schottky metal 23.

[0029] Embodiment 1 Device structure like Figures 1 to 5 As shown, the depletion-mode GaN device in this embodiment includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistor 14, a field plate drive resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a gate drive loop connection segment 29, a field plate drive loop connection segment 30, a first metal connection strip 24, a second metal connection strip 41, a third metal connection strip 25, a fourth metal connection strip 26, a fifth metal connection strip 27, a sixth metal connection strip 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, there are multiple gate structures 12, and the multiple gate structures 12 are all located in the first dielectric layer 8; there are two field plate units in this embodiment, and the second dielectric layer 9 is provided with two layers, and the two field plate units are respectively located in the two second dielectric layers 9; each field plate unit includes multiple field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connecting component and the field plate driving loop connecting section 30 are all arranged in a one-to-one correspondence with the field plate unit.

[0030] Furthermore, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7 arranged in sequence from bottom to top; the source electrode 10, the drain electrode 42, the gate drive circuit connection section 29 and the field plate drive circuit connection section 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20 and the fourth ohmic metal 21 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate drive resistor 14, and a third ohmic metal 20 and a fourth ohmic metal 21 are respectively arranged on both sides of each field plate drive resistor 15.

[0031] Furthermore, the gate connection component includes a gate connection terminal 31, a gate connection segment 32 and a plurality of first connection segments 33, the gate connection terminal 31 is located in the first dielectric layer 8, one end of the gate connection segment 32 is connected to the gate connection terminal 31, and the plurality of first connection segments 33 are respectively arranged in a one-to-one correspondence with the plurality of gate structures 12, so that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32, and the gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection assembly includes a field plate connection terminal 34, a field plate connection segment 35, and multiple second connection segments 36. A field plate connection terminal 34 is located in a corresponding second dielectric layer 9, one end of the field plate connection segment 35 is connected to the field plate connection terminal 34, and the multiple second connection segments 36 are respectively arranged in a one-to-one correspondence with the multiple field plates 13 in each field plate unit, so that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the multiple second connection segments 36 are used to connect the multiple field plates 13 in the field plate unit in parallel.

[0032] The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection terminal 31, the third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection terminal 34, the second ohmic metal 19 is provided with a first extension section 37 at one end away from the gate driving resistor 14, and the fourth ohmic metal 21 is provided with a second extension section 38 at one end away from the field plate driving resistor 15. In this embodiment, there are two second extension sections 38, and one end of the first extension section 37 and the second extension section 38 are both connected to the gate electrode 11. In addition, in the present embodiment, the first metal connecting strip 24 and the second metal connecting strip 41 both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, and the first metal connecting strip 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connecting strip 24 is connected to the source electrode 10, and the other end of the first metal connecting strip 24 is connected to the source electrode ohmic metal 16; the second metal connecting strip 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connecting strip 41 is connected to the drain electrode 42, and the other end of the second metal connecting strip 41 is connected to the drain electrode ohmic metal 17.

[0033] The third metal connection bar 25 and the fourth metal connection bar 26 of this embodiment both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the third metal connection bar 25 is located between the gate drive circuit connection section 29 and the gate connection terminal 31, one end of the third metal connection bar 25 is connected to the gate drive circuit connection section 29, and the other end of the third metal connection bar 25 is connected to the gate connection terminal 31; the fourth metal connection bar 26 is located between the gate drive circuit connection section 29 and the first ohmic metal 18, one end of the fourth metal connection bar 26 is connected to the gate drive circuit connection section 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. Such a configuration enables one end of the gate drive resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate drive resistor 14 to be electrically connected to the gate electrode 11 through the first extension section 37.

[0034] In this embodiment, the other structures corresponding to a field plate unit in a second dielectric layer 9 located near the first dielectric layer 8 are set as follows: a fifth metal connecting strip 27 runs through the thickness direction of the two second dielectric layers 9, the fifth metal connecting strip 27 is located between a field plate drive circuit connection section 30 and a corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate drive circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate drive circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate drive circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20.

[0035] The other structures corresponding to a field plate unit located in a second dielectric layer 9 away from the first dielectric layer 8 are arranged as follows: a fifth metal connecting strip 27 runs through the thickness direction of the second dielectric layer 9 away from the first dielectric layer 8, the fifth metal connecting strip 27 is located between another field plate driving circuit connection section 30 and another corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate driving circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate driving circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate driving circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate driving resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate driving resistor 15 to be electrically connected to the gate electrode 11 through the second extension section 38.

[0036] Figure 1is a schematic diagram of a top view of the depletion-mode GaN device of this embodiment, Figure 1 The field plate driving resistor 15 close to the gate driving resistor 14 is the first field plate driving resistor 15. Figure 1 The field plate driving resistor 15 far away from the gate driving resistor 14 is the second field plate driving resistor 15, then the gate driving resistor 14 in this embodiment is less than or equal to the first field plate driving resistor 15, and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15. Among them, the gate driving resistor 14 is greater than or equal to 0.1Ω, preferably 0.1~5Ω, and the second field plate driving resistor 15 is less than or equal to 1000Ω, preferably 10~40Ω.

[0037] like Figure 1 and Fig.10 As shown, through the structural design of the depletion-mode GaN device in this embodiment, the gate structure 12 and the two field plate units have their own different driving circuits, which is convenient for voltage division adjustment, and can achieve voltage division control of the low-voltage MOS device to a safe range, while extending the turn-on time of the device and shortening the turn-off time; it is particularly suitable for flyback circuits, etc., which is beneficial to improving EMI without causing high turn-off losses.

[0038] Double pulse measurement simulation calculation is performed on each structure in the depletion-mode GaN device of this embodiment, and the voltage division of each structure is analyzed. Fig.13 As shown, it is a graph showing the relationship between the voltage division corresponding to the gate structure 12 and each field plate 13 in the two field plate units and the driving resistance, which is represented by Fig.13 It can be seen that in this embodiment, even if the gate structure 12 and the corresponding field plates 13 in the two field plate units use the same driving resistance, the change rules of the voltage division of each structure and the driving resistance show a more consistent corresponding relationship (linear relationship) rather than an irregular one, which is beneficial to the voltage division adjustment of each structure in the depletion-type GaN device.

[0039] In some other embodiments of the present invention, conventionally, the number of field plate units can be set to one, three or four, and the number of the second dielectric layer 9, the field plate driving resistor 15, the field plate connecting assembly and the field plate driving circuit connecting section 30 are all the same as the number of field plate units. In addition, the resistance of the gate driving resistor 14 is less than or equal to the resistance of the field plate driving resistor 15 corresponding to the field plate unit located in the second dielectric layer 9 closest to the first dielectric layer 8, and the resistance of the field plate driving resistor 15 corresponding to each field plate unit located in each second dielectric layer 9 gradually increases from the second dielectric layer 9 close to the first dielectric layer 8 to the second dielectric layer 9 far away from the first dielectric layer 8. And compared with two field plate units, the introduction of four field plate units is more conducive to the voltage division optimization of the device and improves the withstand voltage capability.

[0040] Embodiment 2 Device structure like Figure 6 and Figure 7 As shown, the depletion-mode GaN device in this embodiment includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistor 14, a field plate drive resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a fifth ohmic metal 22, a Schottky metal 23, a gate drive loop connection segment 29, a field plate drive loop connection segment 30, a first metal connection strip 24, a second metal connection strip 41, a third metal connection strip 25, a fourth metal connection strip 26, a fifth metal connection strip 27, a sixth metal connection strip 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, there are multiple gate structures 12, and the multiple gate structures 12 are all located in the first dielectric layer 8; there are two field plate units in this embodiment, and the second dielectric layer 9 is provided with two layers, and the two field plate units are respectively located in the two second dielectric layers 9; each field plate unit includes multiple field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connecting component and the field plate driving loop connecting section 30 are all arranged in a one-to-one correspondence with the field plate unit.

[0041] Furthermore, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7 arranged in sequence from bottom to top; the source electrode 10, the drain electrode 42, the gate drive circuit connection section 29 and the field plate drive circuit connection section 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21, the fifth ohmic metal 22 and the Schottky metal 23 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate drive resistor 14, and a third ohmic metal 20 and a fourth ohmic metal 21 are respectively arranged on both sides of each field plate drive resistor 15. In this embodiment, each field plate driving resistor 15 includes a first resistor portion R1 and a second resistor portion R2 connected to each other, the fourth ohmic metal 21 is located on a side of the first resistor portion R1 away from the second resistor portion R2, the third ohmic metal 20 is electrically connected to the fifth ohmic metal 22, and the second resistor portion R2 is connected in parallel to the Schottky metal 23.

[0042] Furthermore, the gate connection component includes a gate connection terminal 31, a gate connection segment 32 and a plurality of first connection segments 33, the gate connection terminal 31 is located in the first dielectric layer 8, one end of the gate connection segment 32 is connected to the gate connection terminal 31, and the plurality of first connection segments 33 are respectively arranged in a one-to-one correspondence with the plurality of gate structures 12, so that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32, and the gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection assembly includes a field plate connection terminal 34, a field plate connection segment 35, and multiple second connection segments 36. A field plate connection terminal 34 is located in a corresponding second dielectric layer 9, one end of the field plate connection segment 35 is connected to the field plate connection terminal 34, and the multiple second connection segments 36 are respectively arranged in a one-to-one correspondence with the multiple field plates 13 in each field plate unit, so that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the multiple second connection segments 36 are used to connect the multiple field plates 13 in the field plate unit in parallel.

[0043] The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection terminal 31, the third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection terminal 34, the second ohmic metal 19 is provided with a first extension section 37 at one end away from the gate driving resistor 14, and the fourth ohmic metal 21 is provided with a second extension section 38 at one end away from the field plate driving resistor 15. In this embodiment, there are two second extension sections 38, and one end of the first extension section 37 and the second extension section 38 are both connected to the gate electrode 11. In addition, in the present embodiment, the first metal connecting strip 24 and the second metal connecting strip 41 both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, and the first metal connecting strip 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connecting strip 24 is connected to the source electrode 10, and the other end of the first metal connecting strip 24 is connected to the source electrode ohmic metal 16; the second metal connecting strip 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connecting strip 41 is connected to the drain electrode 42, and the other end of the second metal connecting strip 41 is connected to the drain electrode ohmic metal 17.

[0044] The third metal connection bar 25 and the fourth metal connection bar 26 of this embodiment both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the third metal connection bar 25 is located between the gate drive circuit connection section 29 and the gate connection terminal 31, one end of the third metal connection bar 25 is connected to the gate drive circuit connection section 29, and the other end of the third metal connection bar 25 is connected to the gate connection terminal 31; the fourth metal connection bar 26 is located between the gate drive circuit connection section 29 and the first ohmic metal 18, one end of the fourth metal connection bar 26 is connected to the gate drive circuit connection section 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. Such a configuration enables one end of the gate drive resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate drive resistor 14 to be electrically connected to the gate electrode 11 through the first extension section 37.

[0045] In this embodiment, the other structures corresponding to a field plate unit in a second dielectric layer 9 located near the first dielectric layer 8 are set as follows: a fifth metal connecting strip 27 runs through the thickness direction of the two second dielectric layers 9, the fifth metal connecting strip 27 is located between a field plate drive circuit connection section 30 and a corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate drive circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate drive circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate drive circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20.

[0046] The other structures corresponding to a field plate unit located in a second dielectric layer 9 away from the first dielectric layer 8 are arranged as follows: a fifth metal connecting strip 27 runs through the thickness direction of the second dielectric layer 9 away from the first dielectric layer 8, the fifth metal connecting strip 27 is located between another field plate driving circuit connection section 30 and another corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate driving circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate driving circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate driving circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate driving resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate driving resistor 15 to be electrically connected to the gate electrode 11 through the second extension section 38.

[0047] Figure 6is a schematic diagram of a top view of the depletion-mode GaN device of this embodiment, Figure 6 The field plate driving resistor 15 close to the gate driving resistor 14 is the first field plate driving resistor 15. Figure 6 The field plate driving resistor 15 far away from the gate driving resistor 14 is the second field plate driving resistor 15 , and the gate driving resistor 14 in this embodiment is less than or equal to the first field plate driving resistor 15 , and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15 .

[0048] like Figure 6 and Fig.11 As shown, the first resistor R1 of each field plate driving resistor 15 in this embodiment is connected in series with the second resistor R2, and the setting of the Schottky metal 23 is equivalent to introducing a diode, and the diode is connected in parallel with the second resistor R2. Through the structural design of the depletion-type GaN device in this embodiment, the gate structure 12 and the two field plate units have their own different driving circuits, which is convenient for voltage division adjustment, and can achieve voltage division control of the low-voltage MOS device to a safe range, while extending the device's turn-on time and shortening the turn-off time; and this structure enables the driving current of the corresponding field plate 13 in each field plate unit to flow through the second resistor R2 when the GaN device is turned on, and the driving current flows through the diode when the device is turned off, which can make the turn-off speed faster and more suitable for flyback applications.

[0049] Example 3 Device Structure like Figure 8 and Fig. 9As shown, the depletion-mode GaN device in this embodiment is compared with that in Embodiment 2 in that the direction of the diode in this embodiment is opposite to that in Embodiment 2. Specifically, in this embodiment, the depletion-mode GaN device includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistor 14, a field plate drive resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a fifth ohmic metal 22, a Schottky metal 23, a gate drive loop connection section 29, a field plate drive loop connection section 30, a first metal connection bar 24, a second metal connection bar 41, a third metal connection bar 25, a fourth metal connection bar 26, a fifth metal connection bar 27, a sixth metal connection bar 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, there are multiple gate structures 12, and the multiple gate structures 12 are all located in the first dielectric layer 8; there are two field plate units in this embodiment, and the second dielectric layer 9 is provided with two layers, and the two field plate units are respectively located in the two second dielectric layers 9; each field plate unit includes multiple field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connecting component and the field plate driving loop connecting section 30 are all arranged in a one-to-one correspondence with the field plate unit.

[0050] Furthermore, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7 arranged in sequence from bottom to top; the source electrode 10, the drain electrode 42, the gate drive circuit connection section 29 and the field plate drive circuit connection section 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21, the fifth ohmic metal 22 and the Schottky metal 23 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate drive resistor 14, and a third ohmic metal 20 and a fourth ohmic metal 21 are respectively arranged on both sides of each field plate drive resistor 15. In this embodiment, each field plate driving resistor 15 includes a first resistor portion R1 and a second resistor portion R2 connected to each other, the fourth ohmic metal 21 is located on a side of the first resistor portion R1 away from the second resistor portion R2, the third ohmic metal 20 is electrically connected to the Schottky metal 23, the second resistor portion R2 is connected in parallel to the Schottky metal 23, and the positions of the fifth ohmic metal 22 and the Schottky metal 23 in this embodiment are opposite to those of the fifth ohmic metal 22 and the Schottky metal 23 in Example 2.

[0051] Furthermore, the gate connection component includes a gate connection terminal 31, a gate connection segment 32 and a plurality of first connection segments 33, the gate connection terminal 31 is located in the first dielectric layer 8, one end of the gate connection segment 32 is connected to the gate connection terminal 31, and the plurality of first connection segments 33 are respectively arranged in a one-to-one correspondence with the plurality of gate structures 12, so that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32, and the gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection assembly includes a field plate connection terminal 34, a field plate connection segment 35, and multiple second connection segments 36. A field plate connection terminal 34 is located in a corresponding second dielectric layer 9, one end of the field plate connection segment 35 is connected to the field plate connection terminal 34, and the multiple second connection segments 36 are respectively arranged in a one-to-one correspondence with the multiple field plates 13 in each field plate unit, so that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the multiple second connection segments 36 are used to connect the multiple field plates 13 in the field plate unit in parallel.

[0052] The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection terminal 31, the third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection terminal 34, the second ohmic metal 19 is provided with a first extension section 37 at one end away from the gate driving resistor 14, and the fourth ohmic metal 21 is provided with a second extension section 38 at one end away from the field plate driving resistor 15. In this embodiment, there are two second extension sections 38, and one end of the first extension section 37 and the second extension section 38 are both connected to the gate electrode 11. In addition, in the present embodiment, the first metal connecting strip 24 and the second metal connecting strip 41 both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, and the first metal connecting strip 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connecting strip 24 is connected to the source electrode 10, and the other end of the first metal connecting strip 24 is connected to the source electrode ohmic metal 16; the second metal connecting strip 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connecting strip 41 is connected to the drain electrode 42, and the other end of the second metal connecting strip 41 is connected to the drain electrode ohmic metal 17.

[0053] The third metal connection bar 25 and the fourth metal connection bar 26 of this embodiment both penetrate the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the third metal connection bar 25 is located between the gate drive circuit connection section 29 and the gate connection terminal 31, one end of the third metal connection bar 25 is connected to the gate drive circuit connection section 29, and the other end of the third metal connection bar 25 is connected to the gate connection terminal 31; the fourth metal connection bar 26 is located between the gate drive circuit connection section 29 and the first ohmic metal 18, one end of the fourth metal connection bar 26 is connected to the gate drive circuit connection section 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. Such a configuration enables one end of the gate drive resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate drive resistor 14 to be electrically connected to the gate electrode 11 through the first extension section 37.

[0054] In this embodiment, the other structures corresponding to a field plate unit in a second dielectric layer 9 located near the first dielectric layer 8 are set as follows: a fifth metal connecting strip 27 runs through the thickness direction of the two second dielectric layers 9, the fifth metal connecting strip 27 is located between a field plate drive circuit connection section 30 and a corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate drive circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate drive circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate drive circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20.

[0055] The other structures corresponding to a field plate unit located in a second dielectric layer 9 away from the first dielectric layer 8 are arranged as follows: a fifth metal connecting strip 27 runs through the thickness direction of the second dielectric layer 9 away from the first dielectric layer 8, the fifth metal connecting strip 27 is located between another field plate driving circuit connection section 30 and another corresponding field plate connection terminal 34, one end of the fifth metal connecting strip 27 is connected to the field plate driving circuit connection section 30, and the other end of the fifth metal connecting strip 27 is connected to the field plate connection terminal 34; a sixth metal connecting strip 28 runs through the thickness direction of the first dielectric layer 8 and the second dielectric layer 9, the sixth metal connecting strip 28 is located between the same field plate driving circuit connection section 30 and the third ohmic metal 20, one end of the sixth metal connecting strip 28 is connected to the gate driving circuit connection section 29, and the other end of the sixth metal connecting strip 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate driving resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate driving resistor 15 to be electrically connected to the gate electrode 11 through the second extension section 38.

[0056] Figure 8is a schematic diagram of a top view of the depletion-mode GaN device of this embodiment, Figure 8 The field plate driving resistor 15 close to the gate driving resistor 14 is the first field plate driving resistor 15. Figure 8 The field plate driving resistor 15 far away from the gate driving resistor 14 is the second field plate driving resistor 15 , and the gate driving resistor 14 in this embodiment is less than or equal to the first field plate driving resistor 15 , and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15 .

[0057] like Figure 8 and Fig.12 As shown, the first resistor R1 of each field plate driving resistor 15 in this embodiment is connected in series with the second resistor R2, and the setting of the Schottky metal 23 is equivalent to introducing a diode, and the diode is connected in parallel with the second resistor R2. Through the structural design of the depletion-type GaN device in this embodiment, the gate structure 12 and the two field plate units have their own different driving circuits, which is convenient for voltage division adjustment, and can achieve voltage division control of the low-voltage MOS device to a safe range, while extending the device's turn-on time and shortening the turn-off time; because the direction of the diode in this embodiment is opposite to that of the diode in Example 2, when the GaN device is turned on, the driving current of the corresponding field plate 13 in each field plate unit flows through the diode, and when it is turned off, the driving current flows through the second resistor R2, which is conducive to faster turn-on speed and is more suitable for high-power half-bridge circuits.

[0058] Example 4 Preparation method This embodiment provides a method for preparing the depletion-mode GaN device in the above-mentioned embodiment 1, which specifically includes the following steps: Step 1: Perform nitride epitaxial growth on substrate 1 to sequentially form a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7, wherein the materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 3, the buffer layer 4, the channel layer 5, the barrier layer 6 and the cap layer 7 constitute a stacked structure 2, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 5 and the barrier layer 6 to generate a conductive channel.

[0059] The substrate 1 is one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium or any other material capable of growing group III nitride materials.

[0060] Step 2: Through photoresist protection, patterning is performed on the cap layer 7 and ion materials are injected to destroy the two-dimensional electron gas to form an isolation area. The area that is not injected is protected as a continuous area chip active area 40 where the source electrode 10, the drain electrode 42, and the gate structure 12 exist, and a gate drive resistor 14 and two field plate drive resistors 15 are formed.

[0061] Step 3: Graphic etching is performed on the cap layer 7 to form the first ohmic hole and the second ohmic hole. At the same time, graphic etching is performed on both sides of the gate drive resistor 14 to form the third ohmic hole and the fourth ohmic hole. Graphic etching is performed on both sides of each field plate drive resistor 15 to form the fifth ohmic hole and the sixth ohmic hole.

[0062] Step 4: Fill the first ohmic hole, the second ohmic hole, the third ohmic hole, the fourth ohmic hole, the fifth ohmic hole and the sixth ohmic hole with metal to form the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18 and the second ohmic metal 19 on both sides of the gate drive resistor 14 (the second ohmic metal 19 forms the first extension section 37 on the side away from the first ohmic metal 18), and the third ohmic metal 20 and the fourth ohmic metal 21 on both sides of each field plate drive resistor 15 (the fourth ohmic metal 21 forms the second extension section 38 on the side away from the third ohmic metal 20), and perform annealing treatment. At this time, the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20 and the fourth ohmic metal 21 respectively form ohmic contacts with the epitaxial material below. The second ohmic metal 19 and the two fourth ohmic metals 21 are connected in parallel through the first extension section 37 and the second extension section 38 to form the gate electrode 11. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0063] Step 5: Fill metal on the cap layer 7 and etch to form a gate structure 12, wherein multiple gate structures 12 are connected in parallel, and then deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 on the gate structure 12 to form a first dielectric layer 8.

[0064] Step 6: Fill metal above the first dielectric layer 8 and etch to form a first field plate unit and a field plate connecting component, and at the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the first field plate unit to form a first second dielectric layer 9.

[0065] Step 7: Fill metal above the first second dielectric layer 9 and etch to form a second field plate unit and a field plate connecting component, and at the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate unit to form a second second dielectric layer 9.

[0066] Step 8: Etching from the second second dielectric layer 9 downward to the top of the source electrode ohmic metal 16 to form a first through hole and a second through hole, the first through hole and the second through hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etching from the second second dielectric layer 9 downward to the gate connection terminal 31 to form a third through hole, etching from the second second dielectric layer 9 downward to the first ohmic metal 18 to form a fourth through hole, the third through hole and the fourth through hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etching from the second second dielectric layer 9 downward to the field plate connection terminal 34 in the field plate connection component connected to the first field plate unit to form a fifth through hole, from The second second dielectric layer 9 is etched downward to the third ohmic metal 20 to form a sixth through hole, wherein the fifth through hole penetrates two second dielectric layers 9, and the sixth through hole penetrates the first dielectric layer 8 and two second dielectric layers 9; another fifth through hole is formed by etching downward from the second second dielectric layer 9 to the field plate connection terminal 34 in the field plate connection component connected to the second field plate unit, and another sixth through hole is formed by etching downward from the second second dielectric layer 9 to the third ohmic metal 20, wherein the fifth through hole here penetrates a second dielectric layer 9 away from the first dielectric layer 8, and the sixth through hole penetrates the first dielectric layer 8 and two second dielectric layers 9.

[0067] Step 9: Fill metal into the first through hole, the second through hole, the third through hole, the fourth through hole, the fifth through hole and the sixth through hole to form a first metal connecting bar 24, a second metal connecting bar 41, a third metal connecting bar 25, a fourth metal connecting bar 26, a fifth metal connecting bar 27 and a sixth metal connecting bar 28 respectively.

[0068] Step 10: Fill metal on the second dielectric layer 9 and etch to form a source electrode 10, a drain electrode 42, a gate drive circuit connection segment 29 and two field plate drive circuit connection segments 30, wherein the source electrode 10 is electrically connected to the first metal connection strip 24, the drain electrode 42 is electrically connected to the second metal connection strip 41, the gate drive circuit connection segment 29 is electrically connected to the third metal connection strip 25 and the fourth metal connection strip 26 to form a gate drive circuit, and each field plate drive circuit connection segment 30 is electrically connected to the corresponding fifth metal connection strip 27 and the sixth metal connection strip 28 to form a field plate drive circuit of each field plate unit, and finally a depletion-type GaN device is obtained.

[0069] Example 5 Preparation method This embodiment provides a method for preparing the depletion-mode GaN device in the above-mentioned embodiment 2, which specifically includes the following steps: Step 1: Perform nitride epitaxial growth on substrate 1 to sequentially form a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6 and a cap layer 7, wherein the materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 3, the buffer layer 4, the channel layer 5, the barrier layer 6 and the cap layer 7 constitute a stacked structure 2, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 5 and the barrier layer 6 to generate a conductive channel.

[0070] The substrate 1 is one or more combinations of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium or any other material capable of growing group III nitride materials.

[0071] Step 2: Through photoresist protection, patterning is performed on the cap layer 7 and ion materials are injected to destroy the two-dimensional electron gas to form an isolation area. The area that is not injected is protected to be the continuous area chip active area 40 where the source electrode 10, the drain electrode 42, and the gate structure 12 exist, and the gate drive resistor 14, two field plate drive resistors 15 and the diode injection protection area 39 are formed (to facilitate the subsequent formation of the diode).

[0072] Step 3: Graphic etching is performed on the cap layer 7 to form the first ohmic hole and the second ohmic hole. At the same time, graphic etching is performed on both sides of the gate drive resistor 14 to form the third ohmic hole and the fourth ohmic hole. Graphic etching is performed on both sides of each field plate drive resistor 15 to form the fifth ohmic hole and the sixth ohmic hole. Graphic etching is performed on both sides of the diode injection protection area 39 to form the seventh ohmic hole and the filling hole.

[0073] Step 4: Fill the first ohmic hole, the second ohmic hole, the third ohmic hole, the fourth ohmic hole, the fifth ohmic hole, the sixth ohmic hole and the seventh ohmic hole with metal to form the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18 and the second ohmic metal 19 on both sides of the gate drive resistor 14 (the second ohmic metal 19 forms the first extension section 37 on the side away from the first ohmic metal 18), and the third ohmic metal 20 and the fourth ohmic metal 21 on both sides of each field plate drive resistor 15 (the fourth ohmic metal 21 A second extension section 38 is formed on the side away from the third ohmic metal 20, and a fifth ohmic metal 22 is formed on the side of the diode injection protection zone 39, and annealing is performed. At this time, the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21 and the fifth ohmic metal 22 respectively form ohmic contacts with the epitaxial materials below them, and metal is further filled in the filling hole to form a Schottky metal 23, and no annealing is performed to form a Schottky contact. Among them, the second ohmic metal 19 and the two fourth ohmic metals 21 are connected in parallel through the first extension section 37 and the second extension section 38 to form a gate electrode 11. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0074] Step 5: Fill metal on the cap layer 7 and etch to form a gate structure 12, wherein multiple gate structures 12 are connected in parallel, and then deposit one or more combinations of SiN, SiO2, SiON, and Al2O3 on the gate structure 12 to form a first dielectric layer 8.

[0075] Step 6: Fill metal above the first dielectric layer 8 and etch to form a first field plate unit and a field plate connecting component, and at the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the first field plate unit to form a first second dielectric layer 9.

[0076] Step 7: Fill metal above the first second dielectric layer 9 and etch to form a second field plate unit and a field plate connecting component, and at the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit one or more combinations of SiN, SiO2, SiON, Al2O3 above the second field plate unit to form a second second dielectric layer 9.

[0077] Step 8: Etching from the second second dielectric layer 9 downward to the top of the source electrode ohmic metal 16 to form a first through hole and a second through hole, the first through hole and the second through hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etching from the second second dielectric layer 9 downward to the gate connection terminal 31 to form a third through hole, etching from the second second dielectric layer 9 downward to the first ohmic metal 18 to form a fourth through hole, the third through hole and the fourth through hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etching from the second second dielectric layer 9 downward to the field plate connection terminal 34 in the field plate connection component connected to the first field plate unit to form a fifth through hole, from The second second dielectric layer 9 is etched downward to the third ohmic metal 20 to form a sixth through hole, wherein the fifth through hole penetrates two second dielectric layers 9, and the sixth through hole penetrates the first dielectric layer 8 and two second dielectric layers 9; another fifth through hole is formed by etching downward from the second second dielectric layer 9 to the field plate connection terminal 34 in the field plate connection component connected to the second field plate unit, and another sixth through hole is formed by etching downward from the second second dielectric layer 9 to the third ohmic metal 20, wherein the fifth through hole here penetrates a second dielectric layer 9 away from the first dielectric layer 8, and the sixth through hole penetrates the first dielectric layer 8 and two second dielectric layers 9.

[0078] Step 9: Fill metal into the first through hole, the second through hole, the third through hole, the fourth through hole, the fifth through hole and the sixth through hole to form a first metal connecting bar 24, a second metal connecting bar 41, a third metal connecting bar 25, a fourth metal connecting bar 26, a fifth metal connecting bar 27 and a sixth metal connecting bar 28 respectively.

[0079] Step 10: Fill metal on the second dielectric layer 9 and etch to form a source electrode 10, a drain electrode 42, a gate drive circuit connection segment 29 and two field plate drive circuit connection segments 30, wherein the source electrode 10 is electrically connected to the first metal connection strip 24, the drain electrode 42 is electrically connected to the second metal connection strip 41, the gate drive circuit connection segment 29 is electrically connected to the third metal connection strip 25 and the fourth metal connection strip 26 to form a gate drive circuit, and each field plate drive circuit connection segment 30 is electrically connected to the corresponding fifth metal connection strip 27 and the sixth metal connection strip 28 to form a field plate drive circuit of each field plate unit, and finally a depletion-type GaN device is obtained.

[0080] The depletion-mode GaN device of the present invention is convenient for voltage division adjustment by designing different driving circuits for the gate structure 12 and the field plate unit, thereby facilitating voltage division control of the low-voltage MOS device to a safe range, while extending the turn-on time and shortening the turn-off time without causing high turn-off losses. This can improve a series of problems caused by excessively fast switching in practical applications and effectively improve the reliability of the device.

[0081] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A depletion-mode GaN device, characterized in that: The invention comprises a source electrode, a drain electrode, a gate electrode, a gate structure, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor, a field plate driving resistor, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, wherein the gate structure is located in the first dielectric layer, the field plate unit is located in the second dielectric layer, a plurality of gate structures are provided, the field plate unit includes a plurality of field plates, and the number of field plates in the field plate unit is equal to the number of gate structures; One end of each of the gate structures is electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor; One end of each of the field plates in the field plate unit is connected to one end of the field plate connecting component, and the other end of the field plate connecting component is electrically connected to one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel to the gate electrode.

2. A depletion-mode GaN device according to claim 1, characterized in that: The resistance of the gate driving resistor is less than or equal to the resistance of the field plate driving resistor.

3. A depletion-mode GaN device according to claim 2, characterized in that: The stacked structure includes a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer from bottom to top, wherein the barrier layer and the cap layer are provided with a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal and a fourth ohmic metal, wherein the first ohmic metal and the second ohmic metal are respectively located on both sides of the gate drive resistor, and the third ohmic metal and the fourth ohmic metal are respectively located on both sides of the field plate drive resistor.

4. A depletion-mode GaN device according to claim 3, characterized in that: It also includes a fifth ohmic metal and a Schottky metal, the field plate drive resistor includes a first resistor part and a second resistor part connected to each other, the fifth ohmic metal and the Schottky metal are both located in the barrier layer and the cap layer, the fourth ohmic metal is located on the side of the first resistor part away from the second resistor part, the third ohmic metal is electrically connected to the fifth ohmic metal or the Schottky metal, the Schottky metal is used to form a diode, and the diode is connected in parallel with the second resistor part.

5. A depletion-mode GaN device according to claim 3 or 4, characterized in that: It also includes a gate drive loop connection section and a field plate drive loop connection section. The source electrode, the drain electrode, the gate drive loop connection section and the field plate drive loop connection section are all located above the second dielectric layer.

6. A depletion-mode GaN device according to claim 5, characterized in that: A first metal connecting strip and a second metal connecting strip are provided in the first dielectric layer and the second dielectric layer, one end of the first metal connecting strip is connected to the source electrode, the other end of the first metal connecting strip is connected to the ohmic metal of the source electrode, one end of the second metal connecting strip is connected to the drain electrode, the other end of the second metal connecting strip is connected to the ohmic metal of the drain electrode.

7. A depletion-mode GaN device according to claim 6, characterized in that: The grid connection assembly comprises a grid connection terminal, a grid connection segment and a plurality of first connection segments, one end of the grid connection segment is connected to the grid connection terminal, the plurality of first connection segments are respectively arranged in one-to-one correspondence with the plurality of grid structures, one end of each of the first connection segments is connected to a corresponding grid structure, the other end of each of the first connection segments is connected to the grid connection segment, and the grid connection segment and the plurality of first connection segments are used to connect the plurality of grid structures in parallel; The field plate connection assembly includes a field plate connection terminal, a field plate connection segment, and a plurality of second connection segments, one end of the field plate connection segment is connected to the field plate connection terminal, the plurality of second connection segments are respectively arranged in one-to-one correspondence with the plurality of field plates in the field plate unit, one end of each of the second connection segments is connected to a corresponding field plate, the other end of each of the second connection segments is connected to the field plate connection segment, and the field plate connection segment and the plurality of second connection segments are used to connect the plurality of field plates in the field plate unit in parallel.

8. A depletion-mode GaN device according to claim 7, characterized in that: The gate connection terminal is located in the first dielectric layer, and a third metal connection bar and a fourth metal connection bar are arranged in the first dielectric layer and the second dielectric layer, one end of the third metal connection bar and the fourth metal connection bar are both connected to the gate drive circuit connection section, the other end of the third metal connection bar is connected to the gate connection terminal, and the other end of the fourth metal connection bar is connected to the first ohmic metal.

9. A depletion-mode GaN device according to claim 8, characterized in that: The field plate connection terminal is located in the second dielectric layer, and a fifth metal connection strip and a sixth metal connection strip are provided in the first dielectric layer and the second dielectric layer, one end of the fifth metal connection strip and the sixth metal connection strip are both connected to the field plate drive circuit connection section, the other end of the fifth metal connection strip is connected to the field plate connection terminal, and the other end of the sixth metal connection strip is connected to the third ohmic metal.

10. A depletion-mode GaN device according to claim 9, characterized in that: The first ohmic metal is located on a side of the gate driving resistor close to the gate connection terminal, the third ohmic metal is located on a side of the field plate driving resistor close to the field plate connection terminal, a first extension section is provided at one end of the second ohmic metal away from the gate driving resistor, a second extension section is provided at one end of the fourth ohmic metal away from the field plate driving resistor, and one end of each of the first extension section and the second extension section is connected to the gate electrode.

11. The depletion-mode GaN device according to claim 5, characterized in that: There are multiple field plate units, multiple layers of the second dielectric layer, and one field plate unit is disposed in each of the second dielectric layers; the field plate driving resistor, the field plate connecting component and the field plate driving loop connecting section are all disposed in one-to-one correspondence with the field plate units.

12. A depletion-mode GaN device according to claim 11, characterized in that: The resistance of the gate drive resistor is less than or equal to the resistance of the field plate drive resistor corresponding to the field plate unit located in a second dielectric layer close to the first dielectric layer, and the resistance of the field plate drive resistor corresponding to each field plate unit located in each layer of the second dielectric layer gradually increases from a second dielectric layer close to the first dielectric layer to a second dielectric layer far away from the first dielectric layer.

13. A method for preparing a depletion-mode GaN device according to any one of claims 1 to 12, characterized in that: The steps include: An active area, a gate drive resistor, and a field plate drive resistor are formed on the stacked structure by photoresist protection; or, an active area, a gate drive resistor, a field plate drive resistor, and a diode injection protection area are formed; Forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, and a fourth ohmic metal over the stacked structure; or forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, a fourth ohmic metal, a fifth ohmic metal, and a Schottky metal; Filling metal on the stacked structure and etching to form a gate structure and a gate connection component; depositing a first dielectric layer over the gate structure, and forming a field plate and a field plate connection assembly over the first dielectric layer; Depositing a second dielectric layer above the field plate, etching through holes downward from the second dielectric layer and filling them with metal to form a first metal connecting bar, a second metal connecting bar, a third metal connecting bar, a fourth metal connecting bar, a fifth metal connecting bar and a sixth metal connecting bar; A source electrode, a drain electrode, a gate drive loop connection section and a field plate drive loop connection section are formed on the second dielectric layer to obtain the depletion-mode GaN device.

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