Digital mutual inductor signal decoding method and device based on FPGA

Abstract

The invention relates to a digital mutual inductor signal decoding method and device based on an FPGA, and the method comprises the steps: receiving a serial Manchester data signal at a rising edge of each clock period through a receiving module according to a reference clock which is 16 times higher than the Manchester signal frequency, detecting a correct rising edge, starting a synchronous clock, and carrying out the decoding of the Manchester data signal. The method comprises the following steps of: generating a central sample to extract effective data according to 1 / 4 and 3 / 4 positions of each bit period of a data cell, converting the extracted effective data into an NRZ code according to a Manchester encoding rule, and storing the decoded NRZ code into a shift register. According to the invention, high efficiency of a decoding process and flexibility of system operation can be realized. According to the design, the parallel processing capacity of the FPGA and the control advantages of the processor are fully combined, and it is ensured that information of the system flows rapidly and reliably.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a digital transformer signal decoding method and device based on FPGA. Background Art

[0002] Digital transformers are core devices in smart grids and are widely used in current and voltage measurement and protection devices. In order to achieve reliable data transmission, digital transformers usually adopt Manchester encoding technology, which is widely used in the industry due to its excellent synchronization performance and anti-interference performance. However, the existing decoding methods have obvious limitations in processing speed and data management, and it is difficult to meet the needs of efficient and real-time decoding. Therefore, the development of a new decoding method and device with higher decoding efficiency and system flexibility has become an urgent need to improve the performance of digital transformers. Summary of the invention

[0003] The present application provides a digital transformer signal decoding method based on FPGA, characterized by comprising: According to a reference clock 16 times higher than the Manchester signal frequency, a serial Manchester data signal is received using a receiving module at the rising edge of each clock cycle; Detect the correct rising edge and start the synchronous clock to provide timing support for subsequent decoding; According to the 1 / 4 and 3 / 4 positions of each bit period of the data cell, a central sample is generated to extract valid data; According to the Manchester coding rule, the extracted valid data is converted into NRZ code, and the decoded NRZ code is stored in the shift register.

[0004] Optionally, the FPGA-based digital transformer signal decoding method is characterized by: The receiving module is composed of two registers for receiving serial Manchester data; The receiving module generates a reference clock with a frequency 16 times the Manchester signal frequency, and processes the data by detecting the rising edge of the reference clock using FPGA; Through non-blocking assignment operation, register 2 <= register 1, register 1 <= serial Manchester data, and the necessary delay of the signal is achieved.

[0005] Optionally, the detecting a correct rising edge includes: When the rising edge of the signal is detected, that is, when register 1 is 1 and register 2 is 0, a synchronous clock with the same frequency as the Manchester signal is started; When the synchronous clock enable signal is valid, it is counted through a 4-bit register. The value of the synchronous clock is determined by the highest bit of the 4-bit register, thus realizing the accurate generation of the synchronous clock. The initial value of the synchronization clock is set to 0 to comply with the signal timing; According to the characteristics of Manchester encoding, during the initial communication establishment or the reconstruction after data anomalies, the synchronous clock needs to be triggered by specific conditions.

[0006] Optionally, the FPGA-based digital transformer signal decoding method is characterized by: The communication protocol of the device is based on the standard FT3 communication protocol, which requires that the idle state is represented by binary 1 and the value 1 is continuously transmitted between two frames of data using Manchester encoding.

[0007] Optionally, the generating of the central sample extracting valid data includes: The valid data is generated when the 4-bit register value is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period, ensuring that the sampling point is located at the center of the Manchester encoded signal.

[0008] Optionally, the detecting a correct rising edge includes: The detection of a correct rising edge refers to detecting a falling edge, and triggering the synchronization clock when a rising edge including a bit 0 is immediately followed.

[0009] Optionally, converting the extracted valid data into NRZ code and storing the decoded NRZ code into a shift register includes: When the rising edge of the reference clock is detected and the sample value is 1, the value of the NRZ code is determined by the XOR operation result of the current Manchester encoding state and the synchronization clock; The storing in the shift register refers to using a 16-bit shift register to store the latest decoded NRZ data starting from the lowest bit, and shifting the nth bit of data to the n+1th bit until 16 bits are filled.

[0010] The present application also provides a digital mutual inductor signal decoding device based on FPGA, characterized in that the device includes an FPGA chip and a shift register.

[0011] Optionally, the FPGA-based digital transformer signal decoding device is characterized in that the FPGA chip has an embedded ARM Cortex-M3 processor responsible for system management and data processing functions, while the FPGA focuses on completing signal decoding.

[0012] The present application also provides an electronic device, characterized in that it includes: An MCU communicates bidirectionally with a main control device through a serial port, and uploads the calculated effective value and fault information to the main control device periodically or when an abnormality occurs, so as to facilitate real-time monitoring and analysis.

[0013] The beneficial effect of the present application is to achieve high efficiency in the decoding process and flexibility in system operation. This design fully combines the parallel processing capability of FPGA and the control advantage of the processor, ensuring that the information flow of the system is fast and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required in the embodiments or the description of the prior art. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0015] Figure 1 A flow chart of a digital mutual inductor signal decoding method based on FPGA disclosed in the present application is shown. DETAILED DESCRIPTION

[0016] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0017] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise clearly and specifically defined.

[0018] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0019] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0020] This application involves processing and analyzing the collected digital signals of the mutual inductor, including data frame parsing, timing signal analysis and synchronization, protocol analysis and implementation. The core of this application is composed of a system-level packaged FPGA+ARM chip, which has an embedded ARM Cortex-M3 processor responsible for system management and data processing functions; at the same time, the FPGA focuses on the signal decoding process. The decoded data is efficiently transmitted between the FPGA and the processor through the AHB bus, and the ARM Cortex-M3 further performs anomaly detection and management tasks, thereby achieving high efficiency in the decoding process and flexibility in system operation.

[0021] The FPGA (Field-Programmable Gate Array) is a semiconductor device that can be programmed on site and has a high degree of flexibility and reconfigurability. Unlike traditional ASICs (Application Specific Integrated Circuits), FPGAs can implement different logic functions by modifying software codes without changing the hardware circuit.

[0022] The ARM Cortex-M3 is a microprocessor core that supports single-cycle multiplication, hardware division, branch prediction, and the Thumb-2 instruction set.

[0023] The AHB (Advanced High-performance Bus) bus is a bus mainly used for connecting high-performance modules. The decoded data is transmitted to the MCU through the AHB bus for data frame judgment, thereby effectively improving the responsiveness and reliability of the system.

[0024] like Figure 1 As shown, the flowchart of the FPGA-based digital transformer signal decoding method includes: S100, using a receiving module to receive a serial Manchester data signal at a rising edge of each clock cycle according to a reference clock that is 16 times higher than the Manchester signal frequency.

[0025] Specifically, the reference clock is generated by a receiving module, and the reference clock frequency is 16 times the Manchester signal frequency to improve the accuracy of decoding; the receiving module is composed of two registers for receiving serial Manchester data.

[0026] The Manchester signal frequency is twice the original data frequency. In Manchester coding, the transmission of each bit is divided into a first half cycle and a second half cycle. The first half cycle transmits the inverse code of the bit, and the second half cycle transmits the original code of the bit. This design allows a level jump in the middle of each bit, and the level jump can be used to generate a synchronization signal for both the sender and the receiver.

[0027] S200, detects the correct rising edge and starts the synchronous clock to provide timing support for subsequent decoding.

[0028] Specifically, the rising edge of the signal refers to the case where the value of register 1 is 1 and the value of register 2 is 0, and a synchronous clock is generated by one register.

[0029] Wherein, each time the 4-bit register counts, the value will be increased by 1, and the value of the synchronous clock is determined by the highest bit of the 4-bit register value, thereby realizing the generation of the synchronous clock.

[0030] S300, generating a central sample and extracting valid data according to the 1 / 4 and 3 / 4 positions of each bit period of the data cell.

[0031] Specifically, the valid data refers to a valid Manchester signal sample, which is generated when the 4-bit register value is 3 or 12, and the corresponding bit period positions are 1 / 4 and 3 / 4. Extraction at this time can ensure that the acquisition point is at the center of the Manchester coded signal.

[0032] S400, converting the extracted valid data into NRZ code according to Manchester coding rules, and storing the decoded NRZ code into a shift register.

[0033] Specifically, if a high-level change is detected within the bit period, it is converted to NRZ code 1, and if a low-level change is detected, it is converted to NRZ code 0 and stored in the shift register. According to the specific start bit and end bit, the valid data in the shift register is transferred to the data register, and then the decoded data is sent to the master device using the hardware SPI interface.

[0034] The Manchester encoding is a self-synchronous encoding method, which is characterized by that in each clock cycle, the state of the signal changes at the midpoint of the clock cycle, so that there is a jump in the middle of each bit. This encoding method can generate two jumps in each bit cycle, representing logic "0" and logic "1" respectively, and there is a jump in the middle of each bit, which allows the receiver to synchronize the clock by observing the signal jump. The disadvantage of Manchester encoding is that the data transmission rate is only half of the maximum theoretical rate, because each bit requires two cycles to transmit.

[0035] The NRZ (Non-Return-to-Zero Code) code is a non-return-to-zero encoding method, which uses a low level to represent a binary 0 and a high level to represent a binary 1. The disadvantage of the NRZ code is that it is impossible to determine the start and end of each bit, so it is necessary to use another channel to transmit a synchronization signal while sending the NRZ code.

[0036] The beneficial effect of the above content is that when processing Manchester signals, not only the efficiency and accuracy of decoding are significantly improved, but also the flexibility and scalability of the system are enhanced, providing an efficient and reliable solution for related applications.

[0037] Specifically, the present application designs a receiving module that receives serial Manchester data (MDI) through two registers (MDI1 and MDI2).

[0038] This module generates a reference clock (clk16x) with a frequency 16 times that of the Manchester signal, and uses FPGA to process data by detecting the rising edge of the reference clock (clk16x).

[0039] Through the non-blocking assignment operations mdi2<= mdi1; mdi1<= mdi, the necessary delay of the signal is achieved.

[0040] Specifically, when a rising edge of a signal is detected (i.e., mdi1 is 1 and mdi2 is 0), a synchronous clock (clk1x) having the same frequency as the Manchester signal is started for subsequent processing.

[0041] The generation of the synchronous clock (clk1x) is performed when the rising edge of the high-frequency reference clock (clk16x) is detected. In addition, when the enable signal of the same-frequency clock is valid, the system counts through a 4-bit register (clkdiv), and the value of clkdiv is increased by 1 each time. The value of the same-frequency clock (clk1x) is determined by the highest bit of clkdiv (clkdiv[3]), thereby achieving accurate generation of the same-frequency clock.

[0042] Based on the characteristics of Manchester encoding (the transition of the intermediate level from low to high represents "1", and the transition from high to low represents "0"), during the initial communication establishment or the reconstruction process after data abnormality, the synchronous clock (clk1x) needs to be triggered by specific conditions.

[0043] Specifically, when a falling edge is detected, followed by a rising edge containing a bit 0, the synchronization clock (clk1x) is triggered to ensure accurate decoding and timing synchronization of subsequent data.

[0044] Specifically, during the decoding process, data sampling is performed at the 1 / 4 and 3 / 4 positions of the bit period. This design ensures that the sampling point is located at the center of the Manchester coded signal, thereby improving the accuracy of signal extraction. Specifically, a valid Manchester signal sample is generated when the clkdiv value is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period. By sampling at the optimal moment of signal transition, the bit error rate caused by timing deviation is minimized, thereby improving the reliability and accuracy of decoding.

[0045] Specifically, according to the rules of Manchester encoding, the received signal is converted into NRZ (non-return-to-zero) code. Specifically, when the rising edge of the high-frequency reference clock (clk16x) is detected, the current sample value (sample) is checked. If sample=1, the value of the NRZ code is determined by the XOR operation result of the current Manchester encoding state (mdi2) and the synchronization clock (clk1x), where mdi2 is used to represent the current Manchester encoding state. Through this process, the precise conversion of Manchester encoded signals to NRZ codes is achieved, providing a reliable foundation for subsequent data processing.

[0046] When the rising edge of the synchronous clock (clk1x) is detected, the following non-blocking assignment operation is performed: rsr[15:1]<=rsr[14:0]; rsr[0]<=nrz; Through this process, a 16-bit shift register (rsr) is used to store the decoded NRZ data. Each bit of the shift register can be regarded as an independent storage unit, and the data is shifted according to the following rules: the 14th bit data is shifted to the 15th bit, the 13th bit data is shifted to the 14th bit, and so on, and the latest decoded data is stored in the lowest bit (rsr[0]). This design ensures that the shift register always stores the latest 16 bits of data in a first-in, first-out order. When the register is filled with 16 bits, the data can be further processed or sent as needed, thereby achieving efficient decoded data management and subsequent operations.

[0047] Specifically, the communication protocol of this device is based on the standard FT3 communication protocol, which is a common serial communication protocol that ensures the effective transmission of data according to strict specifications. According to the GB / T 20840.8-2007 standard, the protocol requires that the idle state is represented by binary 1 and the value 1 is continuously transmitted between two frames of data in Manchester encoding. In this device, when the synchronous clock (clk1x) rises, the system checks the value of the NRZ signal: if NRZ=1, the counter is incremented; if NRZ=0, the counter is reset to 0.

[0048] At the same time, when the NRZ signal returns to zero, the system will detect the value of the counter. When the counter reaches or exceeds 70, the starting position of the data frame header can be determined. This is because according to the FT3 protocol, the data frame usually starts with a specific identifier (0x0564), and the state change of the NRZ signal is an important basis for detecting the identifier. Once the starting position of the data frame header is determined, the system will extract continuous 16-bit data from the shift register (rsr) and transfer it to the data register (data_register). This transmission is achieved through a simple assignment operation, such as data_register<=rsr, thereby completing the effective decoding and storage of the data.

[0049] Among them, in the FT3 communication protocol, each frame of data contains 56 bytes. According to the end signal of data transmission or the complete reception of the frame, it can be determined when to stop the same frequency clock. Usually, the same frequency clock stops when the complete 56 bytes are received. When a new data frame needs to be transmitted, the same frequency clock will be restarted. When the clock is restarted, the clock can be started immediately by detecting the rising edge of the Manchester encoded signal mdi2 at the rising edge of the reference clock (clk16x). This operation ensures the synchronization between each frame of data and the clock. Through the identification of the frame header and clock control, the integrity and accuracy of each frame of data can be effectively guaranteed. At each rising edge of the clock, the system will perform the same NRZ data storage and shifting operations as mentioned above to ensure that the newly received data is accurately recorded and stored.

[0050] In addition, the FT3 communication protocol shows how to ensure data integrity and reliability through multiple mechanisms. CRC16 (cyclic redundancy check) is a common algorithm for detecting data transmission errors. In the FT3 protocol, each frame of data contains three independent CRC16 check values. The receiver will calculate the CRC16 value based on the received frame data and then compare it with the three received CRC16 check values. If the calculated CRC16 value is inconsistent with the received one, it means that an error occurred during the data transmission process. At the same time, in the FT3 communication protocol, there is also a sample counter in each frame of data. The function of the sample counter is to ensure the correct data transmission order and prevent data loss or duplication. Each frame of data contains a sample counter value, which is incremented between each frame. If the received sample counter value is inconsistent with the locally stored counter value (for example, the counter is skipped or repeated), the frame loss processing mechanism will be triggered, so that transmission interruption or data disorder can be discovered in time. The MCU (microcontroller unit) can take corresponding measures in time by detecting data errors, frame loss or other potential faults. When an abnormal situation is detected (such as data verification failure, frame loss, counter inconsistency, etc.), the MCU will trigger a processing mechanism, usually resetting the data reception on the FPGA (field programmable gate array) side to the initial state, resynchronizing the data stream or reestablishing the link.

[0051] Specifically, the device used in this application passes the decoded data to the MCU for data frame judgment through a high-speed bus (AHB), thereby effectively improving the responsiveness and reliability of the system. The use of the AHB bus can provide high-bandwidth data transmission, ensuring that the decoded data can be quickly transmitted to the MCU. After receiving the data frame, the MCU first performs an integrity check, including verifying the frame start character, frame length, checksum, and sample counter. If the MCU finds an abnormality (such as data error, frame loss or other faults), the corresponding processing mechanism will be triggered. The MCU notifies the FPGA of the abnormality through the AHB bus. After receiving the abnormal notification from the MCU, the FPGA will reset the same frequency clock start condition and prepare to receive new data frames, thereby ensuring the continuity of the data stream. This method significantly enhances the robustness and real-time performance of the system by combining the abnormal detection of the MCU with the reconnection mechanism of the FPGA, and can quickly respond and restore the connection when a data transmission error occurs. This solution is particularly suitable for application scenarios with high requirements for data transmission reliability.

[0052] Among them, the MCU can perform statistical analysis on the sampled data, calculate effective values ​​(such as RMS values) and other parameters, and make fault judgments. In the FT3 protocol, each frame of data contains sampled value data of neutral point current, A phase current, B phase current, C phase current, A phase voltage, B phase voltage, C phase voltage, neutral point voltage, etc. According to the storage order of the sampled values ​​and the specified sampling rate, the corresponding effective value can be calculated.

[0053] Moreover, the MCU communicates with the main control device in two directions through the serial port, and uploads the calculated effective value and fault information to the main control device regularly or when an abnormality occurs, so as to facilitate real-time monitoring and analysis. In addition, the MCU can also receive instructions and new configuration parameters from the main control device, adjust its operating mode or data processing method, and reset the system according to the instructions to ensure rapid recovery when a fault occurs or reinitialization is required. Through the calculation and upload functions of the MCU, the main control device can realize real-time monitoring of the entire system, enhancing the reliability of the system. The independent processing capability of the MCU makes the system more flexible and can be adjusted according to different application requirements, while also facilitating future functional expansion.

[0054] In summary, the purpose of this application is to provide a data decoding and transmission system based on Manchester encoding, which has the following advantages: Device structure: The core of this device is composed of a system-level package FPGA chip with an embedded ARM Cortex-M3 processor. The FPGA is responsible for decoding the Manchester signal, while the ARM Cortex-M3 processor is responsible for system management and data processing. The two exchange data through the AHB bus to ensure efficient information flow.

[0055] Efficient decoding: Use a reference clock 16 times higher than the Manchester signal frequency, and use two FF registers to receive the serial Manchester data signal at the rising edge of each clock cycle. When the correct rising edge is detected, start a clock with the same frequency as the Manchester signal (i.e. 1 / 16 of the reference clock frequency) for decoding. Use data cells to generate center samples at 1 / 4 and 3 / 4 points of each bit period to extract valid data.

[0056] Simplify hardware design: Use simple triggers and clock control to reduce system complexity. Decode the received Manchester signal into NRZ code and define the conditions of logic "1" and "0". Use shift registers to store the decoded NRZ data and transfer the data to the data register according to specific conditions.

[0057] Data transmission: The decoded data is sent to the master device using the hardware SPI interface to ensure data integrity and transmission speed. Specific embodiment: For example, assuming that the input Manchester signal frequency is 1 MHz, the system of the present application will use a 16 MHz clock for sampling. In each bit period, the system will generate a central sample and decode it, and finally transmit the data to the master device through the SPI interface.

[0059] The beneficial effect of this application is that through the combination of FPGA and MCU, efficient decoding and intelligent data management of Manchester signals are realized, which significantly improves the real-time performance and reliability of the system. At the same time, the method is flexible and can adapt to various data transmission requirements, and has broad market application prospects.

[0060] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A digital transformer signal decoding method based on FPGA, characterized in that: include: According to a reference clock 16 times higher than the Manchester signal frequency, a serial Manchester data signal is received using a receiving module at the rising edge of each clock cycle; Detect the correct rising edge and start the synchronous clock to provide timing support for subsequent decoding; According to the 1 / 4 and 3 / 4 positions of each bit period of the data cell, a central sample is generated to extract valid data; According to the Manchester coding rule, the extracted valid data is converted into NRZ code, and the decoded NRZ code is stored in the shift register.

2. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The receiving module is composed of two registers for receiving serial Manchester data; The receiving module generates a reference clock with a frequency 16 times the Manchester signal frequency, and processes the data by detecting the rising edge of the reference clock using FPGA; Through non-blocking assignment operation, register 2 <= register 1, register 1 <= serial Manchester data, and the necessary delay of the signal is achieved.

3. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The detection of a correct rising edge includes: When the rising edge of the signal is detected, that is, when register 1 is 1 and register 2 is 0, a synchronous clock with the same frequency as the Manchester signal is started; When the synchronous clock enable signal is valid, it is counted through a 4-bit register. The value of the synchronous clock is determined by the highest bit of the 4-bit register, thus realizing the accurate generation of the synchronous clock. The initial value of the synchronization clock is set to 0 to comply with the signal timing; According to the characteristics of Manchester encoding, during the initial communication establishment or the reconstruction after data anomalies, the synchronous clock needs to be triggered by specific conditions.

4. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The communication protocol of the device is based on the standard FT3 communication protocol, which requires that the idle state is represented by binary 1 and the value 1 is continuously transmitted between two frames of data using Manchester encoding.

5. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The generating center sample extracts effective data, including: The valid data is generated when the 4-bit register value is 3 or 12, corresponding to the 1 / 4 and 3 / 4 positions of the bit period, ensuring that the sampling point is located at the center of the Manchester encoded signal.

6. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The detection of a correct rising edge includes: The detection of a correct rising edge refers to detecting a falling edge, and triggering the synchronization clock when a rising edge including a bit 0 is immediately followed.

7. The FPGA-based digital transformer signal decoding method according to claim 1, characterized in that: The step of converting the extracted valid data into NRZ code and storing the decoded NRZ code into a shift register includes: When the rising edge of the reference clock is detected and the sample value is 1, the value of the NRZ code is determined by the XOR operation result of the current Manchester encoding state and the synchronization clock; The storing in the shift register refers to using a 16-bit shift register to store the latest decoded NRZ data starting from the lowest bit, and shifting the nth bit of data to the n+1th bit until 16 bits are filled.

8. A digital transformer signal decoding device based on FPGA, characterized in that: The device comprises an FPGA chip and a shift register.

9. The FPGA-based digital transformer signal decoding device according to claim 8, characterized in that: The FPGA chip has an embedded ARM Cortex-M3 processor, which is responsible for system management and data processing functions, while the FPGA is focused on signal decoding.

10. An electronic device, characterized in that: include: An MCU communicates bidirectionally with a main control device through a serial port, and uploads the calculated effective value and fault information to the main control device periodically or when an abnormality occurs, so as to facilitate real-time monitoring and analysis.

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