FPGA-based infrared systems, infrared imaging equipment and electronic equipment

Abstract

The present invention belongs to the field of infrared system design technology, and in particular, relates to an infrared system, infrared imaging equipment and electronic equipment based on FPGA, including: a detector module, a dual FPGA processing module and a display module; the detector module is used to obtain infrared digital signals; the dual FPGA processing module includes an FPGA image preprocessing module and an FPGA image processing module; the FPGA image preprocessing module is used to perform image preprocessing on infrared digital signals to obtain target coded data; the FPGA image processing module is used to process the target coded data according to a preset image processing algorithm to obtain infrared image processing results; the display module is used to display infrared image processing results. The infrared system proposed in this application uses a dual FPGA chip as the main processor of the infrared system, combined with the software architecture of the high-resolution infrared system, which can achieve high-resolution infrared image processing while reducing the cost and power consumption of the infrared system.

Description

Technical Field

[0001] The present invention relates to the technical field of infrared system design, and in particular to an infrared system, infrared imaging equipment and electronic equipment based on FPGA. Background Art

[0002] In the field of infrared technology, infrared detectors are key components for acquiring infrared images, and their resolution directly affects the performance and application scope of infrared systems. For a long time, the development of infrared detectors has been mainly concentrated in the field of low resolution, and they are mainly used in basic scenarios such as simple temperature monitoring and smoke detection. However, with the advancement of science and technology and the in-depth application of infrared technology in various fields, the resolution requirements for infrared detectors are getting higher and higher.

[0003] Existing high-resolution infrared systems are expensive and complex in design, and have significant limitations in performance and maintenance. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide an infrared system, infrared imaging device and electronic device based on FPGA, which can realize real-time acquisition, processing and application of high-resolution infrared images, while reducing the cost and power consumption of the infrared system. The specific scheme is as follows: In a first aspect, an embodiment of the present application provides an infrared system based on FPGA, comprising: a detector module, a dual FPGA processing module and a display module; the detector module is connected to the input end of the dual FPGA processing module, and the output end of the dual FPGA processing module is connected to the display module; The detector module is used to obtain infrared digital signals; The dual FPGA processing module includes an FPGA image preprocessing module and an FPGA image processing module, the input end of the FPGA image preprocessing module serves as the input end of the dual FPGA processing module, the output end of the FPGA image preprocessing module is connected to the input end of the FPGA image processing module, and the output end of the FPGA image processing module serves as the output end of the dual FPGA processing module; The FPGA image preprocessing module is used to perform image preprocessing on the infrared digital signal to obtain target coded data; The FPGA image processing module is used to process the target coded data according to a preset image processing algorithm to obtain an infrared image processing result; The display module is used to display the infrared image processing result.

[0005] According to a specific implementation of the embodiment of the present application, the detector module includes an infrared detector and an infrared detector driving circuit, wherein the infrared detector is connected to the infrared detector driving circuit, and the infrared detector driving circuit is connected to the FPGA image preprocessing module; The infrared detector is used to collect infrared signals and convert the infrared signals into electrical signals; The infrared detector driving circuit is used for converting the electrical signal into an infrared digital signal with a preset number of bits.

[0006] According to a specific implementation of the embodiment of the present application, the FPGA image preprocessing module includes a RISC_V soft core processor, an image preprocessing unit, a first data read and write control unit and a first storage unit; The image preprocessing unit is used to perform image preprocessing on the infrared digital signal according to the functional modules configured by the RISC_V soft-core processor to obtain image data; The first data read-write control unit is used to cache the image data in the first storage unit, and perform preset encoding processing according to the image data, character data and control parameters to obtain the target encoded data.

[0007] According to a specific implementation of the embodiment of the present application, the FPGA image processing module includes an image algorithm unit, a second data read and write control unit, a third data read and write control unit, an interface timing unit, and a second storage unit; The image algorithm unit is used to decode the target coded data to obtain the image data, the character data and the control parameter; select a corresponding image processing algorithm according to the control parameter to process the image data to obtain the target image data; The second data read-write control unit is used to cache the target image data and the character data in the second storage unit; The third data read-write control unit is used for reading the target image data and the character data from the second storage unit, and transmitting the target image data and the character data to the interface timing unit; The interface timing unit is used to convert the target image data and the character data into a target display signal to obtain the infrared image processing result.

[0008] According to a specific implementation of the embodiment of the present application, the FPGA image preprocessing module and the FPGA image processing module use the same type of system-level packaged FPGA chip.

[0009] According to a specific implementation of the embodiment of the present application, the interface timing unit includes multiple different types of video signal output ports, wherein the types of the video signal output ports include digital video ports, low voltage differential signal ports and BT1120 protocol ports.

[0010] According to a specific implementation of the embodiment of the present application, the dual FPGA processing module further includes at least one of a USB interface driving circuit and an HDMI interface driving circuit; The input end of the USB interface driving circuit is connected to the output end of the FPGA image processing module, and the output end of the USB interface driving circuit is used to connect to an external display device or the display module; The input end of the HDMI interface driving circuit is connected to the output end of the FPGA image processing module, and the output end of the HDMI interface driving circuit is used to connect to an external display device or the display module.

[0011] According to a specific implementation of the embodiment of the present application, the display module includes at least one of a digital video port interface, a low voltage differential signal port interface, a BT1120 protocol interface, a USB interface and an HDMI interface.

[0012] In a second aspect, an embodiment of the present application provides an infrared imaging device, including the FPGA-based infrared system described in the first aspect.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, comprising the infrared imaging device described in the second aspect.

[0014] In summary, this embodiment provides an infrared system, infrared imaging equipment and electronic equipment based on FPGA, including: a detector module, a dual FPGA processing module and a display module; the detector module is used to obtain infrared digital signals; the dual FPGA processing module includes an FPGA image preprocessing module and an FPGA image processing module; the FPGA image preprocessing module is used to perform image preprocessing on infrared digital signals to obtain target coded data; the FPGA image processing module is used to process the target coded data according to a preset image processing algorithm to obtain infrared image processing results; the display module is used to display infrared image processing results. The infrared system proposed in this application uses a dual FPGA chip as the main processor of the infrared system, combined with the software architecture of the high-resolution infrared system, which can achieve high-resolution infrared image processing while reducing the cost and power consumption of the infrared system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A structural block diagram of an infrared system based on FPGA provided in an embodiment of the present application; Figure 2 A structural block diagram of another FPGA-based infrared system provided in an embodiment of the present application; Figure 3 A structural block diagram of an FPGA image preprocessing module provided in an embodiment of the present application; Figure 4 A structural block diagram of an FPGA image processing module provided in an embodiment of the present application; Figure 5 A schematic diagram of timing control of an FPGA image processing module provided in an embodiment of the present application; Figure 6 A structural block diagram of another FPGA-based infrared system provided in an embodiment of the present application.

[0017] Summary of reference numerals: Detector module-110; infrared detector-111; infrared detector driving circuit-112; Dual FPGA processing module-120; FPGA image preprocessing module-121; RISC_V soft core processor-1211; image preprocessing unit-1212; first data read and write control unit 1213; first storage unit-1214; FPGA image processing module-122; image algorithm unit-1221; interface timing unit-1222; second data read and write control unit-1223; third data read and write control unit-1224; second storage unit-1225; display module-130; DETAILED DESCRIPTION The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0018] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0019] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0020] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0021] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, one skilled in the art will appreciate that aspects may be practiced without these specific details.

[0022] In related technologies, in order to make up for the difficulty of designing complex image algorithms on the Field-Programmable Gate Array (FPGA) platform, long development cycle, limited resources, etc., high-resolution infrared modules or complete machines generally adopt a single FPGA system design method, or a system design method using a combination of multiple chips such as FPGA+DSP, FPGA+ARM, etc. FPGA is used as a coprocessor to be responsible for image acquisition and interface processing, and DSP and ARM are used as main processors to be responsible for control and image processing. These high-resolution infrared systems will be restricted by the development of the semiconductor industry, and will encounter problems such as high cost, difficulty in procurement, complex design, difficulty in maintenance, high power consumption, and poor real-time performance during the design process.

[0023] This embodiment proposes an FPGA-based infrared system that can be equipped with a high-resolution infrared detector 111, and uses a small-size, low-power dual FPGA as the hardware design. In conjunction with the interface design and software coordination, it can achieve real-time acquisition, processing and application of high-resolution infrared images, while reducing the cost and power consumption requirements of the infrared system.

[0024] refer to Figure 1 , provides an FPGA-based infrared system, including: a detector module 110, a dual FPGA processing module 120 and a display module 130, wherein the detector module 110 is connected to the input end of the dual FPGA processing module 120, and the output end of the dual FPGA processing module 120 is connected to the display module 130.

[0025] In this embodiment, the detector module 110 is used to obtain infrared digital signals, wherein the infrared digital signals include infrared image data. Figure 2 As shown, the detector module 110 includes an infrared detector 111 and an infrared detector driving circuit 112 , wherein the infrared detector 111 is connected to the infrared detector driving circuit 112 , and the infrared detector driving circuit 112 is connected to the FPGA image preprocessing module 121 in the dual FPGA processing module 120 .

[0026] In actual application, the infrared detector 111 is used to collect infrared signals and convert the infrared signals into electrical signals. The infrared detector driving circuit 112 is used to convert the electrical signals into infrared digital signals with a preset number of bits.

[0027] In this embodiment, the infrared detector 111 can use a high-resolution detector to achieve the acquisition of high-resolution infrared images. The infrared detector driving circuit 112 can convert the electrical signal into a 14-bit parallel digital signal. This is to facilitate the subsequent FPGA chip to perform data analysis on the infrared digital signal. It should be noted that the specific circuit structure of the infrared detector driving circuit 112 can be adaptively replaced according to the number of bits of the infrared digital signal that needs to be converted in the actual application scenario.

[0028] In this embodiment, if Figure 1 and Figure 2 As shown, the dual FPGA processing module 120 includes an FPGA image preprocessing module 121 and an FPGA image processing module 122. The input end of the FPGA image preprocessing module 121 serves as the input end of the dual FPGA processing module 120. The output end of the FPGA image preprocessing module 121 is connected to the input end of the FPGA image processing module 122. The output end of the FPGA image processing module 122 serves as the output end of the dual FPGA processing module 120.

[0029] In actual application, a small-size, high-performance, low-power dual-system-in-a-package (SIP) FPGA may be used. In one embodiment, the FPGA image preprocessing module 121 and the FPGA image processing module 122 use the same type of SIP FPGA chip.

[0030] In this embodiment, the FPGA chip can use a 16nm process technology. In a 5.5*5.5mm micro package with only a 0.5mm pitch, the FPGA chip integrates a serial peripheral interface flash (SPI Flash) and a double data rate synchronous dynamic random access memory (DDR). The FPGA used in this embodiment can use the above process technology and highly integrated configuration to make the FPGA chip have low power consumption characteristics. And this embodiment uses the same model of system-level packaged FPGA chips, which can greatly reduce the procurement cost, thereby reducing the procurement cost of the infrared system.

[0031] In actual application, the FPGA image preprocessing module 121 is used to perform image preprocessing on the infrared digital signal to obtain target coded data.

[0032] In this embodiment, the target coded data may be combined data encoded based on the BT1120 coding protocol. The combined data includes infrared image data, character data, and control instructions. When the FPGA image preprocessing module 121 performs image preprocessing on the infrared digital signal, it will parse and obtain the corresponding combined data. It should be noted that the infrared image preprocessing performed by the FPGA image preprocessing module 121 includes, but is not limited to, non-uniformity correction (NCU correction for short), time domain filtering, bad pixel processing, and baffle data processing. The specific steps of infrared image preprocessing can be customized according to the needs of the actual application scenario.

[0033] In this embodiment, the FPGA image processing module 122 is used to process the target coded data according to a preset image processing algorithm to obtain an infrared image processing result.

[0034] In this embodiment, the FPGA image processing module 122 can first decode the target encoded data sent by the FPGA image preprocessing module 121 based on the BT1120 encoding protocol, configure the preset image processing algorithm according to the decoded control parameters, and then process the decoded infrared image data according to the preset image processing algorithm, and finally combine the infrared image data and character data processed by the algorithm to obtain the infrared image processing result.

[0035] The display module 130 is used to display the infrared image processing result.

[0036] In this embodiment, the display module 130 is connected to the FPGA image processing module 122, and the display port of the display module 130 can be any one of a digital video port (Digital Visual Interface, referred to as DVI) interface, a low voltage differential signaling port (Low Voltage Differential Signaling, referred to as LVDS) interface, a BT1120 protocol interface, a USB interface and an HDMI interface.

[0037] The FPGA image processing module 122 communicates with the display module 130 via a communication method corresponding to the display port of the display module 130 , so that the display module 130 displays the infrared image processing result, thereby completing the infrared image acquisition, processing and display of the infrared system.

[0038] In summary, the FPGA-based infrared system proposed in this embodiment uses a high-resolution infrared detector 111 as the infrared image acquisition device of the infrared detector module 110, and uses two FPGA chips as the main processor of the infrared system, which effectively reduces the design complexity and production cost of the infrared system. In addition, the infrared system provided in this embodiment does not need to be configured with a digital signal processing (DSP) chip, thereby effectively reducing the power consumption of the infrared system and making it easier to maintain and develop.

[0039] According to a specific implementation of the embodiment of the present application, Figure 3 As shown, the FPGA image preprocessing module 121 includes a control parsing unit, a BT1120 encoding unit, a RISC_V soft core processor 1211, an image preprocessing unit 1212, a first data read and write control unit 1213 and a first storage unit 1214. Among them, the input end of the image preprocessing unit 1212 is connected to the detector module 110 to receive the infrared digital signal sent by the detector module 110. The output end of the RISC_V soft core processor 1211 is connected to the control parsing unit, which is used to send control parameters to the control parsing unit, and the control parsing unit forwards the control parameters to the image preprocessing unit 1212 to configure the functional submodules in the image preprocessing unit 1212 according to the control parameters to implement image preprocessing corresponding to the control parameters. The first data read and write control unit 1213 is used to write the image data output by the image preprocessing unit 1212 into the first storage unit 1214, and the RISC_V soft core processor 1211 is also used to write character data into the first storage unit 1214. The first data read-write control unit 1213 is further used to read image data and character data from the storage unit.

[0040] The image preprocessing unit 1212 is used to perform image preprocessing on the infrared digital signal according to the functional sub-modules configured by the RISC_V soft-core processor 1211 to obtain image data.

[0041] The first data read-write control unit 1213 is used to cache the image data in the first storage unit 1214 .

[0042] The BT1120 encoding unit receives the control parameters sent by the control parsing unit, the character data read and sent by the first data read and write control unit 1213 from the first storage unit 1214, and the image data sent by the image preprocessing unit 1212, and performs preset encoding processing on the control parameters, character data and image data to obtain target encoded data.

[0043] In this embodiment, the FPGA chip of the FPGA image preprocessing module 121 implements the control programs such as power-on initialization, parameter configuration, menu interaction and instruction parsing of the high-resolution infrared system by building a RISC_V soft-core processor 1211. Specifically, the IP core is called in the FPGA chip to build the RISC_V soft-core processor 1211. The functional modules in the RISC_V soft-core processor 1211 include a control module, a baffle drive module, a temperature sensor drive module, a character display and multi-layer menu architecture processing module, and a DDR read-write module. As a reduced instruction set computer (Reduced Instruction Set Computer, referred to as RISC), the RISC_V soft-core processor 1211 can reduce the execution cycle of each instruction by simplifying the instruction set, thereby reducing the power consumption of the processor. In this embodiment, the control module of the RISC_V soft-core processor 1211 is used to send control parameters to the control parsing unit to implement the configuration of the image preprocessing algorithm in the image preprocessing unit 1212.

[0044] The image preprocessing unit 1212 performs image preprocessing by collecting infrared 14-bit parallel digital signals to obtain effective infrared image data.

[0045] Under the scheduling of the internal main state machine, the first data read and write control unit 1213 allows the effective infrared image data to pass through the DDR controller, cached in the DDR inside the FPGA chip, and finally output the combined data of the image, character index and control parameters through the BT1120 interface.

[0046] In some application scenarios, flexible power consumption configuration can be achieved by adjusting the enabling scheduling of the first data read and write control unit 1213 and the start and stop of the functional modules in the RISC_V soft core processor 1211. For example, the dynamic power consumption of the FPGA chip can be further reduced by controlling the shutdown of some functional algorithm modules, thereby effectively improving the flexibility of the power consumption configuration of the infrared system.

[0047] It should be noted that the FPGA chip of the FPGA image preprocessing module 121 in this embodiment can be directly connected to an external DVP device, LVDS device or BT1120 device through a multiplexing interface, wherein the multiplexing interface includes but is not limited to DVP, LVDS, BT1120 and other interfaces. In the specific application process, the FPGA image preprocessing module in this embodiment can also be used alone, and the original 14-bit AD value is directly output through the BT1120 encoding unit to ensure that the software architecture supports multi-interface multiplexing and instruction switching, which greatly expands the application scenarios of the infrared system.

[0048] In one embodiment, a character image overlay function module is also integrated in the BT1120 encoding unit. The character image overlay function module is used to overlay character data with infrared data. Using 3-bit data for character color index can make the interaction of infrared data between FPGAs more concise.

[0049] According to a specific implementation of the embodiment of the present application, Figure 4 As shown, the FPGA image processing module 122 includes a BT1120 decoding unit, an image algorithm unit 1221, a second data read and write control unit 1223, a third data read and write control unit 1224, an interface timing unit 1222 and a second storage unit 1225.

[0050] In this embodiment, the BT1120 decoding unit is used to decode the target coded data to obtain image data, character data and control parameters. According to the algorithm requirements in the actual application scenario, the decoded image data, character data and control parameters are sent to the image algorithm unit 1221, the second data read and write control unit 1223, the interface timing unit 1222 or the multiplexing interface.

[0051] The image algorithm unit 1221 is used to select a corresponding image processing algorithm according to the control parameters to process the image data to obtain target image data.

[0052] The second data read-write control unit 1223 is used to cache the target image data and character data in the second storage unit 1225; The third data read / write control unit 1224 is used to read the target image data and character data from the second storage unit 1225, and transmit the target image data and character data to the interface timing unit 1222; The interface timing unit 1222 is used to convert the target image data and character data into a target display signal to obtain an infrared image processing result.

[0053] In this embodiment, algorithms including stripe elimination algorithm, spatial filtering algorithm, detail enhancement algorithm and automatic gain control (AGC) algorithm are configured in advance in the image algorithm unit 1221. In actual application, the image algorithm unit 1221 selects a suitable algorithm according to the control parameters transmitted by the FPGA image preprocessing module 121, processes the decoded data sent by the BT1120 decoding unit, and obtains the target image data.

[0054] like Figure 5As shown, after the BT1120 decoding unit decodes the target coded data and obtains the image data, character data and control parameters, the second data read-write control unit 1223 caches the target image data and character data in the DDR buffer of the second storage unit 1225 according to the read-write instructions of the internal data read-write control state machine 1. The third data read-write control unit 1224 reads the target image data and character data from the DDR buffer of the second storage unit 1225 according to the read-write instructions of the internal data read-write control state machine 2, and then outputs them to the interface timing unit 1222, so that the interface timing unit 1222 performs signal conversion on the target image data and character data to obtain the corresponding target display signal. Finally, the interface timing unit 1222 is used to output the target display signal to the corresponding display module 130 through the multiplexing interface.

[0055] It should be noted that the target display signal includes but is not limited to a DVP signal, a LVDS signal, a BT1120 signal, a USB signal, and an HDMI signal. In one embodiment, the interface timing unit 1222 includes a plurality of different types of video signal output ports, wherein the types of the video signal output ports include a digital video port, a low voltage differential signal port, and a BT1120 protocol port. Each video signal output port is used to output a corresponding target display signal.

[0056] like Figure 5 As shown, the dual FPGA system design proposed in this embodiment fully utilizes the core advantages of FPGA as the main chip for image algorithm processing compared to DSP or ARM, namely high concurrency, high throughput and pipeline real-time processing. All sub-units of the FPGA image pre-processing module 121 and the FPGA image processing module 122 are cascaded in the form of a pipeline, avoiding the bottleneck caused by waiting for the results of the previous stage in serial processing. The minimum delay between sub-units is only 1 clock cycle, and the cumulative delay of the entire system is less than 80ms. The real-time performance of the high-resolution infrared system is guaranteed.

[0057] According to a specific implementation of the embodiment of the present application, Figure 6 As shown, the dual FPGA processing module 120 also includes at least one of a USB interface driving circuit and an HDMI interface driving circuit. Figure 6 As shown, the display module 130 includes an LVDS display device, a PC display device, a BT1120 display device and an HDMI display device.

[0058] The input end of the USB interface driving circuit is connected to the output end of the FPGA image processing module 122, and the output end of the USB interface driving circuit is used to connect to an external display device or a display module 130; The input end of the HDMI interface driving circuit is connected to the output end of the FPGA image processing module 122 , and the output end of the HDMI interface driving circuit is used to connect to an external display device or a display module 130 .

[0059] In this embodiment, the image display speed can be accelerated by adding a USB3.0 display mode to the main processing board. The USB interface driver circuit can use a USB interface dedicated chip to receive the parallel DVP data stream output by the FPGA image processing module 122, and process the parallel DVP data stream into a USB3.0 data stream that complies with the UVC protocol, so that the PC end can directly display the infrared image processed by the infrared system.

[0060] In this embodiment, the HDMI interface driving circuit needs to be configured with an additional HDMI adapter board. The HDMI adapter board uses a LVDS to HDMI dedicated chip to receive the LVDS data stream output by the FPGA image processing module 122, and processes it into a standard HDMI video signal, which can ultimately display the infrared image on a PC or a standard HDMI display.

[0061] In summary, this embodiment provides an infrared system based on FPGA, which can use the same type of domestic FPGA as a processing chip, with cost and procurement advantages. In addition, the dual FPGA image processing module does not need to be configured with other types of chips. FPGA chips have the advantages of low price, small size, high performance, high integration, and low power consumption, which in turn brings the advantages of low cost, low power consumption, and high performance of high-resolution infrared systems. The dual FPGA image processing module is used as the core processor, and its programmability and high parallel processing capabilities are used to design a software architecture suitable for high-resolution infrared systems, which fully utilizes the characteristics of FPGA's high concurrency, high throughput, and pipeline processing, and realizes real-time processing of high-resolution infrared images.

[0062] In addition, an embodiment of the present application further provides an infrared imaging device, including the FPGA-based infrared system in the aforementioned embodiment.

[0063] In addition, an embodiment of the present application also provides an electronic device, which includes: the infrared imaging device in the aforementioned embodiment; at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the infrared image processing algorithm configured in the FPGA-based infrared system.

[0064] The embodiment of the present application also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute the infrared image processing algorithm configured in the FPGA-based infrared system. It should be noted that the infrared image processing algorithm can be configured according to the needs of the actual application scenario.

[0065] The electronic devices in the embodiments of the present application may include, but are not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc.

[0066] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. Examples of computer-readable storage media may be, but are not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or components, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0067] In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0068] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0069] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Verilog, VHDL, SystemVerilog, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0070] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0071] The units involved in the embodiments described in this application can be implemented by software or hardware. It should be understood that each part of the present disclosure can be implemented by hardware, software, firmware or a combination thereof.

[0072] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An infrared system based on FPGA, characterized in that: include: Detector module, dual FPGA processing module and display module; The detector module is connected to the input end of the dual FPGA processing module, and the output end of the dual FPGA processing module is connected to the display module; The detector module is used to obtain infrared digital signals; The dual FPGA processing module includes an FPGA image preprocessing module and an FPGA image processing module, the input end of the FPGA image preprocessing module serves as the input end of the dual FPGA processing module, the output end of the FPGA image preprocessing module is connected to the input end of the FPGA image processing module, and the output end of the FPGA image processing module serves as the output end of the dual FPGA processing module; The FPGA image preprocessing module is used to perform image preprocessing on the infrared digital signal to obtain target coded data; The FPGA image processing module is used to process the target coded data according to a preset image processing algorithm to obtain an infrared image processing result; The display module is used to display the infrared image processing result.

2. The system according to claim 1, characterized in that The detector module includes an infrared detector and an infrared detector driving circuit, wherein the infrared detector is connected to the infrared detector driving circuit, and the infrared detector driving circuit is connected to the FPGA image preprocessing module; The infrared detector is used to collect infrared signals and convert the infrared signals into electrical signals; The infrared detector driving circuit is used for converting the electrical signal into an infrared digital signal with a preset number of bits.

3. The system according to claim 1, characterized in that The FPGA image preprocessing module includes a RISC_V soft core processor, an image preprocessing unit, a first data read and write control unit and a first storage unit; The image preprocessing unit is used to perform image preprocessing on the infrared digital signal according to the functional modules configured by the RISC_V soft-core processor to obtain image data; The first data read-write control unit is used to cache the image data in the first storage unit, and perform preset encoding processing according to the image data, character data and control parameters to obtain the target encoded data.

4. The system according to claim 3, characterized in that The FPGA image processing module includes an image algorithm unit, a second data read and write control unit, a third data read and write control unit, an interface timing unit and a second storage unit; The image algorithm unit is used to decode the target coded data to obtain the image data, the character data and the control parameter; select a corresponding image processing algorithm according to the control parameter to process the image data to obtain the target image data; The second data read-write control unit is used to cache the target image data and the character data in the second storage unit; The third data read-write control unit is used for reading the target image data and the character data from the second storage unit, and transmitting the target image data and the character data to the interface timing unit; The interface timing unit is used to convert the target image data and the character data into a target display signal to obtain the infrared image processing result.

5. The system according to any one of claims 1 to 4, characterized in that: The FPGA image preprocessing module and the FPGA image processing module use the same type of system-level packaged FPGA chip.

6. The system according to claim 4, characterized in that The interface timing unit includes a plurality of different types of video signal output ports, wherein the types of the video signal output ports include a digital video port, a low voltage differential signal port and a BT1120 protocol port.

7. The system according to claim 6, characterized in that The dual FPGA processing module also includes at least one of a USB interface driving circuit and an HDMI interface driving circuit; The input end of the USB interface driving circuit is connected to the output end of the FPGA image processing module, and the output end of the USB interface driving circuit is used to connect to an external display device or the display module; The input end of the HDMI interface driving circuit is connected to the output end of the FPGA image processing module, and the output end of the HDMI interface driving circuit is used to connect to an external display device or the display module.

8. The system according to claim 7, characterized in that The display module includes at least one of a digital video port interface, a low voltage differential signal port interface, a BT1120 protocol interface, a USB interface and a HDMI interface.

9. An infrared imaging device, characterized in that: The infrared system based on FPGA comprises any one of claims 1-8.

10. An electronic device, characterized in that: Including the infrared imaging device described in claim 9.

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