A two-stage fault simulation method based on multi-core CPU

Abstract

The application provides a two-stage fault simulation method based on a multi-core CPU, comprising: obtaining a circuit model, a test vector set and a fault list, wherein the vector set comprises a plurality of test vectors, and the fault list comprises a plurality of faults; obtaining the number N of threads of the multi-core CPU, and equally distributing the plurality of test vectors to the N threads; dividing the plurality of faults into M fault blocks to obtain a fault block set, wherein M>N; and simulating by the N threads according to a preset simulation mode, wherein the mode comprises the following operations performed by each thread: performing first-stage simulation, which comprises: each thread obtains one remaining fault block for testing each time until the fault block obtained by the thread has been tested and there is no remaining fault block, and then the thread enters second-stage simulation; and updating undetected faults according to the detected faults and the fault list during simulation; and performing second-stage simulation, which comprises: testing all undetected faults by using the test vector allocated to the thread.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to the field of fault simulation and testing of integrated circuits, and more particularly to a two-stage fault simulation method based on a multi-core CPU. BACKGROUND

[0002] There are many fault models for digital circuits, such as stuck-at fault, bridge fault, permanent fault, and transient fault, etc.

[0003] With the development of nanometer integrated circuit technology, a single very large scale integrated circuit (VLSI) can integrate more than 1 billion transistors. In order to find possible defects missed in the design or manufacturing process, fault simulation plays a crucial role in the test development stage of the VLSI design process. Fault simulation algorithm simulates the behavior of the circuit by inputting the generated test vectors into the circuit, simulates the injection of various faults in the circuit, and evaluates the behavior of the circuit to detect faults in the circuit. With the rapid growth of VLSI scale, the performance of fault simulation algorithm directly affects the efficiency of test generation and fault diagnosis, and the long running time of fault simulation has become a key problem in the current design test development stage.

[0004] In order to improve the speed and effectiveness of fault simulation algorithm, researchers have made in-depth research in various aspects. Many works use the powerful parallel computing capability of GPU to accelerate fault simulation. In addition, some researches aim to speed up multi-core fault simulation by minimizing memory usage or adopting shared memory strategy during fault simulation. In the field of distributed computing, some scholars have also explored the acceleration effect of distributed computing on fault simulation. In addition, some research works optimize fault simulation based on traditional parallel vector single fault propagation (PPSFP) or parallel fault simulation method.

[0005] In today's research field, there are many methods proposed for fault simulation, but a single method often cannot cope with the multiple challenges brought by fault simulation. Fault simulation faces many complexities and uncertainties, such as the continuous expansion of integrated circuit scale, the increase of design complexity, and the continuous progress of manufacturing process, which makes it difficult for a single fault simulation optimization method to meet the actual demand. At the same time, in the research of multi-threaded simulation algorithm, there is still a lack of effective algorithm design, and the load balancing and task scheduling strategy between threads need to be improved, and so far no effective method has been found to effectively combine various optimization strategies and multi-threaded algorithms.

[0006] In the process of investigating the prior art fault simulation acceleration algorithm, it is found that the single-thread model used therein will cause high communication cost in multi-threading, and the task allocation strategy used therein will also cause a large amount of invalid waiting and load imbalance among multi-threads.

[0007] It should be noted that the background art is only used to introduce the relevant information of the present application, so as to help understand the technical solutions of the present application, but does not mean that the relevant information must be the prior art. The relevant information is submitted and disclosed together with the present application scheme, and in the absence of evidence that the relevant information has been publicly disclosed before the filing date of the present application, the relevant information should not be regarded as prior art. SUMMARY

[0008] Therefore, the purpose of the present application is to overcome the defects of the prior art, and to provide a two-stage fault simulation method based on a multi-core CPU.

[0009] The purpose of the present application is achieved by the following technical solutions:

[0010] According to the first aspect of the present application, a two-stage fault simulation method based on a multi-core CPU is provided, comprising: obtaining a circuit model to be tested, a test vector set and a fault list, wherein the test vector set comprises a plurality of test vectors, and the fault list comprises a plurality of faults to be injected; obtaining the number N of threads of the multi-core CPU, and equally distributing the plurality of test vectors to the N threads, and dividing the plurality of faults into M fault blocks to obtain a fault block set, wherein M>N; simulating by the N threads according to a preset two-stage fault simulation mode, which comprises the following operations performed by each thread: performing simulation of the first stage, which comprises: each thread obtains one remaining fault block for testing each time, until the fault block obtained by itself has completed testing and there is no remaining fault block, and then enters the simulation of the second stage, wherein the undetected faults are updated according to the detected faults and the fault list; and performing simulation of the second stage, which comprises: testing all undetected faults using the test vectors allocated to itself.

[0011] Optionally, the simulation of the first stage comprises: maintaining a shared remaining fault block set and a shared undetected fault set for each thread, wherein the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: each thread obtains one remaining fault block from the remaining fault block set each time, and removes it from the remaining fault block set; inputs the test vector allocated to itself into the circuit model to obtain a first result; individually injects each fault in the obtained fault block into the circuit model to obtain a corresponding circuit fault model; inputs the test vector allocated to itself into the circuit fault model to obtain a second result; detects each fault, wherein whether the fault is detected is determined according to the first result and the second result, and if the fault is detected, the undetected fault set is updated. The scheme can at least achieve the following beneficial technical effects: the new fault block allocation strategy is used to balance the workload between threads, so as to improve the performance and effectiveness of fault simulation.

[0012] Optionally, the simulation of the second stage comprises repeatedly performing the following processing: obtaining the latest undetected fault set, and extracting only one undetected fault therefrom; injecting the undetected fault into the individual injection circuit model to obtain a circuit fault model corresponding to the undetected fault; inputting the test vector allocated to itself into the circuit fault model corresponding to the undetected fault to obtain a third result; detecting the undetected fault, wherein whether the fault is detected is determined according to the first result and the third result, and if the fault is detected, the undetected fault set is updated. The scheme can at least achieve the following beneficial technical effects: the second stage still maintains the test vectors originally allocated to each thread, and only changes the fault acquisition granularity, that is, from acquiring multiple faults in a fault block to acquiring only a single fault, so as to better optimize fault allocation when the remaining undetected faults are relatively few, and to guarantee the accuracy of the results as much as possible through the second stage.

[0013] Optionally, the method further comprises: maintaining an already processed thread list for each undetected fault, the list recording the thread ID of the thread that has injected the fault but has not detected the fault; when each thread performs the simulation of the second stage, the already processed thread list is used to shield the faults that have not been detected by itself when entering the second stage, and the simulation is performed on the faults that have not been injected. The scheme can at least achieve the following beneficial technical effects: the scheme can enable the thread to effectively identify the faults simulated by itself when entering the second stage, so as to effectively reduce invalid work.

[0014] Optionally, the method further comprises: when all threads complete the simulation of the second stage, marking the detected faults and the undetected faults on the fault list. This scheme can at least achieve the following beneficial technical effects: marking the detected faults and the undetected faults can facilitate the user to better analyze how to optimize the circuit and improve the performance of the circuit.

[0015] Optionally, when a thread completes the simulation of the first stage, the thread directly enters the simulation of the second stage without waiting for other threads to complete the simulation of the first stage. This scheme can at least achieve the following beneficial technical effects: avoiding the case that a certain thread completes the task first and needs to wait for other threads to complete the simulation of the first stage, and improving the utilization of computing resources.

[0016] Optionally, the value range of M is [2N, 3N]. This scheme can at least achieve the following beneficial technical effects: experiments show that when the value of M is about 2-3 times the number of threads, the overall simulation performance is relatively optimal.

[0017] According to a second aspect of the present application, an electronic device is provided, comprising: one or more processors; and a memory, wherein the memory is configured to store executable instructions; and the one or more processors are configured to implement the steps of the method of the first aspect by executing the executable instructions. BRIEF DESCRIPTION OF DRAWINGS

[0018] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of test vector and fault allocation for the first stage of the existing algorithm 1;

[0020] Figure 2 A flowchart of a two-stage fault simulation method based on a multi-core CPU according to an embodiment of the present application;

[0021] Figure 3 A schematic diagram of test vector and fault allocation for the first stage of a two-stage fault simulation method based on a multi-core CPU according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] As mentioned in the background technology section, there is currently a lack of effective algorithm design, and the load balancing and task scheduling strategies between threads need to be improved. To date, no effective method has been found to effectively combine various optimization strategies with multi-threaded algorithms. Existing technologies usually divide all test vectors and faults equally and distribute them all at once. However, the time it takes for different threads to complete the divided faults may vary, causing some threads to wait for other threads to complete the remaining calculations before starting the next stage of calculation, resulting in resource waste and affecting the overall simulation efficiency. See the multi-threaded scheduling method shown in the following existing algorithm 1:

[0024]

[0025] The meaning of each line of the algorithm is as follows:

[0026] Input: test set partition Ti, fault list partition Fi, where the test set refers to the test vector set;

[0027] Line 01: For all test vectors t in the test set partition Ti, start processing.

[0028] Line 02: Select w test vectors from the test set Ti to form a subset Tw.

[0029] Line 03: Perform bit-parallel simulation in the fault-free circuit on the subset Tw to obtain the correct reference results after each test vector is input.

[0030] Line 04: Initialize Fdi to an empty set for storing detected faults.

[0031] Line 05: For each test vector tk in the test set Ti, perform the following operations.

[0032] Line 06: Select w faults from the fault list partition Fi to form the fault subset Fw.

[0033] Line 07: Perform bit-parallel simulation of the faulty circuit on the test tk and the fault subset Fw, and compare the results with the reference results to detect the faults, and obtain the detected fault set Fdet.

[0034] Line 08: Updates Fi, removing the fault Fw that has been selected for simulation.

[0035] Line 09: Add the detected fault Fdet to Fdi.

[0036] Line 10: If the ratio of the number of detected faults to the number of faults in Fi is less than the set drop rate (DropRate), then exit the loop.

[0037] Line 11: Break out of the loop and do not perform more tests.

[0038] Line 12: Lock the shared fault list F to ensure data consistency during the update process.

[0039] Line 13: Update the shared fault list F by removing the faults in Fdi that have already been detected.

[0040] Line 14: Unlock the shared fault list F to release the lock.

[0041] Line 15: Return the updated shared fault list F.

[0042] Algorithm 1 is based on the parallel fault model, where each thread has its own test vector and fault sub-list, and they are independent of each other, as shown in Figure 1 . The allocation of test vectors t1-t12 and faults 1-12 to threads 1-3 is balanced. However, there is a potential problem when the number of remaining faults is small, near the end of the simulation process. When using the parallel fault model, a thread needs to acquire a certain number of fault instances related to the parallel bit position to perform simulation, which leads to a large amount of mutual waiting time for other threads while waiting for the release of faults. For example, if a machine can handle 8-bit data in parallel, then each thread can simulate 8 faults in parallel. However, when the number of fault instances acquired by a thread is less than 8, it needs to wait for other threads to complete the simulation and release the undetected fault instances. These undetected fault instances will be added to the fault set of the current thread to continue the simulation. This mechanism leads to a large amount of mutual waiting time between threads, which affects the overall simulation efficiency.

[0043] It can be seen that the balanced allocation of test vectors and faults in Algorithm 1 actually affects the overall performance. Because when a thread completes its simulation task earlier than other threads, it must wait until other threads complete their tasks, and then all threads enter the second phase. This does not fully utilize the efficiency of multi-threading. Although it introduces the DropRate metric to terminate this phase in advance to solve this problem, there is still a large amount of idle waiting time for most threads.

[0044] To this end, the present application optimizes the existing multi-thread fault simulation acceleration technology to improve the performance and effectiveness of fault simulation and meet the growing simulation needs. Embodiments of the present application set the number of fault blocks M to be greater than the number of threads N, and do not allocate fault blocks to each thread at a time, optimizing the task allocation and inter-thread cooperation mechanism, with low inter-thread communication cost. Among them, each thread acquires and tests a single fault block in the first stage, and acquires the next fault block after testing each fault block, avoiding the situation that each thread acquires multiple fault blocks and some threads may complete the processing of their allocated fault blocks and have to wait for other threads to complete the related calculation due to processing speed deviation; the thread that completes the simulation of the acquired fault block can continue to acquire and process the fault blocks (remaining fault blocks) that have not been acquired by the thread until all fault blocks are acquired. Moreover, after each thread completes the simulation of the first stage, it can enter the next stage without waiting for other threads to complete the test, and detect the faults that have not been detected to improve the detection efficiency and ensure the accuracy of the results; in addition, in the first stage, since the fault amount is large at this time, the fault blocks are acquired in units of fault blocks to avoid excessive allocation of faults in the early stage; and in the second stage, the faults are acquired in units of faults to avoid locking too many faults by a single thread to improve the simulation efficiency.

[0045] According to an embodiment of the present application, referring to Figure 2 , a two-stage fault simulation method based on a multi-core CPU is provided, including steps S1, S2 and S3.

[0046] Step S1: acquiring a circuit model to be tested, a test vector set and a fault list, wherein the test vector set includes a plurality of test vectors, and the fault list includes a plurality of faults to be injected.

[0047] According to an embodiment of the present application, the circuit model refers to a simulation model corresponding to an integrated circuit that needs to be tested. For example: a model corresponding to an integrated circuit designed by TC01, TC02, TC03, TC04, TC05, TC06, TC07, TC08, TC09 or the implementer himself.

[0048] According to an embodiment of the present application, the test vector set is a specific set of input signal sequences, which is used to apply to the input end of a digital circuit. Usually, a series of test vectors are generated according to the design description and fault model information of the circuit, which can maximize the test coverage and detect all possible faults. Then, by observing the output response of the circuit under the action of these input signal sequences, it can be verified whether the circuit meets the design specifications or whether there is a fault in the circuit.

[0049] According to one embodiment of the present application, the faults refer to artificially introduced fault points in the circuit model, used to simulate defects that may occur in actual operation of the circuit. By injecting these faults and observing the behavior of the circuit, the testability of the circuit can be evaluated, the effectiveness of the test vectors can be verified, and potential problems can be located. The fault list includes, for example, stuck-at faults, bridge faults, transient faults, and / or open / closed faults.

[0050] Step S2: Obtain the number N of threads of the multi-core CPU, evenly distribute the plurality of test vectors to the N threads, divide the plurality of faults into M fault blocks, and obtain a fault block set, wherein M>N.

[0051] According to one embodiment of the present application, for test vectors, a one-by-one allocation manner can be adopted, so that the number of test vectors allocated to each thread is as equal as possible (with a difference of 0 or 1). For example, assuming that there are 99 test vectors that need to be evenly distributed to 4 threads: thread 1 is allocated 25 vectors, thread 2 is allocated 25 vectors, thread 3 is allocated 25 vectors, and thread 4 is allocated 24 vectors. Of course, if there are more test vectors, the implementer can also allocate more test vectors (2, 3, or 4, etc.) to a thread each time according to the specific situation until all test vectors are allocated, so as to improve the allocation efficiency.

[0052] According to one embodiment of the present application, for the division of fault blocks, the present application no longer performs balanced division, but divides more fault blocks than the number of threads, so that when some threads complete the simulation of the obtained fault blocks, the remaining fault blocks can be obtained for simulation, thereby avoiding invalid waiting and more effectively utilizing the computing resources. See Figure 3 As can be seen, threads 1-3 still evenly allocate test vectors t1-t12 at one time, but not all fault blocks f1-f12 are allocated. Preferably, the value range of M is [2N, 3N]. The technical scheme of this embodiment can at least achieve the following beneficial technical effects: experiments show that when the value of M is about 2-3 times the number of threads, the overall simulation performance is relatively optimal.

[0053] According to one embodiment of the present application, when dividing fault blocks, all fault blocks can be divided into the same size, simplifying the difficulty of division.

[0054] If the fault list is large, it can result in a single fault block being large, and if the fault block is divided too small, it can result in frequent reading of the fault block, resulting in a large access overhead. According to an embodiment of the present application, the method further comprises: when dividing the fault block, setting different fault block sizes, dividing X first fault blocks of equal size and Y second fault blocks smaller than the first fault blocks, X being greater than zero and being an integer multiple of the number of threads, X+Y=M. For example, the fault list is divided into N first fault blocks of a first size and M-N second fault blocks of a second size, wherein the first size is larger than the second size. The size is measured in terms of the number of faults. In this way, at the beginning, each thread can obtain a larger fault block to reduce the access overhead, and the size of the remaining fault blocks is relatively smaller, which can reduce the situation that a certain thread gets more tasks later, resulting in the simulation progress falling behind other threads too much, and improve the overall simulation performance.

[0055] Step S3: performing simulation by the N threads according to the preset two-stage fault simulation manner, which includes performing the following operations by each thread respectively: performing simulation of the first stage, which includes: each thread obtains one remaining fault block for testing each time until the fault block obtained by itself has completed testing and there is no remaining fault block, and then enters the simulation of the second stage, wherein the undetected faults are updated according to the detected faults and the fault list; and performing simulation of the second stage, which includes: testing all undetected faults using the test vectors allocated by itself.

[0056] According to one embodiment of the present application, the first-stage simulation comprises: maintaining a shared remaining fault block set and a shared undetected fault set shared by each thread, wherein the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: each thread obtains one remaining fault block from the remaining fault block set each time, and removes it from the remaining fault block set; inputs the test vector allocated to itself into the circuit model to obtain a first result; individually injects each fault in the obtained fault block into the circuit model to obtain a corresponding circuit fault model; inputs the test vector allocated to itself into the circuit fault model to obtain a second result; detects each fault, wherein whether the fault is detected is determined according to the first result and the second result, and if the fault is detected, the undetected fault set is updated. In VLSI simulation, a test vector is a sequence of input signals used to activate and detect circuit faults. By inputting a test vector into a circuit, it can be observed whether the output response is consistent with the expectation, so as to determine whether the circuit has a fault. That is, if the first result and the second result are inconsistent when simulating a certain fault, it indicates that the fault is detected. In addition, when a thread completes the first-stage simulation, the thread directly enters the second-stage simulation without waiting for other threads to complete the first-stage simulation. This scheme can at least achieve the following beneficial technical effects: the present application balances the workloads among threads by using a new fault block allocation strategy, thereby improving the performance and effectiveness of fault simulation.

[0057] According to one example of the present application, the schematic process of the first-stage simulation of the method of the present application is shown in Algorithm 2:

[0058]

[0059] The meanings of the rows of the algorithm are as follows:

[0060] Data: test vector Ti allocated to thread i, fault block list Fb, detected fault set Fdi;

[0061] Result: updated shared fault list F, F refers to a set of undetected faults.

[0062] Row 01: initialize the detected fault set Fdi to an empty set.

[0063] Row 02: start processing for each fault block fbj in the fault block list Fb:

[0064] Row 03: perform a mutual exclusion operation on fbj.

[0065] Row 04: if fbj has been allocated:

[0066] Line 05: Unlock operation on fbj.

[0067] Line 06: Continue with the next fault block.

[0068] Line 07: Else:

[0069] Line 08: Assign fbj to the thread with thread ID i.

[0070] Line 09: Unlock operation on fbj.

[0071] Line 10: For all test vectors in test vector set Ti, begin processing:

[0072] Line 11: Select w test vectors from Ti to form Tw.

[0073] Line 12: Simulate Tw under fault-free circuit to get correct reference results.

[0074] Line 13: For each fault f in fbj:

[0075] Line 14: Call function PPSPF model with input Tw to simulate under faulty circuit and compare the results with reference results to detect faults to get detected fault set Fdet.

[0076] Line 15: Incorporate Fdet into Fdi.

[0077] Line 16: Mutual exclusion operation on the remaining fault list F shared by all threads.

[0078] Line 17: Update the remaining fault list F as F minus Fdi.

[0079] Line 18: Unlock operation on the remaining fault list F.

[0080] Line 19: Return.

[0081] According to one embodiment of the present application, the simulation in the second stage comprises repeatedly performing the following processes: obtaining the latest undetected fault set, extracting only one undetected fault therefrom; injecting the undetected fault into the separate injection circuit model to obtain the circuit fault model corresponding to the undetected fault; inputting the circuit fault model corresponding to the undetected fault with the test vector allocated thereto to obtain the third result; detecting the undetected fault, wherein whether the fault is detected is determined according to the first result and the third result, and if the fault is detected, the undetected fault set is updated. Since some test vectors can detect the corresponding fault, and this is not considered in the division, the present application uses the test vector allocated to each thread to detect the fault in the undetected fault set in the second stage, so as to guarantee the accuracy of the result. Moreover, the second stage still maintains the original test vector allocated to each thread, and only changes the granularity of obtaining the fault, i.e., from obtaining multiple faults in a fault block to obtaining only one fault, so as to better optimize the fault allocation when the remaining undetected faults are relatively few.

[0082] According to one embodiment of the present application, the method further comprises: maintaining a processed thread list for each undetected fault, the list recording the thread ID that has injected the fault but failed to detect the fault; and when each thread performs the simulation in the second stage, masking the fault that has not been detected by itself according to each processed thread list, and selecting the fault that has not been injected for simulation. For example, assuming that there are four threads (Thread 0-3), the number of faults is 80 (Fault 0-79), and eight fault blocks are divided, wherein the fault block containing Fault 0 is allocated to Thread 0, and Thread 0 has not detected Fault 0. Then a processed thread list [Thread 0] is maintained for the undetected Fault 0, and Thread 0 will mask Fault 0 in the second stage, i.e., Fault 0 will not be selected for simulation again. The technical scheme of this embodiment can at least achieve the following beneficial technical effects: this scheme can enable the thread to effectively identify the fault that has been simulated by itself when entering the second stage, so as to reduce invalid work.

[0083] According to one embodiment of the present application, the method further comprises: after all threads complete the simulation in the second stage, marking the detected faults and the undetected faults on the fault list. For example: assuming that there are Fault 0-79, the undetected faults are marked as Fault 0 and Fault 78, and the remaining faults are marked as detected faults. Of course, a more detailed result can also be given, i.e., the first result, the second result and the third result obtained by each fault in the simulation, so as to facilitate comparison by the implementer. The technical scheme of this embodiment can at least achieve the following beneficial technical effects: marking the detected faults and the undetected faults can facilitate the user to better analyze how to optimize the circuit and improve the performance of the circuit.

[0084] According to one example of the present application, a schematic two-stage fault simulation method is given, comprising:

[0085] The first stage is to evenly distribute the test vectors to each thread according to the number of threads, and the faults are divided into blocks according to 2 times the number of threads, each thread takes one fault block and uses the test vector allocated to itself to simulate, and each thread dynamically acquires the remaining fault blocks that have not been acquired after the simulation of the allocated fault block is completed, to perform a load balancing task allocation strategy.

[0086] The second stage is to use the test vector allocated to each thread in the first stage to test all the remaining faults that have not been detected, to ensure the correctness of the results.

[0087] In addition, the method of the present application can be improved on the basis of Algorithm 1, and the adjustment is as follows:

[0088] (1) For the test vector, the original test vector allocation strategy is retained, that is, based on the number of threads, the allocation is evenly distributed;

[0089] (2) For the faults, they are divided into independent sub-blocks, and the number of sub-blocks is 2 times the number of threads (2 * threads). This value is an empirical value determined through our experiments;

[0090] (3) In the independent stage, when all fault sub-blocks are allocated, each thread enters the dynamic cooperation stage immediately after completing its own simulation task, without waiting for the entire independent stage to end;

[0091] (4) By checking the thread ID allocated to each fault sub-block during the allocation period in the independent stage, each thread in the dynamic cooperation stage can determine whether it has previously processed the fault sub-block in the first stage, to avoid redundant work;

[0092] (5) Replace the parallel fault simulation model of Algorithm 1 with the PPSFP model. In the PPSFP model, only one fault is simulated at a time, which significantly reduces the communication cost between threads and increases the parallelism between threads;

[0093] (6) Delete the drop rate index introduced in Algorithm 1, because it is no longer applicable. Because the optimized algorithm uses fault blocks, the simulation in the first stage ends when all fault blocks are simulated, and the single-simulation fault detection rate is no longer used as a standard. The drop rate (DropRate) is the original single-simulation fault detection rate index, so it is no longer needed.

[0094] The example optimizes the existing multi-threaded fault simulation method to improve the performance and effectiveness of fault simulation to meet the growing simulation needs. On the basis of the existing multi-threaded fault simulation scheduling algorithm, the task allocation and inter-thread scheduling strategy are optimized, and the parallel pattern single fault propagation (PPSFP) model is used to replace the original parallel fault simulation model, which has a lower inter-thread communication cost. Compared with the previous solutions, multi-dimensional acceleration results are achieved. A new fault block allocation strategy is proposed to balance the workload between threads.

[0095] To verify the effect of the method of the application, the inventors also conducted the following experiments:

[0096] Experimental conditions: The nine test circuits provided by EDA2 were tested on a Kunpeng920 processor, and the acceleration effect of the fault simulation comprehensive model in small and large circuits was comprehensively evaluated.

[0097] The experimental results are shown in Table 1:

[0098] Table 1 Performance of multi-threaded algorithm under different thread counts

[0099] In Table 1, the multi-threaded algorithm is compared with the single-threaded algorithm with excellent performance. The choice of thread count will affect the effectiveness of the multi-threaded algorithm. Too few threads may not fully utilize the advantages of a multi-core system, while too many threads may result in reduced efficiency due to high inter-thread communication costs. Given that the test server has 32 cores, the experiment started with 32 threads and gradually increased by 16 threads, eventually reaching 80 threads. Then, the speedup ratio of each thread count was calculated to compare the results. The experimental results show that as the number of threads increases from 32 to 64, the performance of the algorithm gradually improves. However, when the number of threads reaches 80, the efficiency begins to decline. Therefore, it can be concluded that the optimal number of threads to maximize the effectiveness of the multi-threaded algorithm model in the experiment is 64, and the average speedup ratio of all circuits is 2.986. The results show that the study performs similarly to traditional multi-threaded simulation optimization strategies in small circuits, but significantly outperforms them in large circuits, indicating that the application can achieve an acceleration ratio of about 3 times in most circuits even when the performance of the single-threaded simulation algorithm is good enough. This finding provides important empirical support for the progress of fault simulation technology and highlights the potential of the application in large-scale circuit simulation.

[0100] It is to be understood that even though various steps of the method are described in a particular order, the method can be performed in a different order, or some of the steps can be performed concurrently, or even changed, so long as the desired function is performed.

[0101] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0102] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves.

[0103] Embodiments of the application have been described above, and the description is not exhaustive, and does not limit the scope of the disclosed embodiments. Many modifications and variations of the described embodiments will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The description is intended to cover any and all modifications and variations, including such concepts contained therein of which the author is not explicitly aware. The terms used herein are to be construed in their broadest, ordinary sense, and are not to be limited by any slight changes that can be made to the specification.

Claims

1. A two-stage fault simulation method based on a multi-core CPU, comprising: Obtaining a circuit model to be tested, a test vector set, and a fault list, wherein the test vector set includes multiple test vectors, and the fault list includes multiple faults to be injected; Obtain the number of threads N of the multi-core CPU, evenly distribute multiple test vectors to the N threads, divide multiple faults into M fault blocks, and obtain a fault block set, where M>N; N threads perform simulation according to a preset two-stage fault simulation method, which includes each thread performing the following operations: Executing a first phase of simulation, which includes: each thread acquires one remaining fault block at a time for testing, and transitioning to a second phase of simulation when the acquired fault block has been tested and there are no remaining fault blocks, wherein undetected faults are updated based on the faults detected during the simulation and the fault list; and The second stage of simulation is performed, which includes testing all undetected faults using the test vectors assigned to them.

2. The method according to claim 1, characterized in that The first phase of simulation includes: Maintain the remaining fault block set and the shared undetected fault set shared by each thread, where the remaining fault block set is initially a set of M fault blocks, and the undetected fault set is initially a set of all faults in the fault list; each thread is configured to perform the following processing: Each thread obtains a remaining fault block from the remaining fault block set each time and removes it from the remaining fault block set; Input the test vector assigned to the circuit model to obtain a first result; Inject each fault in the acquired fault block into the circuit model separately to obtain the corresponding circuit fault model; Using the test vector assigned to itself as input to the circuit fault model, a second result is obtained; Detection is performed for each fault, wherein whether the fault is detected is determined according to the first result and the second result; if the fault is detected, the undetected fault set is updated.

3. The method according to claim 1 or 2, characterized in that The second stage of simulation consists of repeatedly executing the following processes: Get the latest set of undetected faults and extract only one undetected fault from it; Injecting the undetected fault into a separate injection circuit model to obtain a circuit fault model corresponding to the undetected fault; Using the test vector assigned to itself as input into the circuit fault model corresponding to the undetected fault, to obtain a third result; Detection is performed on the undetected fault, wherein whether the fault is detected is determined according to the first result and the third result; if the fault is detected, the undetected fault set is updated.

4. The method according to claim 1, wherein The method further comprises: Maintain a processed thread list for each undetected fault, which records the thread IDs that have been injected with the fault but not detected; When each thread performs the second stage of simulation, it masks the faults that have not been detected by itself according to the list of each processed thread, and selects the faults that have not been injected for simulation.

5. The method according to claim 1, wherein The method further comprises: When all threads have completed the second phase of simulation, the detected faults and undetected faults are marked on the fault list.

6. The method according to claim 1, characterized in that When a thread completes its first phase of simulation, the thread directly enters the second phase of simulation without waiting for other threads to complete their first phase of simulation.

7. The method according to claim 1, characterized in that The value range of M is [2N, 3N].

8. A computer program product comprising a computer program / instruction, which implements the steps of the method according to any one of claims 1 to 7 when executed by a processor.

9. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; as well as a memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method of any one of claims 1 to 7 by executing the executable instructions.

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