High-performance switch shared cache control system

Abstract

The invention provides a shared cache control system for a high-performance switch. The shared cache control system comprises a plurality of port modules, a plurality of memory allocation modules, a plurality of memory recovery modules, a dynamic channel allocation module and an SRAM (Static Random Access Memory) array, the dynamic channel distribution module is used for cross communication among the port module, the memory distribution module, the memory recovery module and the SRAM array; the port module is used for receiving and transmitting data packets, scheduling other modules to work and performing read-write operation on addresses in the SRAM array; the memory allocation module is used for allocating a memory space address for the data packet and recording an idle state or an occupied state of an SRAM address space by adopting a vector mapping mechanism; and the recovery module is used for requesting the destination port to read the data packet and recovering the memory address space corresponding to the read data packet. The method has the beneficial effect that the switching rate of the shared cache type switch is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of cache control, and in particular to a high-performance switch shared cache control system. Background Art

[0002] With the rapid development of fifth-generation communication technology and large models of artificial intelligence, the importance of intelligent network devices in people's lives has become increasingly prominent. Users' requirements for network bandwidth, reliability, and stability have also increased accordingly. At present, data storage and scheduling occupy most of the time and become the main bottleneck in the communication and large model training and inference process. Therefore, it is urgent to have extremely high data storage capabilities for network devices such as switches and routers. To this end, it is necessary to design a high-bandwidth, multi-port shared cache controller to meet the needs of modern communication technology.

[0003] In traditional shared cache switches, the SRAM free address allocation and SRAM memory recycling mechanisms are inefficient. Specifically, after completing the service of a port, the system needs to wait for the port to release resources before the next port that needs service can start working. However, the port actually only needs service when reading and writing SRAM. This polling method invalidates the shared cache and takes up a lot of time, thereby increasing the delay of data transmission and reducing the overall performance.

[0004] The queue scheduling method of traditional switches is weighted round-robin scheduling. The problem with this method is that when no queue makes an arbitration request within a certain period, the authorization counts of all queues will be reset. This weakens the effect of weighted round-robin when the requests are not frequent, and further affects the effective allocation of bandwidth between queues of different priorities. In addition, if a high-priority queue has unused weights but no new requests arrive for a long time, it will also cause resource waste or even blockage.

[0005] In traditional shared cache switches, CrossBar is often used as the switching matrix, which has advantages such as simple implementation and flexibility. However, as the scale increases, the cost and power consumption will increase dramatically. In a high-speed network environment, switching delay becomes a performance bottleneck. The total bandwidth of the internal switching rate of a traditional shared cache switch = SRAM bit width × frequency × utilization. However, both the bit width and frequency are limited by the manufacturing process, and the utilization is affected by the time-consuming port service polling and shared cache storage management. These factors cannot be improved infinitely. Therefore, they have become bottlenecks that limit the further improvement of the switching rate of shared cache switches. Summary of the invention

[0006] The technical problem to be solved by the present invention is: a high-performance switch shared cache control system, aiming to improve the exchange rate of the shared cache switch.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: a high-performance switch shared cache control system, including: multiple port modules, multiple memory allocation modules, multiple memory recycling modules, a dynamic channel allocation module and an SRAM array;

[0008] The dynamic channel allocation module is used for cross communication between the port module, the memory allocation module, the memory recovery module and the SRAM array;

[0009] The port module is used for receiving and sending data packets, scheduling the work of other modules, and performing read and write operations on addresses in the SRAM array;

[0010] The memory allocation module is used to allocate memory space addresses for data packets and use a vector mapping mechanism to record the idle state or occupied state of the SRAM address space;

[0011] A memory recovery module is used to request the destination port to read out data packets and to recover the memory address space corresponding to the read data packets;

[0012] Among them, the memory recovery module receives the descriptor of the data packet that has been written into the SRAM array from the port module, manages the descriptors through multiple FIFOs with different priorities, and works for the FIFO through multiple state machine queues. After weighted polling arbitration between the FIFOs, it is determined that all state machine queues work for a certain FIFO after serving it. The state machine queue takes the descriptor, and the port module is scheduled to read the corresponding data packet through the descriptor. After completion, the descriptor is sent to the memory allocation module to schedule it to clear the occupancy mark of the address space of the data packet corresponding to the descriptor, so as to realize the request to read the data packet and memory recovery at the destination port.

[0013] Furthermore, the memory recycling module is provided with a weighted polling arbiter, a plurality of FIFOs of different priorities and a plurality of state machine queues;

[0014] The FIFO is used to store descriptors of corresponding levels. When the FIFO is not empty, it actively sends a service request signal to the weighted polling arbitrator. After receiving at least one valid service request signal, the weighted polling arbitrator marks all FIFOs in the request state as pending, and starts a round-robin selection process based on the weight ratio, and only performs an authorization operation once for each FIFO marked as pending, and can only get one opportunity in the same round; the selected FIFO is jointly completed by all state machine queues to complete the required amount of data retrieval and task scheduling work, and the control right is released immediately after completion, and the pending mark of the FIFO is cleared. For the remaining FIFOs that have not been selected and still have pending marks, they will continue to participate in polling until all pending marks are cleared. After all pending marks are cleared, the weighted polling arbitrator starts a new round of weighted polling.

[0015] Furthermore, when a FIFO is exhausted, a control right release signal is immediately sent to the weighted polling arbitrator.

[0016] Furthermore, the bandwidth allocated to each FIFO by the weighted polling arbiter is adjusted through the APB interface dynamically configuring the register value, thereby adjusting the weight of each FIFO.

[0017] Furthermore, the memory recycling module also includes a data distributor for storing the received data packets into the corresponding priority FIFO according to the priority information thereof.

[0018] Furthermore, the memory recovery module also includes a TAG FIFO for scheduling the state machine queue. Each queue is assigned a TAG value. When the state machine queue is idle and has a data packet or descriptor processing requirement, it applies for the corresponding TAG through fair polling arbitration to obtain work authorization.

[0019] Furthermore, the descriptor includes: source port, destination port, data packet length, priority, module id, multicast destination port and multicast enable.

[0020] Furthermore, each port module is internally configured with multiple FIFOs for storing data packets, multiple state machine queues, TAG FIFOs, fair polling arbitrators, data distributors, information vector tables, and state vector tables;

[0021] The data distributor is used to distribute the received data packets to the FIFO; the FIFO is used to store the data packets; the state machine queue applies to the TAG FIFO for the corresponding work authorization through the fair polling arbitrator; the information vector table is used to store the frame header information of the data packet; the state vector table is used to identify the work process and guide the operation of the state machine by changing the register value in the state vector table after the port module successfully establishes communication with other modules and completes the handshake protocol.

[0022] Furthermore, the frame header information of the data packet includes a source port, a destination port, a data packet length, a priority, a multicast destination port and a multicast enable.

[0023] Furthermore, the dynamic channel allocation module is integrated with a load balancing module and a routing module;

[0024] The dynamic channel allocation module first receives a request from the host and simultaneously obtains the real-time status information of all slaves; the port module acts as the host, and the memory allocation module and the memory recovery module act as slaves; based on the real-time status information of the slaves, the dynamic channel allocation module arbitrates the request of the host to determine which host to provide services for; after determining which host to provide services for, the load balancing module further arbitrates the slaves in the idle state and allocates the request to the slave that has obtained arbitration authorization; the index of the slave that has obtained arbitration authorization is output to the routing module, and the routing module selects the corresponding line according to the slave index to complete the data transmission between the host and the slave.

[0025] The beneficial effects of the present invention are as follows: the technical solution manages the SRAM array composed of multiple SRAMs in a refined manner by means of memory space mapping vectors, and performs dynamic memory allocation and recycling after reading and writing data packets, which greatly improves the utilization rate of the shared cache. All ports can write data packets to any position of the SRAM array through the dynamic channel allocation module, and each port may be at a different position in the workflow, and the port only needs to participate in polling to apply for the bus to read and write SRAM when reading and writing SRAM, which reduces time consumption and greatly improves the total bandwidth. The technical solution of the present invention optimizes the weighted polling scheduling mechanism, solves the problem of resetting the authorization count of all queues in a cycle without requests, and the problem of resource waste and blocking caused by the high priority queue having no new requests for a long time, thereby improving the effective allocation of bandwidth between queues of different priorities. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the mechanisms shown in these drawings without paying any creative work.

[0027] Figure 1 A block diagram of a high-performance switch shared cache control system according to an embodiment of the present invention;

[0028] Figure 2 is a structural block diagram of a port module according to an embodiment of the present invention;

[0029] Figure 3 A structural block diagram of a memory recycling module according to an embodiment of the present invention;

[0030] Figure 4 A structural block diagram of a dynamic channel allocation module according to an embodiment of the present invention;

[0031] Figure 5 A block diagram of a global shared cache implementation method according to an embodiment of the present invention;

[0032] Figure 6 A memory space mapping vector block diagram of an embodiment of the present invention;

[0033] Figure 7 A flowchart of a data writing process according to an embodiment of the present invention;

[0034] Figure 8 A flowchart of a data reading process according to an embodiment of the present invention;

[0035] Fig. 9 A structural diagram of a data packet frame header according to an embodiment of the present invention;

[0036] Fig.10 This is a descriptor structure diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] It should be noted that the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0039] like Figure 1 As shown, the embodiments of the present invention are: Figure 1 The overall architecture of the high-performance switch shared cache control system provided by the embodiment of the present invention is shown. The system includes a port module, a memory allocation module, a memory recycling module, a routing module, a dynamic channel allocation module and an SRAM array.

[0040] In this embodiment, the system is configured with 16 port modules and an SRAM array consisting of 16 SRAMs. The number of memory allocation modules and memory recycling modules can be parameterized according to requirements, and can be configured to a maximum of 16. The same module works independently and is not affected by other modules, so each module may be in a different process. Cross-communication between modules is achieved through routing modules and dynamic channel allocation modules.

[0041] In the present embodiment, the system allows all ports to share a unified SRAM array resource to achieve efficient data packet storage and forwarding functions. Whenever any source port receives a new data packet, it will apply for memory space from the memory allocation module and store the data packet in the SRAM array. Each port module may be in a different workflow, and will only participate in arbitration to apply for the bus to read and write SRAM when it is necessary to read and write SRAM. As long as there are data packets in the SRAM array that are not read by the destination port, the memory recovery module will continuously initiate a read request, aiming to read the data packets stored in the SRAM array from the destination port. The memory recovery module will then initiate a recovery request to release the previously occupied space for subsequent use, thereby ensuring the stable operation of the entire system and efficient use of existing hardware resources.

[0042] The read and write interface between the system and the outside is located in the port module. When an external request is made to write data, the port module will temporarily store the data packet, and splice the data packet size, priority, destination port and other information in the frame header to generate a descriptor corresponding to the data packet, and then send this descriptor to the memory allocation module. The memory allocation module queries the free memory space in the shared cache that matches the size of the data packet based on the descriptor, and allocates an address for the data packet. At the same time, the memory allocation module marks the allocated address as occupied by vector mapping. After obtaining the address, the port module writes the data packet into the shared cache. After the writing is completed, the port module sends the descriptor to the memory recovery module. The memory recovery module stores the descriptor in the FIFO and actively initiates a read data request to the port module. After the destination port reads the data packet, the memory recovery module uses the descriptor to communicate with the memory allocation module to clear the vector occupation mark corresponding to the data packet in the memory allocation module, thereby completing the forwarding of the data packet and the memory recovery process.

[0043] Figure 2 The port module structure of the present invention is shown. The port module is an interface module for the system to read and write data externally, and is responsible for the sending and receiving of data packets, scheduling system workflow, and the reading and writing operations of SRAM. Each port module is internally configured with 8 FIFOs for storing data packets, 8 state machine queues, a TAG FIFO, a fair polling arbiter, a data distributor, an information vector table, and a state vector table.

[0044] The 16-port module has exactly the same structure and function. Each port may be in a different stage of writing or reading data, and they are independent of each other and work in parallel.

[0045] The 8 internal state machine queues are scheduled through TAG FIFO. TAG is a tag. Each queue has an independent TAG value. After getting the TAG belonging to this queue, the state machine can be started. In this way, the 8 state machine queues are scheduled to work in parallel and out of order. TAG FIFO has 8 depths and stores integers from 0 to 7 as TAGs. Each queue corresponds to a unique TAG. For example, state machine queue 0 corresponds to TAG 0. When the queue is idle and there is a need to send or receive data packets or descriptors, it will participate in fair polling arbitration to apply for the corresponding TAG from TAG FIFO. Once the TAG is obtained, the work authorization is obtained, the state machine is started, and after completing all states, the TAG is pushed back to the TAG FIFO. This mechanism allows multiple queues to process multiple tasks in parallel and out of order.

[0046] The TAG FIFO depth is 8. When the power is on, the 8 data are reset to 8 integers from 0 to 7, which correspond to the TAG values ​​of the 8 queues as passes. At the same time, the write pointer in the FIFO is increased by 8. In this way, a FIFO that is full after power-on will be obtained, and all 8 tags are in the FIFO.

[0047] In the port module, there are two situations in which the state machine queue applies for TAG: the first is when writing data packets (WP), the external sends a request to the port to write data; the second is when reading data packets (RP), the memory recovery module requests the port module to read the data packet corresponding to the descriptor and perform corresponding memory recovery. In these two situations, the eight queues apply for TAG from the TAG FIFO through the fair polling arbiter.

[0048] Similarly, the state machine queue returns the tag in two cases: the first is when writing a data packet (WP), when the data packet is written into the SRAM, the queue returns the tag to the tag FIFO; the second is when reading a data packet (RP), when the data packet is read from the destination port module, the task of returning the tag begins. In both cases, the 8 queues return the tag by pushing the tag back to the tag FIFO through the fair polling arbiter.

[0049] When an external request is made to write a data packet, the state machine queue extracts the information in the packet header, such as Fig. 9 As shown, including source port, destination port, packet length, priority, multicast destination port and multicast enable, the packet header information is stored in the information vector table constructed by the register. Furthermore, some fields in the packet header information such as packet length, priority and destination port will be spliced ​​into descriptors for scheduling other modules to complete packet forwarding and memory recovery functions.

[0050] In the process of communicating with other modules, additional information is recorded in the information vector table, including address, SRAM ID, memory recovery module ID, memory allocation module ID, ECC warning and ECC error, etc.

[0051] After the port module successfully establishes communication with other modules and completes the handshake protocol, it identifies the workflow and guides the operation of the state machine by changing the register value in the state vector table. The port module is responsible for updating and maintaining the information vector table and the state vector table to manage the queues of the eight state machines and realize parallel and unordered workflow.

[0052] exist Figure 3The structure and function of the memory recycling module are described in detail in the paper. The core of the memory recycling module is to set up multiple FIFOs to store the descriptors corresponding to the data packets that have been written but not yet read. The descriptors instruct the port module to read the corresponding data packets and notify the memory allocation module to release the memory space mapping vector occupation status corresponding to these data packets, thereby effectively realizing the recycling and reuse of memory resources.

[0053] In this embodiment, each memory recovery module includes: 8 independent FIFOs, each responsible for managing descriptors of corresponding priorities; 8 state machine queues for tracking and processing descriptors; a TAG FIFO for scheduling state machine queue work; a weighted polling arbitrator to ensure that the required bandwidth is allocated to data packets of different priorities; and a data distributor responsible for storing received data packets into the corresponding priority FIFO according to their priority information.

[0054] The FIFO in the memory recycling module has 8 priorities, which is designed to efficiently receive descriptors from the port module and improve the quality of service provided to descriptors of different priorities. During the descriptor reception process, the system uses the data selector to accurately allocate each descriptor to the FIFO of the corresponding priority based on the priority information carried by each descriptor. This mechanism ensures that high-priority tasks can be processed faster.

[0055] After completing the data packet reading, the memory allocation module is instructed to perform a cleanup operation according to the specific details provided by the descriptor, that is, to clear the occupied mark in the memory space address mapping vector corresponding to the read data packet.

[0056] The memory recycling module also involves an optimized arbitration mechanism to improve the efficiency and fairness of system resource allocation. The eight FIFOs are arbitrated using an improved weighted round-robin method. The problem with the traditional method is that when no queue makes an arbitration request within a certain period, the authorization counts of all queues will be reset, which weakens the effect of weighted round-robin when requests are not frequent, and thus affects the effective allocation of bandwidth between queues of different priorities. In addition, if a high-priority queue has unused weights but no new requests arrive for a long time, it will also cause resource waste or even blockage.

[0057] In view of the above problems, a new solution is proposed: eight FIFOs with different priorities are set to store task descriptors of corresponding levels. Non-empty FIFOs will actively send request signals to the weighted polling arbitrator. Once the weighted polling arbitrator receives at least one valid application, it will mark all FIFOs currently in the request state as pending and start a round-robin selection process based on weight ratio. In this process, only those FIFOs marked as pending are authorized once in turn; each FIFO can only get one chance in the same round. The marked FIFOs are authorized in turn. When a FIFO gets the authorization, all state machines serve it together, take the descriptor from it and complete the corresponding task scheduling work with other modules. After all state machines take the weighted number of descriptors together, they end the service to the FIFO, release the control right, and clear the pending mark on the FIFO. For the remaining FIFOs that have not been selected and still have pending marks, continue to authorize in turn until all processing is completed. When the pending marks of all FIFOs are cleared, a new round of weighted polling begins.

[0058] In order to prevent the entire process from being stalled due to insufficient remaining data in a single FIFO to support the scheduled number of operations, a safety measure is designed: when a FIFO is detected to be exhausted, it will immediately send a release control signal to the weighted polling arbitrator to avoid unnecessary waiting time extension. At the same time, the bandwidth allocated to each FIFO can be adjusted according to actual conditions. This function is achieved by dynamically configuring the register value through the APB interface and then adjusting the weight of each FIFO.

[0059] Figure 4 The structure of the dynamic channel allocation module is shown. This module integrates the load balancing module and the routing module, etc., to optimize the data transmission between the host (master) and the slave (slave). The port module acts as the master to send a request, and the load balancing module and the routing module allocate the request to any single idle line, and then access the corresponding slave, that is, the memory allocation module or the memory recycling module.

[0060] In this embodiment, the dynamic channel allocation module first receives a request from the master and simultaneously obtains the status information of all slaves. Based on the status information, the dynamic channel allocation module arbitrates the master's request to determine which master to provide service for. Once the service object is determined, the load balancing module further arbitrates the slaves in the idle state and allocates this request to the slave that has obtained arbitration authorization. The selected slave index is then output to the routing module, which selects the corresponding line according to the index, thereby completing the data transmission between the master and the slave.

[0061] The port module obtains a free memory allocation module through the dynamic channel allocation module to serve it, and at the same time returns the module ID to the port module for recording and storing it in Fig.10 In the descriptor shown, when the descriptor is sent to the memory recovery module, the corresponding memory recovery module and SRAM are found through the routing module according to the ID index, thereby realizing the cross-connection function.

[0062] In this embodiment, the design of the dynamic channel allocation module allows parameterization of the number of memory allocation and memory recovery modules, effectively reducing resource consumption, and is particularly suitable for use on resource-constrained hardware platforms.

[0063] like Figure 5 As shown, the dynamic channel allocation module supports any port module to access any memory allocation module or memory recycling module, so that data packets input from any port can access any SRAM area, achieving the effect of global shared cache, and realizing load balancing, which significantly improves system performance.

[0064] Figure 6The way in which the memory allocation module manages the SRAM array is shown. Each memory allocation module records the occupied and idle states of all addresses in a block of SRAM by mapping the memory space with vectors. All memory allocation modules work together to manage the occupied and idle states of the memory space of the entire SRAM array. Specifically, this management method is implemented through a one-to-one mapping relationship between the memory space address and the vector. In the initial state, all memory spaces in the SRAM array have no data, and their corresponding mapping vectors are also in an idle state. When the port module successfully requests the allocation of an address, the port module will write the data packet to the corresponding address in the SRAM array. Subsequently, the memory allocation module marks the memory space mapping vector of the address with an occupied mark to indicate that the memory space has been used. After the port module reads a data packet from an address in the SRAM array, the memory allocation module will clear the occupied mark of the address and restore it to an idle state. In this way, the memory allocation module can effectively manage the memory allocation and recycling process to ensure the efficient use of the SRAM array.

[0065] After receiving the descriptor sent by the port module, the memory allocation module first extracts the length information len of the data packet from the descriptor. Then, the memory allocation module searches for a continuous memory space whose size is greater than or equal to len to the power of 2 by querying the free mapping vector. Once a suitable continuous memory space is found, the memory allocation module sends the first address of this continuous memory space to the port module and marks the continuous memory space occupied in the free mapping vector to prevent other data packets from writing to it. This ensures the stability and security of the data transmission process and improves the overall performance of the system.

[0066] like Figure 7 , Figure 8 As shown in the figure, the forwarding process of a data packet in the system is as follows:

[0067] Write data:

[0068] (1) The write data request is initiated externally, and the port module decides whether to accept the request based on the idle state of the internal state machine queue.

[0069] (2) If the state machine is in the idle state, it will perform polling arbitration to apply for TAG, and the queue that successfully obtains TAG will store the data packet in its corresponding FIFO. It will also extract information from the data packet frame header (including source port, destination port, data packet length, priority, multicast destination port, and multicast enable, etc.), and this information will be stored in the information vector table constructed by the register.

[0070] (3) The port module selects a memory allocation module through the dynamic channel allocator and sends a descriptor to the memory allocation module to request the allocation of memory space.

[0071] (4) The memory allocation module queries the free address of the SRAM array according to the length of the data packet carried by the descriptor, and returns the first address of a continuous free memory space to the queue.

[0072] (5) The queue uses the obtained first address to write the data packet into the continuous address space starting with this address.

[0073] (6) After completing the data write operation, the queue sends the descriptor to the memory recycling module for temporary storage, waiting for further processing.

[0074] (7) The queue that has completed writing data goes through the arbitration mechanism and pushes its TAG back to the TAG FIFO.

[0075] (8) At this point, the entire data writing process is completed.

[0076] Read data:

[0077] (1) The data reading process is initiated by the memory recovery module.

[0078] (2) The memory recycling module contains 8 FIFOs for storing descriptors. These FIFOs apply for arbitration through weighted polling. Once authorized, all state machine queues serve the FIFO together. When a state machine applies for a TAG, it will take out a descriptor from the FIFO.

[0079] (3) The state machine queue that obtains the descriptor will apply for fair polling arbitration, obtain the authorized state machine control module interface signal, and send the descriptor to the corresponding port module through the routing module. The specific port module to which it is sent depends on the destination port information in the descriptor, which is completed by the routing module.

[0080] (4) After sending the descriptor, the state machine waits for the response signal from the port module. Receiving the response signal indicates that the data packet has been confirmed to be read from the destination port.

[0081] (5) After receiving the response signal from the port module, the state machine sends the descriptor to the memory allocation module, which schedules the memory allocation module to clear the memory space mark occupied by the data packet corresponding to the descriptor, thereby completing the memory recovery function.

[0082] (6) Finally, the state machine pushes the TAG back into the TAG FIFO, indicating that the state machine has completed a data reading task.

[0083] (7) At this point, the data reading process ends.

[0084] The beneficial effects of the embodiments of the present invention are:

[0085] (1) Each memory allocation module is responsible for managing a specific SRAM area. After a data packet is written, an occupied mark is added to its address. After a data packet is read, the occupied mark is cleared and the address is restored to an idle state. All memory allocation modules work together to maintain the memory space usage and idle state information of the entire SRAM array. Through this mechanism, not only can we effectively track which parts are currently occupied and which parts are available, but we can also provide accurate data support for subsequent operations. In addition, a dynamic channel allocation module is designed in the system, which allows any port module to flexibly access any memory allocation module according to actual needs, and then obtain any specified memory address resource in the SRAM array. This design enables any external device or internal component to easily implement read and write operations at any location in the SRAM array, truly realizing a shared cache function on a global scale. Moreover, among the multiple tasks of each port, only when reading and writing SRAM does it need to request SRAM to serve it, which greatly saves time cost and does not cause queue congestion. This method greatly improves the flexibility and efficiency of the overall system, and also significantly enhances the utilization of memory resources, which is particularly important for applications that require high-performance computing and fast response capabilities.

[0086] (2) In order to adapt to platforms of different sizes and reduce the consumption of hardware resources, the present invention adopts an innovative modular architecture design. Specifically, by introducing a routing module and a dynamic channel allocation mechanism, not only is an efficient inter-module interconnection network function achieved, but also the number of memory allocation modules and memory recovery modules can be flexibly adjusted according to actual needs. This design significantly reduces unnecessary hardware resource overhead and improves the scalability and flexibility of the system. In addition, in order to further improve the processing power and efficiency of the system, the present invention particularly considers the load balancing problem. By supporting multiple slave devices (Slave) to provide services for a single master device (Master), the pressure of data processing is effectively dispersed, thereby optimizing the overall performance. This solution not only enhances the robustness of the system, but also ensures that it can maintain stable operation under high concurrency. By adopting the above-mentioned technical means, the present invention greatly reduces the demand for hardware resources while ensuring the efficient operation of the system, providing strong support for the realization of a more economical and efficient solution.

[0087] (3) In order to improve service quality and performance, the present invention proposes an innovative weighted polling arbitrator design. The core function of the weighted polling arbitrator is to allocate service times to FIFO (first-in-first-out queue) according to different priorities, and all state machine queues can work together to serve the same FIFO. Specifically, the weighted polling arbitrator will perform weighted data processing after each authorization and release the authorization after processing. In addition, the present invention also solves the problem of system congestion that may be caused when the FIFO is empty. When the FIFO is detected to be empty, an end authorization signal will be issued to avoid unnecessary waiting and waste of resources. Furthermore, the present invention allows the weight of each queue to be adjusted in real time through the APB (advanced peripheral bus) configuration register, so that bandwidth can be dynamically allocated to data packets of different priorities according to actual needs. This flexible configuration method not only enhances the adaptability of the system, but also optimizes the efficiency of resource utilization.

[0088] By implementing the weighted polling mechanism, the present invention effectively avoids the problem of the whole system being blocked due to the incomplete consumption of the weight counter of a queue, which causes the queue to send a request signal. This improvement significantly improves the utilization of the bus and greatly improves the overall service quality and performance.

[0089] The present invention relates to an advanced system design, which significantly improves the flexibility and efficiency of the system by integrating TAG FIFO, information vector table and state vector table. This design not only optimizes the processing capability of complex tasks, but also can effectively coordinate the working order between multiple state machine queues, and can maintain excellent performance even in the face of highly concurrent tasks. In addition, the system also supports dynamic adjustment of the working priority of each state machine, so that the system can more intelligently adapt to and respond to different application scenario requirements, further enhancing the adaptability and practicality of the system.

[0090] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A high-performance switch shared cache control system, characterized in that: include: Multiple port modules, multiple memory allocation modules, multiple memory recycling modules, dynamic channel allocation module and SRAM array; The dynamic channel allocation module is used for cross communication between the port module, the memory allocation module, the memory recovery module and the SRAM array; The port module is used for receiving and sending data packets, scheduling the work of other modules, and performing read and write operations on addresses in the SRAM array; The memory allocation module is used to allocate memory space addresses for data packets and use a vector mapping mechanism to record the idle state or occupied state of the SRAM address space; A memory recovery module is used to request the destination port to read out data packets and to recover the memory address space corresponding to the read data packets; Among them, the memory recovery module receives the descriptor of the data packet that has been written into the SRAM array from the port module, manages the descriptors through multiple FIFOs with different priorities, and works for the FIFOs through multiple state machine queues. After weighted polling arbitration between the FIFOs, it is determined that all state machine queues work for a certain FIFO after serving it. The state machine queue takes the descriptor, and the port module is scheduled to read the corresponding data packet through the descriptor. After completion, the descriptor is sent to the memory allocation module to schedule it to clear the occupancy mark of the address space of the data packet corresponding to the descriptor, so as to realize the request to read the data packet and memory recovery at the destination port.

2. The high-performance switch shared cache control system according to claim 1, characterized in that: The memory recycling module is provided with a weighted polling arbiter, a plurality of FIFOs of different priorities and a plurality of state machine queues; The FIFO is used to store descriptors of corresponding levels. When the FIFO is not empty, it actively sends a service request signal to the weighted polling arbitrator. After receiving at least one valid service request signal, the weighted polling arbitrator marks all FIFOs in the request state as pending, and starts a round-robin selection process based on the weight ratio, and only performs an authorization operation once for each FIFO marked as pending, and can only get one opportunity in the same round; the selected FIFO is jointly completed by all state machine queues to complete the required amount of data retrieval and task scheduling work, and the control right is released immediately after completion, and the pending mark of the FIFO is cleared. For the remaining FIFOs that have not been selected and still have pending marks, they will continue to participate in polling until all pending marks are cleared. After all pending marks are cleared, the weighted polling arbitrator starts a new round of weighted polling.

3. The high-performance switch shared cache control system according to claim 2, characterized in that: When a FIFO is exhausted, a signal to release control is immediately sent to the weighted polling arbitrator.

4. The high-performance switch shared cache control system according to claim 3, characterized in that: The register value is dynamically configured through the APB interface to adjust the bandwidth allocated to each FIFO by the weighted polling arbitrator, thereby adjusting the weight of each FIFO.

5. The high-performance switch shared cache control system according to claim 4, characterized in that: The memory recycling module also includes a data distributor, which is used to store the received data packets into the corresponding priority FIFO according to the priority information thereof.

6. The high-performance switch shared cache control system according to claim 5, characterized in that: The memory recycling module also includes a TAG FIFO for scheduling state machine queues. Each queue is assigned a TAG value. When the state machine queue is idle and has a data packet or descriptor processing requirement, it applies for the corresponding TAG through fair polling arbitration to obtain work authorization.

7. The high-performance switch shared cache control system according to any one of claims 1 to 6, characterized in that: The descriptor includes: source port, destination port, data packet length, priority, module id, multicast destination port and multicast enable.

8. The high-performance switch shared cache control system according to claim 1, characterized in that: Each port module is internally configured with multiple FIFOs for storing data packets, multiple state machine queues, TAG FIFO, fair polling arbiter, data distributor, information vector table and state vector table; The data distributor is used to distribute the received data packets to the FIFO; the FIFO is used to store the data packets; the state machine queue is used to fairly poll the arbitrator to apply to the TAG FIFO for obtaining the corresponding work authorization; the information vector table is used to store the frame header information of the data packet; the state vector table is used to identify the work process and guide the operation of the state machine by changing the register value in the state vector table after the port module successfully establishes communication with other modules and completes the handshake protocol.

9. The high-performance switch shared cache control system according to claim 8, characterized in that: The frame header information of the data packet includes a source port, a destination port, a data packet length, a priority, a multicast destination port and a multicast enable.

10. The high-performance switch shared cache control system according to claim 1, characterized in that: The dynamic channel allocation module is integrated with a load balancing module and a routing module; The dynamic channel allocation module first receives a request from the host and simultaneously obtains the real-time status information of all slaves; the port module acts as the host, and the memory allocation module and the memory recovery module act as slaves; Based on the real-time status information of the slaves, the dynamic channel allocation module arbitrates the requests of the host to determine which host to provide services for; after determining which host to provide services for, the load balancing module further arbitrates the slaves in the idle state and allocates the requests to the slaves that have obtained arbitration authorization; The slave index that obtains arbitration authorization is output to the routing module, and the routing module selects the corresponding line according to the slave index to complete the data transmission between the host and the slave.

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