Single-ended non-inductive noise reduction push-pull LNA circuit
By designing a single-ended inductor-free noise reduction push-pull LNA circuit, the combined structure of PMOS tube, NMOS tube and capacitor resistor is used to solve the problems of large area, high power consumption and high noise in traditional LNA circuits, and the effect of small, efficient and low noise amplification is achieved.
Patent Information
- Application Number
- CN202411856575.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-04-11
AI Technical Summary
Traditional LNA circuits have large area, high power consumption and high noise, making it difficult to meet the needs of modern communication equipment for small, efficient, and low noise amplification.
A single-ended inductor-free noise reduction push-pull LNA circuit is designed, using a combined structure of PMOS tube, NMOS tube, capacitor and resistor. Noise cancellation is achieved through push-pull amplification and Cascode structure, and noise current is shunted through feedback resistors.
It realizes the characteristics of the circuit with small area, low power consumption, low noise, high gain and strong driving capability, and is suitable for various communication circuits.
Smart Images
Figure CN119813970A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of wireless communication electronic circuits, and in particular to a single-ended inductorless noise reduction push-pull LNA circuit. Background Art
[0002] LNA circuits are used in the RF front end of receiver circuits, providing low-noise amplification of the desired signal frequency. They are widely used in fields such as communications and navigation. Conventional LNA circuits use a common-emitter output amplifier, a source-stage negative feedback inductor to reduce noise, and a feed inductor as a load for frequency selection and gain improvement. Conventional LNA circuits are large in size and require high power consumption to achieve low noise. Summary of the Invention
[0003] In view of the above problems in the prior art, the present invention proposes a single-ended inductorless noise reduction push-pull LNA circuit, which mainly solves the problems of large area, high power consumption and high noise of traditional LNA circuits.
[0004] In order to achieve the above-mentioned and other purposes, the technical solutions adopted by the present invention are as follows.
[0005] The present application provides a single-ended, inductorless, noise-reducing push-pull LNA circuit, comprising: a first PMOS transistor, having a gate connected to a first current copy port and a source connected to a power input unit; a first NMOS transistor, having a gate connected to a second current copy port and a source grounded, to form a push-pull amplification structure with the first PMOS transistor, wherein the drain of the first PMOS transistor and the drain of the first NMOS transistor are respectively connected to a main circuit and an auxiliary circuit, and the main circuit and the auxiliary circuit are connected via a first feedback resistor, so that the drain current is split into two paths and converted into a feedback voltage on the first feedback resistor; wherein the two ends of the first feedback resistor are respectively connected to a radio frequency signal input terminal and a radio frequency signal output terminal, and the feedback voltage is fed back to the gates of the first PMOS transistor and the first NMOS transistor to offset radio frequency noise.
[0006] In one embodiment of the present application, the power input unit includes: a zeroth PMOS tube and a first capacitor, the gate of the zeroth PMOS tube serves as the power switch control terminal, the source is connected to the power supply voltage, the drain is respectively connected to the source of the first PMOS tube and one end of the first capacitor, and the other end of the first capacitor is connected to the radio frequency ground.
[0007] In one embodiment of the present application, a second capacitor is provided between the first current copy port and the RF signal input terminal; and a third capacitor is provided between the second current copy port and the RF signal input terminal.
[0008] In one embodiment of the present application, a first isolation resistor is provided between the first current copy port and the gate of the first PMOS transistor.
[0009] In one embodiment of the present application, a second isolation resistor is provided between the second current copy port and the gate of the first NMOS transistor.
[0010] In an embodiment of the present application, a fourth capacitor and a second feedback resistor are sequentially connected in series between the RF signal input terminal and the first feedback resistor.
[0011] In one embodiment of the present application, the main circuit includes a second PMOS tube and a second NMOS tube; the source of the second PMOS tube is connected to the drain of the first PMOS tube, the drain is connected to the drain of the second NMOS tube, and the gate is connected to the first control end; the source of the second NMOS tube is connected to the drain of the first NMOS tube, and the gate is connected to the second control end.
[0012] In one embodiment of the present application, the auxiliary circuit includes a third PMOS tube and a third NMOS tube; the source of the third PMOS tube is connected to the drain of the first PMOS tube, the drain is connected to the drain of the third NMOS tube, and the gate is connected to the first control end; the source of the third NMOS tube is connected to the drain of the first NMOS tube, the gate is connected to the second control end and the gate of the second NMOS tube, and is connected to the radio frequency ground through a sixth capacitor, and the gate of the second PMOS tube is connected to the gate of the third PMOS tube, and is connected to the radio frequency ground through a fifth capacitor.
[0013] In one embodiment of the present application, the magnification ratio of the second PMOS transistor to the third PMOS transistor is 7:3; the magnification ratio of the second NMOS transistor to the third NMOS transistor is 7:3.
[0014] As described above, the single-ended inductorless noise reduction push-pull LNA circuit provided by the present application has the following beneficial effects.
[0015] The single-ended, inductorless, noise-reducing push-pull LNA circuit of the present application is composed of a PMOS transistor, an NMOS transistor, a capacitor, and a resistor. No feed inductor or feedback inductor is required, resulting in a very small overall circuit size. The circuit employs push-pull amplification to improve efficiency, reduce losses, and provide strong drive capability within a cycle. The drain noise current of the first PMOS transistor and the first NMOS transistor is separated between the main and auxiliary cascodes, converted into a voltage via a first feedback resistor, and then fed back to the first PMOS transistor and the first NMOS transistor, thereby partially canceling out the noise. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of the structure of a single-ended inductorless noise reduction push-pull LNA circuit in one embodiment of the present application.
[0017] Figure 2 In one embodiment of the present application, the frequency of 1.8G to 2.5G is S11 Change curve chart.
[0018] Figure 3 In one embodiment of the present application, the frequency of 1.8G to 2.5G is S 21 Gain variation curve graph.
[0019] Figure 4 In one embodiment of the present application, N F Noise figure change curve.
[0020] Figure 5 In one embodiment of the present application, K f Stability coefficient change curve.
[0021] Description of Figure Numbers:
[0022] PMOS0 - zeroth PMOS transistor; P1 - first PMOS transistor; P2 - second PMOS transistor; P3 - third PMOS transistor; N1 - first NMOS transistor; N2 - second NMOS transistor; N3 - third NMOS transistor; C1 - first capacitor, C2 - second capacitor; C3 - third capacitor; C4 - fourth capacitor; C5 - fifth capacitor; C6 - sixth capacitor; PD - power switch control terminal; V BP -First current copy port; V BN -Second current copy port; RFIN-RF signal input terminal; RFOUT-RF signal output terminal; V BP1 -First control terminal; V BN1 -Second control terminal; R B -First feedback resistor; R BP -First isolation resistor; R BN - Second isolation resistor; R F - Second feedback resistor. DETAILED DESCRIPTION
[0023] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.
[0024] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.
[0025] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a single-ended inductorless noise reduction push-pull LNA circuit in one embodiment of the present application. The LNA circuit in this embodiment of the present application includes: a first PMOS transistor P1, whose gate is connected to a first current copy port VBP and whose source is connected to a power input unit; a first NMOS transistor N1, whose gate is connected to a second current copy port VBN and whose source is grounded, so as to form a push-pull amplification structure with the first PMOS transistor P1. The drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are respectively connected to the main circuit and the auxiliary circuit, and are connected through a first feedback resistor R B Connect the main circuit and the auxiliary circuit so that the drain current is split into two paths and converted into the first feedback resistor R B The feedback voltage on the first feedback resistor R B The two ends are connected to the radio frequency signal input terminal RFIN and the radio frequency signal output terminal RFOUT respectively, and the feedback voltage is fed back to the gate of the first PMOS transistor P1 and the first NMOS transistor N1 to offset the radio frequency noise.
[0026] In one embodiment, the power input unit includes: a zeroth PMOS transistor PMOS0 and a first capacitor. The gate of the zeroth PMOS transistor PMOS0 serves as a power switch control terminal PD, the source is connected to the power supply voltage, and the drain is respectively connected to the source of the first PMOS transistor P1 and one end of the first capacitor C1. The other end of the first capacitor C1 is connected to the radio frequency ground.
[0027] In one embodiment, the first current copy port V BP A second capacitor C2 is provided between the RF signal input terminal RFIN and the second current copy port V BN A third capacitor C3 is provided between the radio frequency signal input terminal RFIN.
[0028] In one embodiment, the first current copy port V BP A first isolation resistor R is provided between the gate of the first PMOS transistor P1 and the first PMOS transistor P2. BP , used to isolate the ripple of the current copy.
[0029] In one embodiment, the second current copy port V BN A second isolation resistor R is provided between the gate of the first NMOS transistor N1 and the gate of the first NMOS transistor N2.BN , used to isolate the ripple of the current copy.
[0030] In one embodiment, the radio frequency signal input terminal RFIN and the first feedback resistor R B The fourth capacitor C4 and the second feedback resistor R are connected in series. F .
[0031] In one embodiment, the main circuit includes a second PMOS transistor P2 and a second NMOS transistor N2; the source of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1, the drain is connected to the drain of the second NMOS transistor N2, and the gate is connected to the first control terminal V BP1 The source of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1, and the gate is connected to the second control terminal V BN1 .
[0032] In one embodiment, the auxiliary circuit includes a third PMOS transistor P3 and a third NMOS transistor N3; the source of the third PMOS transistor P3 is connected to the drain of the first PMOS transistor P1, the drain is connected to the drain of the third NMOS transistor N3, and the gate is connected to the first control terminal V BP1 The source of the third NMOS tube N3 is connected to the drain of the first NMOS tube N1, and the gate is connected to the second control terminal V BN1 The gate of the second NMOS transistor N2 is connected to the radio frequency ground through the sixth capacitor C6, and the gate of the second PMOS transistor P2 is connected to the gate of the third PMOS transistor P3 and is connected to the radio frequency ground through the fifth capacitor C5. BP1 As the current copy port of the second PMOS transistor P2 and the third PMOS transistor P3, the second control terminal V BN1 Serves as a current copy port for the second NMOS transistor N2 and the third NMOS transistor N3.
[0033] Based on the LNA circuit of the embodiment of the present application, the first PMOS transistor P1 and the first NMOS transistor N1 form a push-pull amplifier. The first PMOS transistor P1 and the first NMOS transistor N1 respectively adopt a cascode structure to increase the output impedance and improve the gain. The cascode stage is divided into a main path and an auxiliary path. The amplification ratio of P2 to P3, and N2 to N3 is 7:3. The drain noise current of the first PMOS transistor P1 and the first NMOS transistor N1 is separated between the main path and the auxiliary path cascodes, and is passed through the first feedback resistor R B Converted into voltage, and then fed back to the first PMOS transistor P1 and the first NMOS transistor N1, to achieve the effect of partially canceling the noise; compared with the feedback resistor of the traditional structure, the second feedback resistor R F It can have a higher resistance value to offset noise and increase gain and the stability coefficient Kf The LNA circuit of this application utilizes drain noise current shunt feedback, K f Small changes in the feedback resistor R F It can be multiplied to obtain better noise cancellation effect. The circuit has the characteristics of low noise, small area, low power consumption, high gain and strong driving capability, and can be applied to various communication circuits.
[0034] See also Figure 2 , Figure 2 In one embodiment of the present application, the frequency of 1.8G to 2.5G is S 11 Change curve chart. Figure 2 It can be seen that the return loss of the single-ended inductorless noise reduction push-pull LNA circuit of the embodiment of the present application is less than -10dB in the required frequency band between 2.17GHz and 2.2GHz.
[0035] See also Figure 3 , Figure 3 In one embodiment of the present application, the frequency of 1.8G to 2.5G is S 21 Gain change curve. Figure 3 It can be seen that the gain of the single-ended inductorless noise reduction push-pull LNA circuit of the embodiment of the present application is about 18 dB in the required frequency band between 2.17 GHz and 2.2 GHz.
[0036] See also Figure 4 , Figure 4 In one embodiment of the present application, N F Noise figure change curve. Figure 4 It can be seen that the noise of the single-ended inductorless noise reduction push-pull LNA circuit in the embodiment of the present application is about 0.85dB in the required frequency band between 2.17GHz and 2.2GHz.
[0037] See also Figure 5 , Figure 5 In one embodiment of the present application, K f Stability coefficient change curve. Figure 5 It can be seen that the inductorless noise reduction push-pull LNA circuit of the embodiment of the present application has a K f Around 1.1.
[0038] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A single-ended inductorless noise reduction push-pull LNA circuit, characterized in that: include: A first PMOS tube, a gate of which is connected to the first current copy port, and a source of which is connected to the power input unit; A first NMOS tube, whose gate is connected to the second current copy port and whose source is grounded, so as to form a push-pull amplification structure with the first PMOS tube, wherein a main path and an auxiliary path are respectively connected between the drain of the first PMOS tube and the drain of the first NMOS tube, and the main path and the auxiliary path are connected through a first feedback resistor, so that the drain current is divided into two paths and converted into a feedback voltage on the first feedback resistor; wherein the two ends of the first feedback resistor are respectively connected to the RF signal input end and the RF signal output end, and the feedback voltage is fed back to the gates of the first PMOS tube and the first NMOS tube to offset the RF noise.
2. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 1, characterized in that: The power input unit includes: a zeroth PMOS tube and a first capacitor, the gate of the zeroth PMOS tube serves as a power switch control terminal, the source is connected to the power supply voltage, the drain is respectively connected to the source of the first PMOS tube and one end of the first capacitor, and the other end of the first capacitor is connected to the radio frequency ground.
3. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 1, characterized in that: A second capacitor is arranged between the first current copy port and the RF signal input end; and a third capacitor is arranged between the second current copy port and the RF signal input end.
4. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 1, characterized in that: A first isolation resistor is provided between the first current copy port and the gate of the first PMOS tube.
5. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 4, characterized in that: A second isolation resistor is provided between the second current copy port and the gate of the first NMOS tube.
6. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 1, characterized in that: A fourth capacitor and a second feedback resistor are sequentially connected in series between the RF signal input terminal and the first feedback resistor.
7. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 1, characterized in that: The main circuit includes a second PMOS tube and a second NMOS tube; the source of the second PMOS tube is connected to the drain of the first PMOS tube, the drain is connected to the drain of the second NMOS tube, and the gate is connected to the first control end; the source of the second NMOS tube is connected to the drain of the first NMOS tube, and the gate is connected to the second control end.
8. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 7, characterized in that: The auxiliary circuit includes a third PMOS tube and a third NMOS tube; the source of the third PMOS tube is connected to the drain of the first PMOS tube, the drain is connected to the drain of the third NMOS tube, and the gate is connected to the first control end; the source of the third NMOS tube is connected to the drain of the first NMOS tube, the gate is connected to the second control end and the gate of the second NMOS tube, and is connected to the radio frequency ground through a sixth capacitor, and the gate of the second PMOS tube is connected to the gate of the third PMOS tube, and is connected to the radio frequency ground through a fifth capacitor.
9. The single-ended inductorless noise reduction push-pull LNA circuit according to claim 8, characterized in that: The enlargement ratio of the second PMOS tube to the third PMOS tube is 7:3; the enlargement ratio of the second NMOS tube to the third NMOS tube is 7:3.