High-speed serial computer expansion bus standard terminal equipment and its clock distribution circuit

By using a multi-channel clock selector and level conversion circuit, the latency and quality issues caused by clock conversion and distribution in single-port mode of PCIe terminal equipment are resolved, and synchronous output of the reference clock and accurate control of the device's operating mode are achieved.

CN119884002BActive Publication Date: 2025-12-02SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Patent Information

Application Number
CN202510115398.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-01-23
Publication Date
2025-12-02
Estimated Expiration
2045-01-23

AI Technical Summary

Technical Problem

In the single-port mode of PCIe terminal devices, the PCIe controller's conversion and distribution of the reference clock can lead to latency and quality degradation, affecting the collaborative operation of the two physical media sublayers.

Method used

A multi-channel clock selector and level conversion circuit are used. The host's dual-port enable signal controls the clock selector to output two reference clocks synchronously in dual-port mode and a single reference clock synchronously in single-port mode, ensuring that the clock quality is not affected.

Benefits of technology

It enables synchronous output of two reference clocks in single-port mode, improving operational reliability without affecting reference clock quality. At the same time, the host can accurately control the operating mode of PCIe terminal devices.

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Abstract

This invention discloses a high-speed serial computer extended bus standard terminal device and its clock distribution circuit, belonging to the field of integrated circuit design. When the level conversion circuit receives a "dual-port enable signal from the host", it can control the multiplexer to work in dual-port mode, thereby leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multiplexer to work in single-port mode, so that the reference clock provided by the host through the first output terminal can be synchronously output through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical medium sublayers. Moreover, the forwarding processing performed by the multiplexer does not affect the reference clock quality. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.
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