Preparation method of vacuum device, vacuum device and electronic equipment

Abstract

According to the preparation method of the vacuum device, the vacuum device and the electronic equipment provided by the invention, the carrier plate groove is formed in the outer side of the bonding groove, and the carrier plate electrode is arranged outside the cavity structure, so that the influence of the carrier plate electrode on the vacuum effect of the cavity structure is avoided, and the vacuum effect of the cavity structure is improved. Moreover, the arrangement of the bonding groove not only can avoid the influence on the vacuum effect of the cavity structure due to the overflow of the solder bump to the periphery during the subsequent substrate bonding, but also can avoid the influence on the bonding effect of the substrate due to the projection of the solder bump, thereby further improving the vacuum effect of the cavity structure, and improving the bonding effect of the substrate. Besides, a carrier exposed groove is formed in the second substrate in advance, and a vacuum device formed after bonding can be directly ground to expose a carrier electrode and an alignment mark, so that the possibility of damage to the cavity structure is avoided, and the vacuum effect of the cavity structure is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for preparing a vacuum device, a vacuum device and an electronic device. Background Art

[0002] With the development of science and technology, vacuum devices have become one of the mainstream products of micro-electromechanical systems (MEMS). For example, the inertial measurement unit (IMU) is a typical vacuum device. As a device for measuring and characterizing angular velocity and acceleration in three-dimensional space, IMU integrates two types of devices, gyroscopes and accelerometers, based on the principle of inertia. Among them, the gyroscope is used to measure the angular velocity of an object, that is, the speed at which the object rotates around each coordinate axis. The accelerometer is used to measure the acceleration of an object on each coordinate axis.

[0003] The structure of the vacuum device includes a device cavity, and the vacuum degree of the device cavity will affect the functionality of the vacuum device. Improving the vacuum degree of the cavity usually helps to reduce the friction and damping effect of air on sensor parts, thereby improving the accuracy and stability of the sensor. However, the vacuum degree of the cavity of the vacuum device prepared by the prior art usually cannot meet the performance requirements of the actual device.

[0004] Therefore, providing a method for preparing a vacuum device that can improve the vacuum degree of the device cavity has become a technical problem that the industry urgently needs to solve. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a method for preparing a vacuum device, a vacuum device and an electronic device, so as to improve the vacuum degree of the cavity of the vacuum device.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for preparing a vacuum device, comprising:

[0007] Providing a first substrate, and forming a device layer on a first surface of the first substrate;

[0008] Forming a bonding groove and a pad electrode in a chip region of the device layer, wherein the pad electrode is located outside the bonding groove, and forming an alignment mark in a non-chip region of the device layer;

[0009] Forming a plurality of cavity structures in the device layer corresponding to the area enclosed by the bonding groove, and forming a dicing groove at the junction of the chip area and the non-chip area;

[0010] Providing a second substrate, and forming a cavity groove, a carrier exposed groove and an alignment groove on the first surface of the second substrate respectively; wherein the carrier exposed groove corresponds to the carrier electrode, the cavity groove corresponds to the cavity structure, and the alignment groove corresponds to the alignment mark;

[0011] forming a getter structure in the cavity groove, and forming solder bumps on the first surface of the second substrate on both sides of the cavity groove, wherein the solder bumps and the bonding grooves can be engaged with each other;

[0012] Using the graphic fitting between the alignment mark and the alignment groove as an alignment reference, the bonding groove is engaged with the solder bump to bond the first surface of the second substrate with the first surface of the first substrate, wherein the cavity groove corresponds to the cavity structure to form a closed cavity;

[0013] The second surface of the second substrate is ground to expose the carrier electrode and the alignment mark.

[0014] Optionally, the first substrate includes a plurality of first exposure units, each non-chip area within the first exposure units is provided with at least one alignment mark, and the alignment mark is a cross-shaped scale line structure; the second substrate includes a plurality of second exposure units, each non-chip area within the second exposure units is provided with at least one alignment groove, and the alignment groove is a cross-shaped groove; the size of the alignment groove is equal to the size of the alignment mark.

[0015] Optionally, the method further includes:

[0016] Measuring the offset of the scale lines of the alignment marks in different exposure units on the bonded wafer formed by the first substrate and the second substrate relative to the alignment groove, wherein the offset is the bonding deviation of the bonded wafer;

[0017] If the offset of the exposure unit exceeds a first threshold, it is determined that the vacuum device on the exposure unit fails.

[0018] Optionally, forming a device layer on the first surface of the first substrate specifically includes:

[0019] Depositing an oxide layer and a silicon nitride layer in sequence on the first surface of the first substrate;

[0020] forming a first polysilicon structure in the silicon nitride layer as a lower electrode of the vacuum device;

[0021] forming a multi-layer oxide isolation structure on the silicon nitride layer on both sides of each of the first polysilicon structures;

[0022] forming a patterned sacrificial layer on the first polysilicon structure and the multi-layer oxide isolation structure;

[0023] forming a structural layer on the first substrate, wherein the structural layer covers the patterned sacrificial layer;

[0024] The surface of the structural layer is doped to form an upper electrode of the device.

[0025] Optionally, a plurality of cavity structures are formed in the device layer corresponding to the area enclosed by the bonding groove, and a scribe line groove is formed at the junction of the chip area and the non-chip area, specifically including:

[0026] Forming a patterned first mask layer on the structural layer, wherein the patterned first mask layer includes a plurality of sacrificial hole window patterns, a scribe line groove window pattern and a barrier layer;

[0027] Using the patterned first mask layer as a mask, the structural layer and the sacrificial layer in the plurality of sacrificial hole window patterns and the scribe line groove window patterns are etched to form the plurality of cavity structures and the scribe line grooves.

[0028] Optionally, a bonding groove and a pad electrode are formed in a chip region of the device layer, the pad electrode is located outside the bonding groove, and an alignment mark is formed in a non-chip region of the device layer, specifically including:

[0029] forming a patterned second mask layer on the surface of the device layer;

[0030] Forming a bonding groove and a pad carrier groove with the same depth in the first chip region of the device layer, wherein the pad carrier groove is located outside the bonding groove;

[0031] Re-patterning the patterned second mask layer, wherein the re-patterned second mask layer includes a carrier groove pattern and an alignment mark pattern;

[0032] Depositing a metal layer, wherein the metal layer covers the second patterned mask layer, the carrier groove, and the alignment mark pattern;

[0033] The re-patterned second mask layer and the metal layer formed thereon are removed, a carrier electrode is formed in the carrier groove, and an alignment mark is formed in a non-chip area of ​​the device layer.

[0034] Optionally, forming a cavity structure groove, a carrier exposed groove and an alignment groove on the first surface of the second substrate respectively includes:

[0035] forming a patterned third mask layer on the first surface of the second substrate, wherein the patterned third mask layer comprises a cavity structure groove window pattern, a carrier exposed groove window pattern, an alignment groove window pattern and a barrier layer;

[0036] Using the patterned third mask layer as a mask, etching the second substrate corresponding to the cavity structure groove window pattern, the carrier exposed groove window pattern and the alignment groove window pattern, respectively, to form the cavity structure groove, the carrier exposed groove and the alignment groove;

[0037] Wherein, the depth of the cavity structure groove is respectively greater than the depth of the carrier exposed groove and the depth of the alignment groove.

[0038] Optionally, forming a getter structure in the cavity structure groove, and forming solder bumps on both sides of the cavity structure groove, specifically includes:

[0039] forming a patterned fourth mask layer on the first surface of the second substrate, wherein the patterned fourth mask layer comprises a getter structure window pattern and a barrier layer, wherein the getter structure window pattern is located in the cavity structure groove;

[0040] Using the patterned fourth mask layer as a mask, depositing a getter material in the getter structure window pattern to form the getter structure;

[0041] forming a patterned fifth mask layer on the getter material, the patterned fifth mask layer comprising a solder bump window pattern and a barrier layer, the solder bump window pattern being located on both sides of the cavity structure groove;

[0042] Depositing solder, wherein the solder is formed in the solder bump window pattern and covers the patterned fifth mask layer;

[0043] The fifth mask layer and excess solder formed thereon, and the fourth mask layer and excess getter material formed thereon are removed.

[0044] Optionally, the second substrate is a high-resistance substrate.

[0045] The embodiment of the present invention further provides a vacuum device, which is prepared by the vacuum device preparation method, and the structure includes:

[0046] a first substrate, wherein a device layer is formed on a first surface of the first substrate;

[0047] A bonding groove and a pad electrode, wherein the bonding groove and the pad electrode are both formed in the chip region of the device layer, and the pad electrode is formed outside the bonding groove;

[0048] A plurality of cavity structures, wherein the plurality of cavity structures are formed in the device layers corresponding to the area enclosed by the bonding groove;

[0049] A second substrate, wherein a first surface of the second substrate is respectively formed with a cavity groove; a getter structure is formed in the cavity groove, and solder bumps are formed on the first surface of the second substrate on both sides of the cavity groove;

[0050] The first substrate and the second substrate are embedded in the bonding groove through the solder bump, the cavity groove and the cavity structure form a closed cavity corresponding to each other, and the carrier electrode and the alignment mark are exposed on the second surface of the second substrate.

[0051] An embodiment of the present invention further provides an electronic device, comprising the vacuum device.

[0052] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0053] In the method for preparing the vacuum device of the technical solution of the present invention, by arranging the carrier electrode outside the bonding groove, the carrier electrode is arranged outside the cavity structure, and the carrier exposed groove is formed on the second substrate at the same time, the vacuum device formed after bonding can be directly ground to expose the carrier electrode and the alignment mark, avoiding the possibility of damaging the cavity structure, thereby improving the vacuum effect of the cavity structure. On the other hand, the bonding groove is arranged on the first substrate, and is embedded with the solder bump of the second substrate in the subsequent bonding process, avoiding the solder bump from overflowing to the surroundings, improving the bonding effect, and further improving the vacuum effect of the cavity structure.

[0054] Furthermore, the alignment mark and the alignment groove can be provided not only as an alignment reference during substrate bonding, but also for measuring substrate offset after bonding, thereby improving the utilization rate of the effective area of ​​a single wafer and reducing the process cost of device manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 The process of the method for preparing the vacuum device provided by the embodiment of the present invention Figure 1 ;

[0056] Figure 2 The process of the method for preparing the vacuum device provided by the embodiment of the present invention Figure 2 ;

[0057] Figures 3 to 10 The following are simplified cross-sectional diagrams of the method for preparing a vacuum device according to the embodiment of the present invention under different process flows. Figure 1 ;

[0058] Figures 11 to 18 The following are simplified cross-sectional diagrams of the method for preparing a vacuum device according to the embodiment of the present invention under different process flows. Figure 2 ;

[0059] Fig.19 A top view of a first substrate provided in an embodiment of the present invention;

[0060] Fig. 20 A top view of a second substrate provided in an embodiment of the present invention;

[0061] Fig.21 A top view of an alignment mark combined with an alignment groove provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] As described in the background technology, in the prior art, a first substrate having a device layer formed thereon and a second substrate having a cavity structure formed thereon are bonded to form a vacuum device, and the bonding deviation in the vacuum device is measured by an infrared measurement method. According to the bonding deviation, the second substrate is etched to expose the carrier electrode in the first substrate. When a high-resistance substrate is used as the second substrate, the infrared measurement method used in the prior art cannot directly test the bonding deviation, which brings great process challenges to the subsequent lithography and etching processes, and may damage the vacuum structure of the device, thereby affecting the device performance.

[0064] Based on this, the inventor of the present application provides a new method for preparing a vacuum device, comprising the following steps:

[0065] Providing a first substrate, and forming a device layer on a first surface of the first substrate;

[0066] Forming a bonding groove and a pad electrode in a chip region of the device layer, wherein the pad electrode is located outside the bonding groove, and forming an alignment mark in a non-chip region of the device layer;

[0067] Forming a plurality of cavity structures in the device layer corresponding to the area enclosed by the bonding groove, and forming a dicing groove at the junction of the chip area and the non-chip area;

[0068] Providing a second substrate, and forming a cavity groove, a carrier exposed groove and an alignment groove on the first surface of the second substrate respectively; wherein the carrier exposed groove corresponds to the carrier electrode, the cavity groove corresponds to the cavity structure, and the alignment groove corresponds to the alignment mark;

[0069] forming a getter structure in the cavity groove, and forming solder bumps on the first surface of the second substrate on both sides of the cavity groove, wherein the solder bumps and the bonding grooves can be engaged with each other;

[0070] Using the graphic fitting between the alignment mark and the alignment groove as an alignment reference, the bonding groove is engaged with the solder bump to bond the first surface of the second substrate with the first surface of the first substrate, wherein the cavity groove corresponds to the cavity structure to form a closed cavity;

[0071] The second surface of the second substrate is ground to expose the carrier electrode and the alignment mark.

[0072] Through the above technical means, the embodiment of the present invention can not only greatly improve the vacuum effect of the manufactured vacuum device, but also improve the substrate bonding effect. The specific reasons are as follows:

[0073] On the first aspect, since the carrier groove is arranged on the outside of the bonding groove, the carrier electrode is arranged outside the cavity structure, and the carrier exposed groove is formed on the first surface of the second substrate. Moreover, since the carrier exposed groove and the alignment groove are both deeper than the cavity structure groove, after forming the vacuum device, it is only necessary to grind the second surface of the second substrate in the vacuum device to expose the carrier electrode and the alignment mark without damaging the cavity structure. This avoids the problem in the prior art that after bonding, the second substrate is etched based on the bonding error to expose the carrier electrode, which affects the vacuum effect of the cavity structure, thereby improving the vacuum effect of the cavity structure.

[0074] On the second aspect, the graphic fitting between the alignment mark and the alignment groove is used as an alignment reference, the bonding groove is fit into the solder bump, and the bonding alignment of the first substrate and the second substrate is achieved by respectively fitting the graphics of the alignment mark and the alignment groove in the bonding device, thereby improving the bonding accuracy; at the same time, the setting of the bonding groove can prevent the solder bump from overflowing to the surroundings during the subsequent bonding of the first substrate and the second substrate and affecting the vacuum effect of the cavity structure, thereby further improving the vacuum effect of the cavity structure.

[0075] In addition, because the bonding groove and the solder bump are embedded, the protrusion of the solder bump can avoid affecting the bonding effect of the substrate, thereby improving the bonding effect of the substrate.

[0076] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0077] in, Figure 1 The process of the method for preparing the vacuum device provided by the embodiment of the present invention Figure 1 .

[0078] The first part is prepared, and the specific steps include the following:

[0079] S11: providing a first substrate, and forming a device layer on a first surface of the first substrate.

[0080] Among them, taking the vacuum device as an inertial measurement unit as an example, since the vacuum device prepared in the embodiment of the present invention is an inertial measurement unit, the material of the first substrate is a low-resistivity silicon wafer doped with boron. The thickness of the first substrate is specifically 775μm, and its crystal orientation is specifically <100>. Of course, the thickness and crystal orientation of the first substrate can be adjusted according to different types of vacuum devices, and are not limited here.

[0081] For the specific process of step S11, please refer to Figure 2-Figure 10 ; Figure 2 The process of the method for preparing a vacuum device provided by an embodiment of the present invention is Figure 2 , Figures 3 to 10 The following are simplified cross-sectional diagrams of the method for preparing a vacuum device according to the embodiment of the present invention under different process flows. Figure 1 .

[0082] Combination Figures 2 to 10 The device layer is formed in step S11, which may include the following steps S110-S115:

[0083] S110: depositing an oxide layer 101 and a silicon nitride layer 102 in sequence on the first surface of the first substrate 100. Figure 3 shown.

[0084] The oxide layer 101 is used to isolate the first substrate 100 , and the silicon nitride layer 102 is used to match the oxide layer 101 to prevent the oxide layer 101 from absorbing water vapor.

[0085] S111: forming a first polysilicon structure in the silicon nitride layer 102 as a lower electrode of the vacuum device.

[0086] Specifically, step S111 includes steps S1111-S1113:

[0087] S1111: forming a plurality of first grooves in the silicon nitride layer 102, wherein the first grooves penetrate the silicon nitride layer 102 and expose the surface of the oxide layer 101, such as Figure 4 shown.

[0088] S1112: forming a first polysilicon structure in each of the first grooves, such as Figure 6 shown.

[0089] Specifically, the method includes: depositing a first polysilicon layer on the surface of the first substrate, forming a patterned mask layer on the surface of the first polysilicon layer, the mask layer including a first polysilicon structure blocking pattern. Then, using the patterned mask layer as a mask, etching the first polysilicon layer 103 except for the first polysilicon structure blocking pattern, so as to form a first polysilicon structure in each of the first grooves. Finally, removing the mask layer, the height of the first polysilicon structure is higher than the silicon nitride layer. Preferably, the height of the first polysilicon structure is 0.8μ, such as Figure 6 shown.

[0090] S1113: doping all first polysilicon structures to form a lower electrode of the device.

[0091] Specifically, P-type ions are implanted into the first polysilicon structure, and the implanted P-type ions include but are not limited to boron, aluminum, indium, etc. The doping process for the first polysilicon structure is a common technical means in the art and will not be described in detail here.

[0092] S112: forming a multi-layer oxide isolation structure 104 on both sides of each of the first polysilicon structures, such as Figure 7 shown.

[0093] The multi-layer oxide isolation structure 104 is specifically used to isolate the first polysilicon structure to optimize the performance of the vacuum device.

[0094] S113: forming a patterned sacrificial layer 105 on the first polysilicon structure and the multi-layer oxide isolation structure, such as Fig. 9 shown.

[0095] Specifically, a sacrificial layer material layer is deposited on the first polysilicon structure and the multi-layer oxide isolation structure, such as Figure 8 As shown, the sacrificial layer material layer is an insulating material, preferably silicon dioxide; the sacrificial layer material layer is etched to form a patterned sacrificial layer 105. The pattern of the sacrificial layer material in the patterned sacrificial layer 105 can ensure electrical connectivity between the structural layer and the substrate after the structural layer is subsequently formed, and the pattern of the sacrificial layer material in the patterned sacrificial layer is used to assist in the subsequent formation of the cavity structure in the structural layer to form a structural layer partially suspended relative to the substrate.

[0096] S114: forming a structural layer on the first substrate, wherein the structural layer covers the patterned sacrificial layer; Fig.10 Preferably, the structural layer material is polysilicon.

[0097] S115: doping the surface of the structure layer 106 to form an upper electrode of the device.

[0098] The specific steps of doping the structural layer 106 in step S115 are similar to the specific steps of doping the first polysilicon structure in step S1103, and are not described here in detail. The doped structural layer region corresponds to the region of the carrier groove 108 prepared later.

[0099] After completing the preparation of the device layer in S11, please continue to refer to Figures 11 to 18 ,in, Figures 11 to 18 The following are simplified cross-sectional diagrams of the method for preparing a vacuum device according to the embodiment of the present invention under different process flows. Figure 2 The subsequent steps after completing the device layer preparation include:

[0100] S12: forming a bonding groove and a pad electrode in a chip region of the device layer, wherein the pad electrode is located outside the bonding groove, and forming an alignment mark in a non-chip region of the device layer.

[0101] Step S12 specifically includes the following steps:

[0102] Step S120: applying photoresist on the surface of the structural layer 106, and sequentially exposing, developing and ultraviolet treating the photoresist to form a patterned mask layer on the device layer.

[0103] Wherein, the patterned mask layer includes a bonding groove window pattern, a carrier groove window pattern, and a blocking area.

[0104] Step S121: using the patterned mask layer as a mask, dry-etching the structure layer 106 to form the bonding groove 107 and the carrier groove 108 of the same depth. Fig.11 shown.

[0105] The carrier groove 108 is located outside the bonding groove 107 to ensure that the prepared carrier electrode 109 is located outside the cavity structure 111, thereby preventing the carrier electrode 109 from affecting the vacuum effect of the cavity structure 111.

[0106] Step S122: re-patterning the patterned second mask layer, wherein the re-patterned second mask layer includes a carrier groove pattern and an alignment mark pattern;

[0107] Step S123: depositing a metal layer, the metal layer covers the patterned second mask layer, the carrier groove, and the alignment mark pattern; wherein the material of the metal layer includes AlCu alloy. Of course, the material of the metal layer can also be replaced by other metal materials or alloys with conductive ability, which is not limited here.

[0108] Step S124: removing the patterned second mask layer and the metal layer formed thereon, forming a carrier electrode 109 in the carrier groove 108, and forming an alignment mark 110 in the non-chip area of ​​the device layer, such as Fig.12 shown.

[0109] In the specific production process of forming a chip from a substrate, since the current common wafer exposure method is: set a semiconductor structure layer of a specific pattern in the mask, and then use the mask as an exposure unit to repeatedly expose the wafer until the entire wafer is exposed; therefore, there will be several exposure units on a single wafer, and one exposure unit includes several chips. In this embodiment, the first substrate 100 includes several first exposure units A1, and at least one alignment mark 110 is set in each first exposure unit A1. The alignment mark 110 can be set in the non-chip area a2 at the edge of the first exposure unit A1, such as Fig.19 The number and position of the alignment marks 110 in each first exposure unit A1 can be set according to the precision requirements of the vacuum device for substrate bonding deviation, which is not limited here.

[0110] Step S125: removing the re-patterned second mask layer and the metal layer formed thereon.

[0111] S13: forming a plurality of cavity structures 111 in the device layer corresponding to the area enclosed by the bonding groove 107, and forming a dicing groove 112 in the device layer between the chip area a1 and the non-chip area; Fig.13 shown.

[0112] Wherein, step S13 specifically includes the following steps:

[0113] S130: applying photoresist again on the surface of the structural layer 106, and sequentially exposing, developing and ultraviolet treating the photoresist to form a patterned first mask layer on the device layer.

[0114] Wherein, the first mask layer includes a plurality of sacrificial hole window patterns, a scribe line groove window pattern and a blocking layer.

[0115] S131 : using the patterned first mask layer as a mask, dry-etching the structural layer 106 in the plurality of sacrificial hole patterns and in the scribe line groove window pattern to form a plurality of sacrificial holes and the scribe line groove 112 .

[0116] S132: wet-etching the structural layer 106 and the sacrificial layer in the device layer through the plurality of sacrificial holes to form a plurality of the cavity structures 111, thereby forming a structural layer 106 suspended relative to the substrate to serve as an induction motion layer of a vacuum device.

[0117] The specific components of the wet etching solution can be set according to conventional technical means in the art and are not limited here.

[0118] S133: removing the fifth mask layer.

[0119] The second part is prepared, and the specific steps include the following:

[0120] S21: providing a second substrate 200, and forming a cavity structure groove 202, a carrier exposed groove 201 and an alignment groove 203 on the first surface of the second substrate 200; Fig.14 and Fig.15 shown.

[0121] Wherein, in step S14, a second substrate 200 is provided, and a cavity structure groove 202, a carrier exposed groove 201 and an alignment groove 203 are respectively formed on the first surface of the second substrate 200, which specifically includes the following steps:

[0122] S210: Provide a second substrate 200, such as Fig.14 shown.

[0123] Among them, since the vacuum device prepared in the embodiment of the present invention is specifically an inertial measurement unit, the material of the second substrate 200 is a high-resistivity silicon wafer doped with boron. The thickness of the first substrate 100 is specifically 775μm, and its crystal orientation is specifically <100>. Of course, the thickness and crystal orientation of the second substrate 200 can also be adjusted according to different types of vacuum devices, which are not limited here.

[0124] S211 : applying photoresist on the surface of the second substrate 200 , and sequentially exposing, developing and ultraviolet treating the photoresist to form a patterned third mask layer on the surface of the second substrate 200 .

[0125] The third mask layer includes a cavity structure groove window pattern, a carrier exposed groove window pattern, an alignment groove window pattern and a barrier layer. The width of the cavity structure groove window pattern is greater than the width of the carrier exposed groove window pattern and the width of the alignment groove window pattern.

[0126] S212: Using the patterned third mask layer as a mask, dry etching is performed on the second substrate 200 within the cavity structure groove window pattern, the carrier exposed groove window pattern and the alignment groove window pattern to form the cavity structure groove 202, the carrier exposed groove 201 and the alignment groove 203.

[0127] The carrier exposed groove 201 corresponds to the carrier electrode, the cavity structure groove 202 corresponds to the cavity structure, and the alignment groove 203 corresponds to the alignment mark.

[0128] In one embodiment, the alignment groove 203 corresponds to the alignment mark 110, the second substrate 200 includes a plurality of second exposure units B2, and the alignment groove 203 can be disposed in a non-chip region a2 at an edge of the second exposure unit B2, such as Fig. 20 The number and position of the alignment grooves 203 in each second exposure unit B2 correspond to the number and position of the alignment marks 110 in the first substrate 100 .

[0129] Among them, because the width of the cavity structure groove window pattern is relatively large, the depletion and distribution of the etching gas on the second substrate 200 in the cavity structure groove window pattern will be uneven, resulting in a slower etching rate. The window patterns of the carrier exposed groove 201 and the alignment groove 203 are relatively small, so the etching gas can effectively cover the second substrate 200 in the window patterns of the carrier exposed groove 201 and the alignment groove 203, thereby increasing the etching rate. Therefore, within the same etching time, the cavity structure groove 202 formed by etching is shallower than the carrier exposed groove 201 and the alignment groove 203.

[0130] Specifically, the etching gas for dry etching in step S212 specifically includes: a mixed gas of carbon tetrafluoride and oxygen. In step S212, the specific ratio of the groove depths of the cavity structure groove 202, the carrier exposed groove 201, and the alignment groove 203 can be controlled by reducing the etching environment pressure and adjusting the flow rate of the mixed gas. Among them, controlling the ratio of different groove depths by adjusting the flow rate of the mixed gas is a conventional technical means in the art and will not be repeated here.

[0131] S213: removing the third mask layer, such as Fig.15 shown.

[0132] It should be noted that, in addition to preparing the cavity structure groove 202, the carrier exposed groove 201 and the alignment groove 203 through step S211 and step S212, multiple photoresist coating, exposure and development can be performed on the second substrate 200 to form a patterned mask layer, each of which corresponds to the cavity structure groove window pattern, the carrier exposed groove window pattern and the alignment groove window pattern. And each patterned mask layer is used as a mask for etching in batches to form the cavity structure groove 202, the carrier exposed groove 201 and the alignment groove 203 of different depths, but this solution will increase certain process costs. Of course, the specific preparation scheme for preparing the cavity structure groove 202, the carrier exposed groove 201 and the alignment groove 203 can be selected according to different application scenarios, and is not limited here.

[0133] S22: forming a getter structure 205 in the cavity structure groove 202, and forming solder bumps 204 on both sides of the cavity structure groove 202; Fig.16 shown.

[0134] The step S22 of forming a getter structure 205 in the cavity structure groove 202 and forming solder bumps 204 on both sides of the cavity structure groove 202 specifically includes the following steps:

[0135] S220 : applying photoresist again on the surface of the second substrate 200 , and sequentially exposing, developing and ultraviolet treating the photoresist to form a patterned fourth mask layer on the surface of the second substrate 200 .

[0136] The fourth mask layer includes a getter structure window pattern and a barrier layer. The width of the getter structure window pattern is smaller than the width of the cavity structure groove 202 .

[0137] S221 : using the patterned fourth mask layer as a mask, depositing a getter material in the getter structure window pattern to form the getter structure 205 .

[0138] The getter is a material that can effectively absorb active gases, and can absorb residual gases, increase the vacuum degree, and improve the environment atmosphere in the device. Preferably, the getter material can be metals such as Ti, Zr, V, Al, Ni, ZrVFe, and ZrCo.

[0139] S222: applying photoresist on the surface of the getter material layer, and sequentially exposing, developing and ultraviolet treating the photoresist to form a patterned fifth mask layer on the surface of the getter material layer.

[0140] The patterned fifth mask layer includes a solder bump window pattern and a barrier layer, and the solder bump window pattern is located on both sides of the cavity structure groove 202 .

[0141] S223: depositing solder, wherein the solder is formed in the solder bump window pattern and covers the patterned fifth mask layer; wherein the solder bump 204 and the bonding groove can be fitted into each other.

[0142] S224: removing the fifth mask layer and the excess solder formed thereon, the fourth mask layer and the excess getter material formed thereon, such as Fig.16 shown.

[0143] Among them, the specific steps in step S224 specifically include: first removing the fifth mask layer and the solder material on its surface through a film peeling process, then removing the fourth mask layer and the getter material on its surface through a second film peeling process, and then using the NMP (N-methyl-2-pyrrolidone) solution in the wet etching process to remove the residual photoresist.

[0144] The first part and the second part mentioned above can be prepared simultaneously, or the first part can be prepared first and then the second part. Those skilled in the art can prepare them according to the specific circumstances, and the preparation order of the first part and the second part is not limited here.

[0145] After completing the preparation of the first and second parts, the third part is prepared: bonding the first substrate and the second substrate to complete the preparation of the vacuum device. The specific steps are as follows:

[0146] S31: Using the pattern fitting between the alignment mark 110 and the alignment groove 203 as an alignment reference, the bonding groove 107 is engaged with the solder bump 204 to bond the first surface of the second substrate 200 to the first surface of the first substrate 100 to form the vacuum device; Fig.17 shown.

[0147] Among them, in step S31, the pattern fitting between the alignment mark 110 and the alignment groove 203 is used as an alignment reference to fit the bonding groove 107 with the solder bump 204, which specifically includes the following steps:

[0148] S311: Using the pattern fitting between the alignment mark 110 and the alignment groove 203 as an alignment reference, the bonding groove 107 is fitted into the solder bump 204, such as Fig.17 shown.

[0149] S312: performing thermal annealing on the first substrate 100 and the second substrate 200 that have been bonded.

[0150] Step S32: grinding the second surface of the second substrate 200 in the vacuum device to expose the carrier electrode 109 and the alignment mark 110 respectively; Fig.18 shown.

[0151] The step S32 of grinding the second surface of the second substrate 200 in the vacuum device to expose the disk electrode 109 and the alignment mark 110 respectively includes the following steps:

[0152] S321: grinding the second surface of the second substrate 200 in the vacuum device to expose the carrier electrode 109 and the alignment mark 110 respectively.

[0153] When grinding the second surface of the second substrate 200 in the vacuum device, grinding is stopped after the carrier electrode 109 and the alignment mark 110 are exposed. Because the cavity structure groove 202 is shallower than the carrier exposed groove 201 and the alignment groove 203, the cavity structure 111 will not be exposed after the carrier and the alignment mark 110 are exposed, so the cavity structure 111 will not be damaged, thereby improving the vacuum effect of the vacuum device.

[0154] S322: measuring the offset of the scale lines of the alignment marks in different exposure units on the bonded wafer formed by the first substrate and the second substrate relative to the alignment groove, wherein the offset is the bonding deviation of the bonded wafer;

[0155] If the offset of the exposure unit exceeds a first threshold, it is determined that the vacuum device on the exposure unit fails.

[0156] Please refer to Fig.18 and Fig.21 Specifically, the alignment mark 110 has a cross-shaped scale line structure, the alignment groove 203 is a cross-shaped groove, the alignment groove 203 matches the shape of the alignment mark 110, the size of the alignment groove is equal to the size of the alignment mark, the maximum width of the alignment groove 203 is equal to the maximum width of the alignment mark 110, and the maximum length of the alignment groove 203 is equal to the maximum length of the alignment mark 110. The number of scale lines on the scale line structure of the alignment mark 110 can be set according to the accuracy requirements of the vacuum device for substrate bonding deviation, which is not limited here.

[0157] The specific principle of detecting the bonding deviation of the bonded wafer formed by the first substrate 100 and the second substrate 200 through the alignment mark 110 and the alignment groove 203 is as follows:

[0158] As can be seen from the above, at least one alignment mark 110 is set in the non-chip area a2 of each first exposure unit A1 of the first substrate 100. Therefore, a second exposure unit B1 corresponding to the first exposure unit is also set on the second substrate. An alignment groove 203 corresponding to the alignment mark 110 is set in the non-chip area a2 of each second exposure unit B2. After the first substrate 100 and the second substrate 200 are bonded, when the bonding of the first substrate 100 and the second substrate 200 is just right without deviation, the alignment mark 110 in each exposure unit on the bonded wafer will also be just embedded in the alignment groove 20, and will not cover the scale on the alignment mark 110.

[0159] When there is an offset in the bonding between the first substrate 100 and the second substrate 200, the second substrate 200 on both sides of the alignment groove 203 will block part of the scale on the alignment mark 110 due to the bonding deviation during the bonding process. Therefore, after the alignment mark 110 is exposed, by measuring the blocked scale value on the alignment mark 110 in each exposure unit of the bonded wafer, that is, the offset of the alignment mark 110 relative to the alignment groove 203, the bonding deviation of the first substrate 100 and the second substrate 200 can be detected, and according to whether the bonding deviation is greater than the first threshold, it is determined whether the chip in any exposure unit is failed, that is, whether the vacuum device is failed. Preferably, the first threshold is set to 1μm. If there is an offset between the alignment mark 110 of the exposure unit and the alignment groove 203 that exceeds 1μ, the wafer formed after the first substrate and the second substrate are bonded needs to be subjected to failure analysis, and the manufacturing process of the vacuum device is improved according to the failure analysis results. If the bonding deviation of some exposure units in the bonded wafer does not exceed the first threshold, the wafer still performs subsequent process steps (metal lead process, passivation layer process, etc.) after completing the failure analysis. After completing the entire manufacturing process of the vacuum device, the exposure unit whose bonding deviation does not exceed the first threshold is subjected to wafer testing. If it meets the test standards, it can be used as a qualified vacuum device product. The failure analysis, subsequent process steps and wafer testing are conventional technical means in this field and are not described in detail here. It should be added that in order to enable the second substrate 200 on both sides of the alignment groove 203 to block the alignment mark 110, the thickness of the alignment mark 110 is set to be very thin. For example, the depth of the alignment groove 203 is 400μ, while the thickness of the alignment mark 110 is only about 2μ. Of course, this is just an example. The actual thickness of the alignment mark 110 can be set according to demand and is not limited here.

[0160] Because the bonding deviation can be directly read by a measuring device or an optical microscope, it is not necessary to set up a dedicated failure detection device to detect whether the vacuum device has failed, thereby reducing the process cost of device manufacturing.

[0161] In addition, because the alignment mark 110 and the alignment groove 203 can serve as an alignment reference during substrate bonding, the alignment mark 110 and the alignment groove 203 can perform both overlay measurement during the device preparation process and overlay measurement after the device preparation is completed, thereby improving the utilization rate of the effective area of ​​a single wafer.

[0162] In summary, the method for preparing a vacuum device provided by an embodiment of the present invention arranges the carrier groove outside the bonding groove so that the carrier electrode is arranged outside the cavity structure, thereby avoiding the carrier electrode from affecting the vacuum effect of the cavity structure and improving the vacuum effect of the cavity structure. Furthermore, the arrangement of the bonding groove not only avoids the solder bump from overflowing to the surroundings during the subsequent substrate bonding, thereby further improving the vacuum effect of the cavity structure, but also improves the bonding effect of the substrate because the bonding groove and the solder bump are interlocked. In addition, by forming the carrier exposed groove on the second substrate in advance, the vacuum device formed after bonding can be directly ground to expose the carrier electrode and the alignment mark, thereby avoiding the possibility of damage to the cavity structure, thereby further improving the vacuum effect of the cavity structure.

[0163] Furthermore, the alignment mark and the alignment groove are arranged in a non-chip area, which does not occupy the use area of ​​the vacuum device. After the vacuum device is prepared, the vacuum device chip area is reserved by cutting the scribe line. The alignment mark and the alignment groove can not only be used as an alignment reference during substrate bonding, but also can be used to measure the bonding offset of the first substrate and the second substrate, thereby improving the utilization rate of the effective area of ​​a single wafer. At the same time, it is possible to detect whether the vacuum device has failed without the need for a dedicated failure detection device, thereby reducing the process cost of device manufacturing.

[0164] Please refer to Fig.18 The embodiment of the present invention further provides a vacuum device, which is prepared by the method for preparing the vacuum device provided in the above embodiment, and the structure includes:

[0165] A first substrate 100, wherein a device layer is formed on a first surface of the first substrate 100;

[0166] A bonding groove and a pad electrode 109, wherein the bonding groove 107 and the pad electrode 109 are both formed in the chip region a1 of the device layer, and the pad electrode is formed outside the bonding groove;

[0167] A plurality of cavity structures 111, wherein the plurality of cavity structures 111 are formed in a corresponding device layer in an area surrounded by the bonding groove;

[0168] A second substrate 200, wherein a first surface of the second substrate 200 is respectively formed with a cavity groove 202; a getter structure 205 is formed in the cavity groove 202, and solder bumps 204 are formed on the first surface of the second substrate 200 on both sides of the cavity groove 202;

[0169] The first substrate 100 and the second substrate 200 are embedded in the bonding groove 107 through the solder bump 204 , the cavity groove 202 corresponds to the cavity structure 111 to form a closed cavity, and the carrier electrode 109 and the alignment mark 110 are exposed on the second surface of the second substrate 200 .

[0170] The materials, formation process, working principle, specific implementation method and beneficial effects involved in the vacuum device in the embodiment of the present invention can all be found in the preparation method of the vacuum device in the embodiment of the present invention, and will not be described in detail here.

[0171] An embodiment of the present invention further provides an electronic device, comprising the vacuum device provided in the above embodiment.

[0172] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for preparing a vacuum device, characterized in that: include: Providing a first substrate, and forming a device layer on a first surface of the first substrate; Forming a bonding groove and a pad electrode in a chip region of the device layer, wherein the pad electrode is located outside the bonding groove, and forming an alignment mark in a non-chip region of the device layer; Forming a plurality of cavity structures in the device layer corresponding to the area enclosed by the bonding groove, and forming a dicing groove at the junction of the chip area and the non-chip area; Providing a second substrate, and forming a cavity groove, a carrier exposed groove and an alignment groove on the first surface of the second substrate respectively; wherein the carrier exposed groove corresponds to the carrier electrode, the cavity groove corresponds to the cavity structure, and the alignment groove corresponds to the alignment mark; forming a getter structure in the cavity groove, and forming solder bumps on the first surface of the second substrate on both sides of the cavity groove, wherein the solder bumps and the bonding grooves can be engaged with each other; Using the graphic fitting between the alignment mark and the alignment groove as an alignment reference, the bonding groove is engaged with the solder bump to bond the first surface of the second substrate with the first surface of the first substrate, wherein the cavity groove corresponds to the cavity structure to form a closed cavity; The second surface of the second substrate is ground to expose the carrier electrode and the alignment mark.

2. The method for preparing a vacuum device according to claim 1, characterized in that: The first substrate includes a plurality of first exposure units, and the non-chip areas within the first exposure units are each provided with at least one alignment mark, and the alignment mark is a cross-shaped scale line structure; the second substrate includes a plurality of second exposure units, and the non-chip areas within the second exposure units are each provided with at least one alignment groove, and the alignment groove is a cross-shaped groove; the size of the alignment groove is equal to the size of the alignment mark.

3. The method for preparing a vacuum device according to claim 2, characterized in that: The method further includes: Measuring the offset of the scale lines of the alignment marks in different exposure units on the bonded wafer formed by the first substrate and the second substrate relative to the alignment groove, wherein the offset is the bonding deviation of the bonded wafer; If the offset of the exposure unit exceeds a first threshold, it is determined that the vacuum device on the exposure unit fails.

4. The method for preparing a vacuum device according to claim 1, characterized in that: Forming a device layer on the first surface of the first substrate specifically includes: Depositing an oxide layer and a silicon nitride layer in sequence on the first surface of the first substrate; forming a first polysilicon structure in the silicon nitride layer as a lower electrode of the vacuum device; forming a multi-layer oxide isolation structure on the silicon nitride layer on both sides of each of the first polysilicon structures; forming a patterned sacrificial layer on the first polysilicon structure and the multi-layer oxide isolation structure; forming a structural layer on the first substrate, wherein the structural layer covers the patterned sacrificial layer; The surface of the structural layer is doped to form an upper electrode of the device.

5. The method for preparing a vacuum device according to claim 4, characterized in that: A plurality of cavity structures are formed in the device layer corresponding to the bonding groove enclosed area, and a dicing groove is formed at the junction of the chip area and the non-chip area, specifically comprising: Forming a patterned first mask layer on the structural layer, wherein the patterned first mask layer includes a plurality of sacrificial hole window patterns, a scribe line groove window pattern and a barrier layer; Using the patterned first mask layer as a mask, the structural layer and the sacrificial layer in the plurality of sacrificial hole window patterns and the scribe line groove window patterns are etched to form the plurality of cavity structures and the scribe line grooves.

6. The method for preparing a vacuum device according to claim 1, characterized in that: A bonding groove and a pad electrode are formed in a chip region of the device layer, the pad electrode is located outside the bonding groove, and an alignment mark is formed in a non-chip region of the device layer, specifically comprising: forming a patterned second mask layer on the surface of the device layer; Forming a bonding groove and a pad carrier groove with the same depth in the first chip region of the device layer, wherein the pad carrier groove is located outside the bonding groove; Re-patterning the patterned second mask layer, wherein the re-patterned second mask layer includes a carrier groove pattern and an alignment mark pattern; Depositing a metal layer, wherein the metal layer covers the second patterned mask layer, the carrier groove, and the alignment mark pattern; The re-patterned second mask layer and the metal layer formed thereon are removed, a carrier electrode is formed in the carrier groove, and an alignment mark is formed in a non-chip area of ​​the device layer.

7. The method for preparing a vacuum device according to claim 1, characterized in that: A cavity structure groove, a carrier exposed groove and an alignment groove are respectively formed on the first surface of the second substrate, specifically comprising: forming a patterned third mask layer on the first surface of the second substrate, wherein the patterned third mask layer comprises a cavity structure groove window pattern, a carrier exposed groove window pattern, an alignment groove window pattern and a barrier layer; Using the patterned third mask layer as a mask, etching the second substrate corresponding to the cavity structure groove window pattern, the carrier exposed groove window pattern and the alignment groove window pattern, respectively, to form the cavity structure groove, the carrier exposed groove and the alignment groove; Wherein, the depth of the cavity structure groove is respectively greater than the depth of the carrier exposed groove and the depth of the alignment groove.

8. The method for preparing a vacuum device according to claim 7, characterized in that: Forming a getter structure in the cavity structure groove and forming solder bumps on both sides of the cavity structure groove, specifically comprising: forming a patterned fourth mask layer on the first surface of the second substrate, wherein the patterned fourth mask layer comprises a getter structure window pattern and a barrier layer, wherein the getter structure window pattern is located in the cavity structure groove; Using the patterned fourth mask layer as a mask, depositing a getter material in the getter structure window pattern to form the getter structure; forming a patterned fifth mask layer on the getter material, the patterned fifth mask layer comprising a solder bump window pattern and a barrier layer, the solder bump window pattern being located on both sides of the cavity structure groove; Depositing solder, wherein the solder is formed in the solder bump window pattern and covers the patterned fifth mask layer; The fifth mask layer and excess solder formed thereon, and the fourth mask layer and excess getter material formed thereon are removed.

9. The method for preparing a vacuum device according to claim 1, characterized in that: The second substrate is a high-resistance substrate.

10. A vacuum device, characterized in that: Prepared by the method for preparing a vacuum device according to any one of claims 1 to 9, the structure comprises: a first substrate, wherein a device layer is formed on a first surface of the first substrate; A bonding groove and a pad electrode, wherein the bonding groove and the pad electrode are both formed in the chip region of the device layer, and the pad electrode is formed outside the bonding groove; A plurality of cavity structures, wherein the plurality of cavity structures are formed in the device layers corresponding to the area enclosed by the bonding groove; A second substrate, wherein a first surface of the second substrate is respectively formed with a cavity groove; a getter structure is formed in the cavity groove, and solder bumps are formed on the first surface of the second substrate on both sides of the cavity groove; The first substrate and the second substrate are embedded in the bonding groove through the solder bump, the cavity groove and the cavity structure form a closed cavity corresponding to each other, and the carrier electrode and the alignment mark are exposed on the second surface of the second substrate.

Images