Chip structure determination method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a chip structure determination method and device, a storage medium and electronic equipment, and relates to the technical field of computers, the method is applied to the electronic equipment, and the method comprises the steps that cache attribute information and / or equipment attribute information are / is acquired; determining chip structure information according to the cache attribute information and / or the equipment attribute information; and constructing a chip structure chart according to the chip structure information. Therefore, by analyzing the cache attribute information and / or the equipment attribute information, the hardware configuration of the chip is quickly known, and the structure chart is automatically generated based on the hardware configuration, so that a designer can more intuitively know the internal composition and layout of the chip, and more accurate tuning and verification are carried out.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a chip structure determination method, device, storage medium and electronic device. Background Art

[0002] With the continuous advancement of chip technology, especially in the context of the growing demand for high-performance computing such as artificial intelligence, big data processing, and virtual reality, the design and structure of chips have become increasingly complex. In order to cope with the increasing demand for computing power, chip manufacturers continue to introduce new architectural innovations in their designs, such as multi-core processing, heterogeneous computing, and integrating more functional units on-chip. Although the introduction of these technologies has greatly improved the computing power of the processor, it has also made the chip structure more complex.

[0003] However, chip manufacturers usually do not disclose the internal process and technical details of the chip due to various considerations. This situation makes it difficult for the whole machine manufacturer to schedule and optimize the process after using the chip. The lack of sufficient micro-architecture details makes it difficult for the whole machine manufacturer to perform targeted optimization according to the actual situation, which affects the maximum performance of the chip. Therefore, it is necessary to provide a method for analyzing and dissecting the chip micro-architecture. Summary of the invention

[0004] The present disclosure provides a chip structure determination method, device, storage medium and electronic device to at least solve the above technical problems existing in the prior art.

[0005] The technical solution of the embodiment of the present disclosure is implemented as follows: In a first aspect, an embodiment of the present disclosure provides a chip structure determination method, the method being applied to an electronic device, the method comprising: Obtain cache attribute information and / or device attribute information; Determine chip structure information according to the cache attribute information and / or device attribute information; A chip structure diagram is constructed according to the chip structure information.

[0006] In the above solution, determining the chip structure information according to the cache attribute information and / or the device attribute information includes: Analyze the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics; The cache characteristics and / or core characteristics are analyzed to obtain chip structure information.

[0007] In the above solution, the cache attribute information includes: the number of cache levels and / or attribute information of each level of cache; The analyzing the cache attribute information to determine cache characteristics includes: Determine information of a first-level instruction cache, information of a first-level data cache, information of a second-level cache, and information of a third-level cache according to the number of cache levels and / or attribute information of each level of cache; The information includes at least one of the following: cache size, number of cache blocks, and cache block size.

[0008] In the above solution, the device attribute information includes: slot related information; Analyze the device attribute information to determine the core features, including: Determine a first feature according to the slot related information; the first feature includes: The number of sockets, the number of processor cores contained in each socket, and whether each of the processor cores supports hyper-threading technology.

[0009] In the above solution, the device attribute information includes: non-uniform memory access (NUMA, Non Uniform Memory Access) node information; Analyze the device attribute information to determine the core features, including: Determine a second feature according to the NUMA node information; the second feature includes: The number of NUMA nodes, the number of processor cores contained in each NUMA node, and the distribution of processor cores in each NUMA node.

[0010] In the above solution, analyzing the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics includes: Analyze the cache attribute information and / or the device attribute information to determine a third feature; the third feature includes: The cache size corresponding to each processor core in each cache level; Cache write policies supported by caches at all levels; Whether the NUMA node supports hyperthreading technology.

[0011] In the above solution, analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The cache feature and / or core feature is analyzed based on the first rule to determine second structure information, where the second structure information includes: a situation where the cache is shared between processor cores.

[0012] In the above solution, analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The second feature is analyzed based on the first rule to determine first structural information, where the first structural information includes: the number of processor groups (CCX, CPU Complex) of the NUMA node, and the number of processor cores of each CCX.

[0013] In the above solution, constructing a chip structure diagram according to the chip structure information includes: A chip structure diagram is constructed according to the chip structure information using a drawing model.

[0014] In the above scheme, the method further comprises: Acquire a training data set; the training data set includes at least one sample chip structure information and a logical architecture diagram of the sample chip structure corresponding to each sample chip structure information; A preset neural network model is trained according to the training data set to obtain a trained neural network model as the drawing model.

[0015] In the above solution, the obtaining of cache attribute information and / or device attribute information includes: At least one query instruction is called by using a test tool, and cache attribute information and / or device attribute information of the electronic device is obtained according to the query instruction.

[0016] In a second aspect, an embodiment of the present disclosure provides a chip structure determination device, the device is applied to an electronic device, and the device includes: An acquisition module, used to acquire cache attribute information and / or device attribute information; A first processing module, configured to determine chip structure information according to the cache attribute information and / or device attribute information; The second processing module is used to construct a chip structure diagram according to the chip structure information.

[0017] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein: The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute any one of the chip structure determination methods.

[0018] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute any one of the chip structure determination methods.

[0019] The embodiments of the present disclosure have the following beneficial effects: The chip structure determination method, device, storage medium and electronic device provided in the embodiments of the present disclosure are applied to obtain cache attribute information and / or device attribute information; determine chip structure information based on the cache attribute information and / or device attribute information; and construct a chip structure diagram based on the chip structure information. In this way, by analyzing the cache attribute information and / or device attribute information, the hardware configuration of the chip can be quickly understood, and a structure diagram is automatically generated based on the hardware configuration, so that designers can more intuitively understand the internal composition and layout of the chip, thereby performing more accurate tuning and verification.

[0020] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of a chip structure determination method provided in an embodiment of the present disclosure; Figure 2 A schematic diagram of a chip structure provided for an application embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a chip structure determination device provided in an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0023] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] If similar descriptions of "first / second" appear in the application documents, the following instructions are added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0026] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations.

[0027] CCX (CPU Complex): refers to a small collection of multiple cores in a central processing unit (CPU) chip. Each CCX contains several cores, which is a functional module in the CPU architecture used to handle multi-threaded tasks and improve computing performance. Usually, a CCX contains one or more cores, and multiple CCXs can be combined to form a more powerful multi-core processor.

[0028] CCD (Core Chiplet Die): refers to a complete Die, which can be understood as a CCD is a Die.

[0029] Die: refers to a small chip that is a component of the CPU. It is a physical packaging unit. A complete CPU chip is composed of multiple Dies, and each Die independently carries a certain computing power. Each Die can contain multiple functional modules or computing cores and is the smallest physical unit of the CPU chip.

[0030] A CPU chip is usually composed of multiple CCDs, each of which is an independent Die containing multiple CCXs. Each CCD is connected to other CCDs through interconnection technology to form a powerful multi-core computing unit.

[0031] In modern high-performance CPUs, multiple Dies are integrated into one chip to improve overall performance and power efficiency. Each Die is called a CCD, each CCD contains one or more CCXs, and each CCX contains one or more cores. Through this hierarchical structure, the CPU can flexibly allocate computing resources according to task requirements to achieve a balance between high performance and low power consumption.

[0032] With the continuous increase in computing needs, especially in the field of high-performance computing, higher requirements are placed on the number of cores, performance, and efficiency of processors. For example, AMD has adopted innovative packaging technology and architectural design in its Zen architecture to meet these challenges and promote the improvement of its multi-core processing capabilities. The Zen1 architecture introduced the MCM (Multi-ChipModule) packaging solution for the first time, abandoning the traditional monolithic design, which is to package multiple small chips (Die) into one CPU. This design concept aims to increase the number of cores while achieving high concurrent processing capabilities by combining multiple Dies.

[0033] However, although MCM packaging has made progress in the number of cores, it has significant deficiencies in the communication efficiency between multiple Dies. Since an off-chip bus is used for communication between Dies, communication latency and bandwidth bottlenecks have become important factors affecting overall performance. In particular, in some application scenarios that require frequent access to multiple cores, the performance of the MCM architecture is not satisfactory. Therefore, although MCM technology has advantages in increasing the number of cores and improving production flexibility, the communication performance bottleneck it brings still limits the further improvement of processor performance in some cases.

[0034] In order to solve this problem, AMD has made relatively significant architectural adjustments in the Zen2 architecture, especially the introduction of the IO Die separation design. Specifically, AMD separated the IO (Input / Output) function from the core chip (CoreDie) and designed an independent IO Die. By using the previous generation process to manufacture IO Die, AMD can improve the yield rate and reduce costs. At the same time, the core chip can use the latest process to run with higher performance and lower power consumption. In this way, not only the production efficiency of Die is improved, but also the overall cost of chip manufacturing is effectively reduced. At the same time, the independent design of IODie also solves the communication bottleneck problem in the previous MCM architecture, which greatly improves the efficiency of data transmission between Core Dies, thereby improving the overall performance of the CPU.

[0035] However, with the continuous development of the above technologies, although the chip performance has been improved, the structural complexity of the chip has also increased, because it involves the coordination of different functional modules (Core Die, IO Die), different manufacturing processes and optimized transmission paths. The chip is no longer a simple single integrated structure, but consists of multiple small modules that need to work efficiently with each other to achieve stronger performance and lower costs.

[0036] In actual applications, chip manufacturers usually do not disclose the internal process and technical details of the chip due to various considerations. This situation leads to greater technical difficulties for the whole machine manufacturers when scheduling and optimizing the process and running process after using the chip. The lack of sufficient micro-architecture details makes it difficult for the whole machine manufacturers to perform targeted optimization according to the actual situation, affecting the maximum performance of the chip. Therefore, it is necessary to provide a method for analyzing and dissecting the chip micro-architecture.

[0037] Based on this, the embodiments of the present disclosure provide a chip structure determination method, device, storage medium and electronic device, which obtain cache attribute information and / or device attribute information; determine chip structure information based on the cache attribute information and / or device attribute information; and construct a chip structure diagram based on the chip structure information. In this way, by analyzing the cache attribute information and / or device attribute information, the hardware configuration of the chip can be quickly understood, and a structure diagram can be automatically generated based on the hardware configuration, thereby analyzing and dissecting the chip microarchitecture, so that designers can more intuitively understand the internal composition and layout of the chip, thereby performing more accurate tuning and verification.

[0038] Figure 1 A schematic diagram of a chip structure determination method provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the method is applied to electronic equipment, and the chip structure determination method includes: Step 101: Obtain cache attribute information and / or device attribute information; Step 102: Determine chip structure information according to the cache attribute information and / or device attribute information; Step 103: construct a chip structure diagram according to the chip structure information.

[0039] Here, the cache attribute information may refer to: specific information of the cache part in the chip, such as the size and type of the cache (first level (L1, Level 1) cache, L2 (L2, Level 2) cache, etc.), the hierarchical structure of the cache, etc.

[0040] Device attribute information may refer to: detailed information of other hardware or devices used by the chip, such as the number of processor cores, supported interfaces, etc.

[0041] Based on the acquired cache attribute information and / or device attribute information, the chip structure information is inferred. For example, the size and hierarchy of the cache may affect the chip architecture design, and device attributes (such as the number of cores, interface type, etc.) also help determine how different modules of the chip are connected to each other. After the chip structure information is determined, this information is graphed to construct a chip structure diagram, which shows the layout, connection method and hierarchical relationship of each component inside the chip.

[0042] In this way, since designers can more intuitively understand the internal composition and layout of the chip, it can help designers understand the internal architecture of the chip and how the various components work together, thereby performing more accurate tuning and verification.

[0043] In some embodiments, determining chip structure information according to the cache attribute information and / or device attribute information includes: Analyze the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics; The cache characteristics and / or core characteristics are analyzed to obtain chip structure information.

[0044] Here, cache characteristics refer to the specific characteristics of the cache, such as cache size, cache hierarchy (L1, L2, etc.), cache access speed, etc.

[0045] Core characteristics: refers to the characteristics of the processor core, such as the performance of each core, the number of threads supported, etc.

[0046] By analyzing cache features (such as cache size, hierarchy, etc.) and processor core features (such as the number of cores, etc.), we can further infer the overall structure and performance of the chip. For example, by analyzing the number of processor cores and the relationship between cache hierarchies, we can infer whether the chip supports multi-core, whether the cache is shared, etc.

[0047] In this way, by analyzing information about cache properties and device characteristics, the overall architectural design of the chip can be determined and inferred, including cache configuration, processor core characteristics, etc. Ultimately, this information helps understand how the chip works and how to optimize performance.

[0048] In some embodiments, the cache attribute information includes: the number of cache levels and / or attribute information of caches at each level; The analyzing the cache attribute information to determine cache characteristics includes: Determine information of a first-level instruction cache, information of a first-level data cache, information of a second-level cache, and information of a third-level cache according to the number of cache levels and / or attribute information of each level of cache; The information includes at least one of the following: cache size, number of cache blocks, and cache block size.

[0049] Here, cache levels: refers to different levels of cache. A chip can have multiple levels of cache (such as L1, L2, L3). L1 is usually the smallest but fastest cache, while L3 is usually the largest but slower.

[0050] Cache attributes: refers to the various attributes of the cache, such as cache size.

[0051] In one example, the cache attribute information obtained includes but is not limited to the following: LEVEL1_ICACHE_SIZE: 32768; LEVEL1_ICACHE_ASSOC: 8; LEVEL1_ICACHE_LINESIZE: 64; LEVEL1_DCACHE_SIZE: 32768; LEVEL1_DCACHE_ASSOC: 8; LEVEL1_DCACHE_LINESIZE: 64; LEVEL2_CACHE_SIZE: 524288; LEVEL2_CACHE_ASSOC: 8; LEVEL2_CACHE_LINESIZE: 64; LEVEL3_CACHE_SIZE: 268435356; LEVEL3_CACHE_ASSOC: 64; LEVEL3_CACHE_LINESIZE: 64; LEVEL4_CACHE_SIZE: 0; LEVEL4_CACHE_ASSOC: 0; LEVEL4_CACHE_LINESIZE: 0.

[0052] ASSOC stands for Associativity, which refers to the cache association, that is, the cache organization, indicating how the cache divides and stores data. The cache can be divided into multiple cache sets, each of which contains multiple cache lines. The association determines the number of cache lines in each set.

[0053] LINESIZE refers to the size of the cache line, that is, the amount of data that can be stored in each cache line. The cache line is the basic unit of cache, and the amount of data loaded from the memory into the cache each time is a cache line.

[0054] ICACHE stands for instruction cache and DCACHE stands for data cache.

[0055] LEVEL1, LEVEL2, LEVEL3, and LEVEL4 represent the first-level cache, second-level cache, third-level cache, and fourth-level cache respectively.

[0056] Based on the above analysis, we can obtain the information of the first-level instruction cache, the first-level data cache, the second-level cache, and the third-level cache as shown in Table 1 below.

[0057] Table 1

[0058] Here, considering the detailed information of each level of cache (such as cache size, number of cache blocks, cache block size) helps to reveal the architectural design of the chip. For example, the configuration of the first-level instruction cache, the first-level data cache, and the second-level cache and third-level cache is often closely related to the chip's architecture and design goals. By analyzing the cache attribute information, some structural characteristics of the chip can be inferred.

[0059] In some embodiments, the device attribute information includes: slot related information; Analyze the device attribute information to determine the core features, including: Determine a first feature according to the slot related information; the first feature includes: The number of sockets, the number of processor cores contained in each socket, and whether each of the processor cores supports hyper-threading technology.

[0060] Here, the socket related information can reflect the number of sockets in the device, the hardware contained in each socket (such as processor, memory module, etc.), etc.

[0061] In one example, the acquired slot related information includes but is not limited to the following: Socket count:2; Socket Designation: CPU0; L1 Cache Handle: 0x0006; L2 Cache Handle: 0x0007; L3 Cache Handle: 0x0008; Core Count: 64; Core Enabled: 64; Thread Count: 128.

[0062] Among them, Socket count indicates the number of sockets; Socket Designation indicates the socket identification; CacheHandle indicates the cache handle, which is usually used as a unique identifier in the system. Core Count indicates the number of cores. As shown above, the processor has 64 cores. Core Enabled indicates the number of enabled cores. As shown above, all 64 cores are enabled. ThreadCount indicates the number of threads. As shown above, the processor supports 128 threads, usually because hyperthreading technology is enabled and each core can process two threads.

[0063] Slot-related information can also include the following information: Characteristics: 64-bit capable, indicating support for 64-bit architecture; Multi-Core, which stands for a multi-core processor, meaning that the processor has multiple cores (64 cores); Hardware Thread, indicating support for hardware threads; Execute Protection, which means execution protection, helps prevent certain types of malicious attacks.

[0064] Enhanced Virtualization: indicates enhanced virtualization support.

[0065] The required information can be analyzed based on the above slot related information, such as: the number of processor cores contained in a single slot (64 as above), and whether each of the processor cores supports hyperthreading technology (supported as above).

[0066] Here, considering the number of sockets helps to understand the processor scalability, while the number of processor cores in each socket reveals the core scale of the chip. Further analysis of whether the core supports hyperthreading technology can infer the chip's design in terms of parallel processing capabilities and multi-tasking execution efficiency. Inferring these features provides a basis for constructing a chip structure diagram.

[0067] In some embodiments, the device attribute information includes: non-uniform memory access (NUMA) node information; Analyze the device attribute information to determine the core features, including: Determine a second feature according to the NUMA node information; the second feature includes: The number of NUMA nodes, the number of processor cores contained in each NUMA node, and the distribution of processor cores in each NUMA node.

[0068] Here, NUMA is a memory architecture in which each processor core or processor cluster has its own local memory while other memories are shared between different processors. This architecture helps improve the performance of the system, but the memory access speed may vary between different nodes.

[0069] Here, according to the obtained NUMA node information, the number and configuration of different NUMA nodes are understood, and the second feature is determined, such as: Number of NUMA nodes: how many NUMA nodes are there in the chip; The number of processor cores contained in each NUMA node; Distribution of processor cores within each NUMA node: How are processor cores allocated within a NUMA node, whether they are evenly distributed or have other special configurations.

[0070] In an example, NUMA node information may include but is not limited to the following: NUMA node 0CPU:0-15,128-143; NUMA node 1 CPU: 16-31, 144-159; NUMA node 2 CPU: 32-47, 160-175; NUMA node 3 CPU: 48-63, 176-191; NUMA node 4CPU: 64-79,192-207; NUMA node 5 CPU: 80-95, 208-223; NUMA node 6CPU: 96-111, 224-239; NUMA node 7 CPU: 112-127, 240-255.

[0071] According to the above content, the second feature can be analyzed, including: There are 8 NUMA nodes, each containing multiple CPU cores. The processor cores of each node are identified by the format of CPU:XY; each NUMA node has 32 CPU cores, including two different core number ranges (for example, NUMA node 0 has CPU 0-15 and CPU 128-143).

[0072] Here, considering the number of NUMA nodes reveals the memory and processor distribution architecture, while the number and distribution of processor cores in each node helps understand how the chip optimizes data access and parallel computing. With this information, we can infer the performance, memory access efficiency, and load balancing strategy of the chip in a multi-processor environment, and thus infer the structure of the chip.

[0073] In some embodiments, analyzing the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics includes: Analyze the cache attribute information and / or the device attribute information to determine a third feature; the third feature includes: The cache size corresponding to each processor core in each cache level; Cache write policies supported by caches at all levels; Whether the NUMA node supports Hyper-Threading technology.

[0074] Here, after obtaining the above first and second features, the first and second features and other information may be combined for further speculation to obtain a third feature; for example, the other information obtained may include: the number of threads, cache attribute information, etc.; wherein the cache attribute information, such as information about the L1 cache, is as follows: Socket Designation: L1-Cache: Indicates that the cache type is L1 cache.

[0075] Configuration: Enabled, Not Socketed, Level 1: Indicates that the L1 cache is enabled but has no socket and is a first-level cache.

[0076] Operational Mode: Write Back: indicates that the operation mode is write back. Of course, there may be other strategies such as a combination of write back and write through, on-demand update, write through, etc.

[0077] Location: Internal: Indicates that the cache is located inside the processor.

[0078] Installed Size: 4 MB: Indicates that the installed cache size is 4 MB.

[0079] Maximum Size: 4 MB: Indicates that the maximum supported cache size is 4 MB.

[0080] Supported SRAM Types: Pipeline Burst: Indicates that the supported SRAM type is pipeline burst, a memory access mode.

[0081] Installed SRAM Type: Pipeline Burst: Indicates that the installed SRAM type is also pipeline burst.

[0082] Speed: 1 ns: Indicates that the cache access speed is 1 nanosecond (ns).

[0083] Error Correction Type: Multi-bit ECC: Indicates the use of multi-bit ECC (Error Correction Code) technology, which can detect and correct multi-bit errors.

[0084] System Type: Unified: Indicates that the cache system type is unified, that is, the data and instruction caches are shared.

[0085] Other L2 Cache, L3 Cache, etc. are similar and are not illustrated here one by one.

[0086] The above information can be used to determine the third characteristics of the chip. For example, the size of each level of cache reveals the data access capability of each core, and the cache write strategy reflects the chip's design strategy for data consistency and performance optimization. At the same time, analyzing whether the NUMA node supports hyperthreading technology can infer the chip's performance scheduling method in multi-core and multi-threaded parallel computing. Combining these characteristics, the overall architecture of the chip, the cache management method, and the collaborative working mode of multiple processors can be inferred.

[0087] In some embodiments, analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The second feature is analyzed based on the first rule to determine first structural information, where the first structural information includes: the number of processor groups CCXs of the NUMA node, and the number of processor cores of each CCX.

[0088] Here, the first rule may be a rule for feature integration and analysis, which may indicate how to combine the above-mentioned various features to determine the chip structure information.

[0089] Here, NUMA node refers to a memory access architecture. Each NUMA node has a set of CPUs and memory, and there is a certain delay between the processor and the memory.

[0090] Each NUMA node has multiple processor groups (CCX, Core Complex), which are small units composed of multiple cores. Each CCX contains several processor cores.

[0091] Here, we can also detect the access delay of each CPU to different NUMA nodes and infer the situation of the NUMA node based on the range of the access delay. For example, the delay of CPU0-7 is in a range (for example, the delay distribution of CPU0-7 is 106.7, 106.7, 108.2, 108.3, 106.9, 106.2, 108.2, 108.8), the delay of CPU8-15 is in another range (110.3, 110.3, 110.3, 110.8, 110.7, 110.5, 111.0, 111.8), the delay of CPU16-23 is in a range of 204.3, 204.5, 204.3, 204.8, 204.7, 204.5, 206.0, 206.8), and so on. Through the above characteristics, we can analyze: NUMA0 node (including 0-15 CPUs), CPU 0-7 The latency is in one range, 8-15 in another, leading to the conclusion that 8 cores are the whole.

[0092] In some embodiments, analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The cache feature and / or core feature is analyzed based on the first rule to determine second structure information, where the second structure information includes: a situation where the cache is shared between processor cores.

[0093] In some embodiments, the method may further include: obtaining access test information, and determining second structure information in combination with the access test information.

[0094] Here, based on the cache characteristics and / or core characteristics obtained above, information such as the cache hierarchy, the size of each cache level, and the information of the processor core, such as the number of cores and the configuration of each core, can be known.

[0095] In one example, the transmission delay of accessing the cache between cores can also be used to make an inference to determine whether the cache is shared. For example, the following transmission delay is detected: Core0->Core2 26.3ns; Core0->Core1 27.9ns; Core0->Core3 27.6ns; Core0->Core497.9ns.

[0096] In this way, it can be determined that Core4 and Core0, Core1, Core2, and Core3 do not share L3 cache, and it can be further determined that each CCX contains 4 processor cores.

[0097] In another example, data of Core0 accessing L2 cache of other cores is obtained, as shown in Table 2 below.

[0098] Table 2

[0099] Based on Table 2 above, it can be further determined that the four cores share one L3 cache, which is not shared with other cores. CCX accesses other CCXs through IO Die, and direct data transmission between CCXs is not supported. A NUMA node contains two CCDs, and CCDs contain two CCXs, rather than a NUMA node containing four independent CCXs.

[0100] It should be noted that the above examples are only for illustrating that various cache attribute information, access test information, device attribute information, etc. can be obtained, and the chip structure information can be determined by analyzing and extracting the required features. There is no limitation on the specific first rule adopted. The first rule can actually contain a variety of information, which defines various feature extraction and information integration inference methods.

[0101] Here, we infer the chip structure by combining the analysis of cache characteristics and core characteristics. Analyzing the number of processor groups (CCX) of the NUMA node and the number of processor cores of each CCX helps us understand the multi-processor architecture of the chip and its internal distribution. Knowing the number of cores of each CCX under the NUMA node can infer the parallel computing capability of the chip and the coordination between multiple cores.

[0102] Next, by analyzing cache characteristics and core characteristics, we can also determine the shared cache between processor cores. Shared cache (such as L3 cache) is usually used to share data between multiple cores. Understanding how processor cores share cache, as well as the size, level, and distribution of cache, can help infer the chip's design ideas for optimizing data access, reducing bottlenecks, and improving multi-core processing performance.

[0103] In addition, the accuracy of the analysis was further verified by combining access test information to confirm the second structure information. Access test information is usually used to evaluate the access pattern, latency, and bandwidth of the cache. Through testing, the actual performance of each level of cache can be obtained, such as cache hit rate, access latency, and data transfer rate, so as to more accurately infer the performance characteristics and potential bottlenecks of the chip.

[0104] Based on the analysis of the first rule above, the required chip structure information can be analyzed so as to draw a chip structure diagram using the chip structure information.

[0105] In some embodiments, constructing a chip structure diagram according to the chip structure information includes: A chip structure diagram is constructed according to the chip structure information using a drawing model.

[0106] Here, the drawing model is used to present the hardware architecture of the chip as a graphical chip structure diagram in a visual manner according to the chip structure information.

[0107] For example, the chip structure information is determined as follows using the above method: (1) A single socket contains 4 NUMA nodes; (2) Each NUMA node contains 2 CCDs; (3) Each CCD contains two CCXs, and each CCX contains four processor cores; (4) Each Core contained in the CCX contains a private L1 instruction cache, L1 data cache, private L2 cache and a shared L3 cache.

[0108] Combining the above information, we can draw the following Figure 2 A chip structure diagram as shown in FIG. Figure 2 As shown, Socket-0 is drawn, which includes NUMA Node-0, NUMA Node-1, NUMA Node-2, and NUMA Node-3; and specifically presents the structures and associations of CCD-0, CCD-1, CCX-0, CCX-1, Core 0, Core 1, Core 2, Core 3, and L1 instruction cache (L1 Icache), L1 data cache (L1 Dcache), L2 cache (L2 cache), and L3 cache (L3 cache) in NUMA Node 0. It should be understood that NUMA Node 1, NUMA Node 2, and NUMA Node 3 can also have a similar structure to NUMA Node 0.

[0109] Here, using the drawing model to build a chip structure diagram can present the unknown chip hardware architecture in an intuitive and clear way, helping technicians better understand the various components of the chip and their interrelationships. Through the graphical chip structure diagram, the chip's NUMA nodes, processor groups (CCX), cores, cache levels (such as L1, L2, L3 cache) and their connections can be displayed, making the chip's design structure more transparent.

[0110] Furthermore, technicians can formulate corresponding core binding methods based on the chip structure diagram when conducting program testing, and determine which cores the program should be bound to for optimal performance. Even if the internal architecture is kept opaque to the outside world by the chip manufacturer, the system manufacturer can still obtain the chip framework required for application tuning and implement the maximum performance tuning method, thereby promoting more efficient chip development and application.

[0111] In some embodiments, the method further comprises: Acquire a training data set; the training data set includes at least one sample chip structure information and a logical architecture diagram of the sample chip structure corresponding to each sample chip structure information; A preset neural network model is trained according to the training data set to obtain a trained neural network model as the drawing model.

[0112] Here, the drawing model can be trained based on a neural network model, for example, a convolutional neural network (CNN) or a graph neural network (GNN) can be used, which can process data with spatial or graph structures.

[0113] In actual application, multiple chip structure information samples can be collected, each sample includes the detailed hardware architecture of the chip (such as NUMA nodes, CCD, CCX, core and cache hierarchical information). For each chip structure sample, a corresponding logical architecture diagram is provided. The logical architecture diagram shows how the levels and components of the chip structure are organized and connected, similar to the topology diagram of the chip.

[0114] Using these data (chip structure information and its corresponding logical architecture diagram), a neural network model is trained. The neural network model learns the relationship between the chip structure and its logical architecture diagram, and learns how to generate or predict the corresponding logical architecture diagram from the input chip structure information.

[0115] Through the training process, the neural network can gradually optimize its parameters, and finally obtain a model that can automatically generate the corresponding architecture diagram according to the new chip structure information. The trained neural network model can be used to draw the logical architecture diagram of the chip, that is, when the new chip structure information is input, the neural network can automatically generate the corresponding logical architecture diagram based on the existing training experience.

[0116] In this way, the drawing model can automatically generate the corresponding logic architecture diagram according to the chip structure information, avoiding the tediousness and errors in the traditional manual drawing process. This method can accelerate design iterations and improve the accuracy of the design, especially when dealing with complex structures, which can effectively reduce human errors. At the same time, the automated process enables designers to quickly verify and adjust the architecture and shorten the R&D cycle. By reducing manual intervention, this method can also significantly save design costs, especially in large-scale and highly complex chip designs.

[0117] In some embodiments, the method further comprises at least one of the following: receiving a tuning test result, wherein the tuning test result is an operation result after process debugging based on the drawn chip structure diagram; feeding back the operation result to the drawing model to optimize the drawing model; Receive at least one other sample chip structure information and a logical architecture diagram of the sample chip structure corresponding to each sample chip structure information, and update the drawing model according to the at least one other sample chip structure information and the logical architecture diagram of the sample chip structure corresponding to each sample chip structure information.

[0118] Specifically, a closed-loop feedback mechanism is designed to use the results of the running process (such as performance, power consumption, throughput, etc.) as feedback for the optimization of the drawing model. Through this mechanism, the drawing model can adjust its strategy according to the different results of each run, thereby continuously optimizing.

[0119] Here, considering that after the process configuration is tuned according to the chip structure diagram, the operating results obtained may not meet expectations, that is, the operating results that should be achieved when this configuration is applied to the chip in theory do not appear. It is believed that the deviation in the drawing of the chip result diagram may be stored. Therefore, a method for optimizing the drawing model with a feedback mechanism is proposed.

[0120] For example, if the running process performs poorly (such as slow running speed, uneven resource utilization, etc.), it indicates that there may be room for optimization in the chip structure diagram, or that the current chip structure diagram error causes the existing running results to fail to meet the requirements; for another example, if the power consumption is too high, it is necessary to check whether there is excessive computing or communication overhead, and the design can be further adjusted to reduce power consumption.

[0121] Here, different weights are set for the tuning test results of different samples. For example, some tuning test results come from known structures or verified chip structures. These tuning test results are usually more accurate and reliable. The weights of these test results are set higher to ensure that more reliance is placed on these test data with higher certainty during adjustments, thereby speeding up the optimization process and reducing potential errors.

[0122] For some chip structures determined based on speculation or incomplete data, their accuracy may not be as high as that of directly verified structures. Therefore, the tuning test results of these chip structures may be more uncertain or noisy. If you rely too much on these speculative results, it may cause the optimization process to deviate from the optimal path or over-adapt to certain specific assumptions. Therefore, reducing the weight of these results can help avoid the model from making incorrect adjustments due to these inaccurate data.

[0123] In this way, constantly adjusting the drawing model according to the actual operation results can effectively improve the drawing accuracy.

[0124] In some embodiments, obtaining cache attribute information and / or device attribute information includes: At least one query instruction is called by using a test tool, and cache attribute information and / or device attribute information of the electronic device is obtained according to the query instruction.

[0125] Here, the technician may use the test tool to send at least one query instruction to the electronic device, and obtain the cache attribute information of the device and / or the attribute information of other devices through the instruction.

[0126] Among them, test tools refer to special software or hardware tools used to test or analyze electronic equipment. It can be used to detect the performance and hardware status of the device.

[0127] Query command: This is a command or instruction by which a request is made to an electronic device to obtain relevant information.

[0128] Here, the electronic device may have a human-computer interaction interface, and various cache attribute information and / or device attribute information may be obtained by calling various query instructions through the test software. Multiple query instructions may be called by themselves, or selectively called by the user according to their own needs, and may be used based on actual conditions, which is not limited here.

[0129] In this way, technicians use the test tool to send query instructions to easily and quickly obtain information about the device's cache and other hardware properties.

[0130] In some embodiments, the testing tool and the drawing model may be integrated into certain hardware or software.

[0131] For example, at the software level, test tools and drawing models can be implemented as part of a software package. For example, some performance monitoring tools (such as CPU-Z, GPU-Z) can integrate performance testing and graphical display functions. In this case, the test tool will collect hardware data, and the drawing model function will process this data and display it on the user interface.

[0132] For example, at the hardware level, some dedicated hardware (such as embedded systems, instrument test equipment, etc.) can integrate corresponding test tools and drawing functions. There may be an embedded processor on the hardware platform to collect various information and display the drawing results of the drawing model through a display interface or external devices. Of course, the collected information can also be processed.

[0133] The integration of test tools and drawing models can automatically collect data and generate visual images. This integration improves efficiency, avoids switching between multiple tools, and allows users to complete testing, data analysis, and result presentation on one platform. Through graphical presentation, users can intuitively understand various information, features, chip structures, etc.

[0134] Through the method provided by the embodiment of the present disclosure, the structure of the chip can be inferred without knowing the chip micro-architecture, thereby helping the whole machine manufacturer to optimize CPU scheduling. The whole machine manufacturer can formulate a targeted binding core strategy based on the inferred chip structure, and determine which cores the program runs on for optimal performance during program testing, thereby avoiding frequent program migration or competition for shared resources (such as cache) between multiple cores, and can more efficiently utilize the various core resources of the processor to improve the overall system efficiency; as well as reducing the uncertainty of program runtime, which can improve the stability and predictability of the program, and avoid performance fluctuations caused by core switching or unbalanced loads and other beneficial effects.

[0135] In this way, even if chip manufacturers keep the microarchitecture opaque, system manufacturers can still perform performance tuning on applications, which helps improve performance, optimize resource utilization, reduce energy consumption, and perform effective program optimization in the absence of transparent information about the chip microarchitecture.

[0136] Figure 3 A schematic diagram of a chip structure determination device provided in an embodiment of the present disclosure; Figure 3 As shown, the device is applied to an electronic device, and the device includes: An acquisition module, used to acquire cache attribute information and / or device attribute information; A first processing module, configured to determine chip structure information according to the cache attribute information and / or device attribute information; The second processing module is used to construct a chip structure diagram according to the chip structure information.

[0137] In some embodiments, the first processing module is used to analyze the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics; The cache characteristics and / or core characteristics are analyzed to obtain chip structure information.

[0138] In some embodiments, the cache attribute information includes: the number of cache levels and / or attribute information of caches at each level; The first processing module is used to determine information of the first-level instruction cache, information of the first-level data cache, information of the second-level cache, and information of the third-level cache according to the number of cache levels and / or attribute information of each level of cache; The information includes at least one of the following: cache size, number of cache blocks, and cache block size.

[0139] In some embodiments, the device attribute information includes: slot related information; The first processing module is used to determine a first feature according to the slot related information; the first feature includes: The number of sockets, the number of processor cores contained in each socket, and whether each of the processor cores supports hyper-threading technology.

[0140] In some embodiments, the device attribute information includes: non-uniform memory access NUMA node information; The first processing module is used to determine a second feature according to the NUMA node information; the second feature includes: The number of NUMA nodes, the number of processor cores contained in each NUMA node, and the distribution of processor cores in each NUMA node.

[0141] In some embodiments, the first processing module is used to analyze the cache attribute information and / or the device attribute information to determine a third feature; the third feature includes: The cache size corresponding to each processor core in each cache level; Cache write policies supported by caches at all levels; Whether the NUMA node supports hyperthreading technology.

[0142] In some embodiments, the first processing module is used to analyze the second feature based on a first rule to determine first structural information, where the first structural information includes: the number of CCXs of the NUMA node, and the number of processor cores of each CCX.

[0143] In some embodiments, the first processing module is used to analyze the cache characteristics and / or core characteristics based on a first rule to determine second structural information, where the second structural information includes: a situation where the cache is shared between processor cores.

[0144] In some embodiments, the second processing module is used to construct a chip structure diagram according to the chip structure information using a drawing model.

[0145] In some embodiments, the second processing module is further used to obtain a training data set; the training data set includes at least one sample chip structure information and a logical architecture diagram of the sample chip structure corresponding to each sample chip structure information; A preset neural network model is trained according to the training data set to obtain a trained neural network model as the drawing model.

[0146] In some embodiments, the acquisition module is used to call at least one query instruction using a test tool, and obtain cache attribute information and / or device attribute information of the electronic device according to the query instruction.

[0147] It is understandable that, when the chip structure determination device provided in the above embodiment implements the corresponding chip structure determination method, the above processing can be assigned to different program modules as needed to complete all or part of the above-described processing. In addition, the device provided in the above embodiment and the embodiment of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0148] The embodiment of the present application provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the chip structure determination method.

[0149] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, wherein executable instructions are stored. When the executable instructions are executed by a processor, the processor will execute the chip structure determination method provided in the embodiment of the present application.

[0150] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface storage, optical disk, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0151] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0152] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file storing other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0153] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0154] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure; Figure 4 As shown, the electronic device 40 includes: a processor 401, and a memory 402 in communication with the processor 401; the memory 402 stores instructions that can be executed by the processor 401. The instructions are executed by the processor 401, so that the processor 401 can execute: Obtain cache attribute information and / or device attribute information; Determine chip structure information according to the cache attribute information and / or device attribute information; A chip structure diagram is constructed according to the chip structure information.

[0155] The electronic device and the corresponding chip structure determination method provided in the above embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0156] In actual application, the electronic device 40 may further include: at least one network interface 403. The various components in the electronic device 40 are coupled together via a bus system 404. It is understood that the bus system 404 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 404 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 4 In the figure, various buses are labeled as bus system 404. There may be at least one processor 401 and at least one memory 402. The network interface 403 is used for wired or wireless communication between the electronic device 40 and other devices.

[0157] The memory 402 in the embodiment of the present disclosure is used to store various types of data to support the operation of the electronic device 40 .

[0158] The method disclosed in the above embodiment of the present disclosure can be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 401 or the instruction in the form of software. The above processor 401 may be a general processor, a digital signal processor (DSP, DiGital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 401 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiment of the present disclosure. The general processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the present disclosure can be directly embodied as a hardware decoding processor to execute, or the hardware and software modules in the decoding processor can be combined to execute. The software module can be located in a storage medium, which is located in the memory 402. The processor 401 reads the information in the memory 402 and completes the steps of the aforementioned chip structure determination method in combination with its hardware.

[0159] In some embodiments, the electronic device 40 can be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), field programmable gate array (FPGA), general processor, controller, microcontroller (MCU), microprocessor, or other electronic components to execute the aforementioned method.

[0160] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0161] In the above description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0162] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0163] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0164] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0165] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for determining a chip structure, characterized in that: The method is applied to an electronic device, and the method comprises: Obtain cache attribute information and / or device attribute information; Determine chip structure information according to the cache attribute information and / or device attribute information; A chip structure diagram is constructed according to the chip structure information.

2. The method according to claim 1, characterized in that The determining chip structure information according to the cache attribute information and / or the device attribute information includes: Analyze the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics; The cache characteristics and / or core characteristics are analyzed to obtain chip structure information.

3. The method according to claim 2, characterized in that The cache attribute information includes: the number of cache levels and / or attribute information of caches at each level; Analyzing the cache attribute information to determine cache characteristics includes: Determine information of a first-level instruction cache, information of a first-level data cache, information of a second-level cache, and information of a third-level cache according to the number of cache levels and / or attribute information of each level of cache; The information includes at least one of the following: cache size, number of cache blocks, and cache block size.

4. The method according to claim 2, characterized in that: The device attribute information includes: slot related information; Analyze the device attribute information to determine the core features, including: Determine a first feature according to the slot related information; the first feature includes: The number of sockets, the number of processor cores contained in each socket, and whether each of the processor cores supports hyper-threading technology.

5. The method according to claim 2, characterized in that: The device attribute information includes: non-uniform memory access NUMA node information; Analyze the device attribute information to determine the core features, including: Determine a second feature according to the NUMA node information; the second feature includes: The number of NUMA nodes, the number of processor cores contained in each NUMA node, and the distribution of processor cores in each NUMA node.

6. The method according to claim 2, characterized in that The analyzing the cache attribute information and / or the device attribute information to determine cache characteristics and / or core characteristics includes: Analyze the cache attribute information and / or the device attribute information to determine a third feature; the third feature includes: The cache size corresponding to each processor core in each cache level; Cache write policies supported by caches at all levels; Whether the NUMA node supports hyperthreading technology.

7. The method according to claim 5, characterized in that The analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The second feature is analyzed based on the first rule to determine first structural information, where the first structural information includes: the number of processor groups CCXs of the NUMA node, and the number of processor cores of each CCX.

8. The method according to claim 2, characterized in that: Analyzing the cache characteristics and / or core characteristics to obtain chip structure information includes: The cache feature and / or core feature is analyzed based on the first rule to determine second structure information, where the second structure information includes: a situation where the cache is shared between processor cores.

9. The method according to claim 1, characterized in that: Constructing a chip structure diagram according to the chip structure information includes: A chip structure diagram is constructed according to the chip structure information using a drawing model.

10. The method according to claim 9, characterized in that The method further comprises: Acquire a training data set; the training data set includes at least one sample chip structure information and a logical architecture diagram of the sample chip structure corresponding to each sample chip structure information; A preset neural network model is trained according to the training data set to obtain a trained neural network model as the drawing model.

11. The method according to claim 1, characterized in that: The obtaining of cache attribute information and / or device attribute information includes: At least one query instruction is called by using a test tool, and cache attribute information and / or device attribute information of the electronic device is obtained according to the query instruction.

12. A chip structure determination device, characterized in that: The device is applied to electronic equipment, and the device comprises: An acquisition module, used to acquire cache attribute information and / or device attribute information; A first processing module, configured to determine chip structure information according to the cache attribute information and / or device attribute information; The second processing module is used to construct a chip structure diagram according to the chip structure information.

13. The device according to claim 12, characterized in that The acquisition module is used to call at least one query instruction using a test tool, and obtain cache attribute information and / or device attribute information of the electronic device according to the query instruction; The second processing module is used to construct a chip structure diagram according to the chip structure information by using a drawing model.

14. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 11.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1 to 11.

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