Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a partition region; forming a groove located in the substrate, and enabling the partition region to be located in the groove; a barrier layer protruding in the groove is formed, and the barrier layer covers the partition area and divides the space of the groove in the extending direction of the groove; forming a channel material layer in the residual space of the groove; and patterning the channel material layer, forming the fin part, and covering the end part, facing the partition region, of the fin part along the extension direction of the fin part by the barrier layer, so that the fin part cannot be formed in the partition region, the lattice strain relaxation problem of the fin part formed by the channel material can be inhibited, and the performance of the device is improved. Therefore, the stress of the fin part formed by the channel material is improved, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of traditional planar metal-oxide-semiconductor field-effect transistors (MOSFETs) has also been shortened. The distance between the source and drain of the device has also been shortened, so the gate structure's ability to control the channel has deteriorated, and it has become increasingly difficult for the gate voltage to pinch off the channel, making subthreshold leakage, the so-called short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to reduce the impact of the short channel effect, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as Fin Field-Effect Transistor (FinFET). In FinFET, the gate structure is a three-dimensional fin structure. Compared with planar MOSFET, this structure increases the control area of ​​the channel, greatly enhancing the gate's control over the channel, thereby effectively suppressing the short channel effect; and FinFET has better compatibility with existing integrated circuit manufacturing than other devices.

[0004] In addition, in the semiconductor field, according to process requirements, it is usually necessary to cut the fins of a partial area. For example, a current practice is to cut the fins of a partial area through a single diffusion block (SDB) process. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, the substrate including a partition region; a fin, located on the substrate, and the fin is located on both sides of the partition region along its extension direction; and a barrier layer, located on the end of the fin facing the partition region.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a partition region; forming a groove located in the substrate, and making the partition region located in the groove; forming a barrier layer protruding in the groove, the barrier layer covering the partition region and dividing the space of the groove in the extension direction of the groove; forming a channel material layer in the remaining space of the groove; patterning the channel material layer to form a fin, and along the extension direction of the fin, the end of the fin facing the partition region is covered by the barrier layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a semiconductor structure, in which a fin is located on both sides of a partition area along its extension direction, and a barrier layer is located on the end of the fin facing the partition area. The embodiment of the present invention implements the partition of the fin through the barrier layer. Since the reliability of the partition implemented by the barrier layer is higher and the barrier layer can protect the end of the fin, the quality and performance of the fin are guaranteed, thereby improving the performance of the semiconductor structure.

[0010] An embodiment of the present invention provides a method for forming a semiconductor structure, forming a groove located in the substrate, and making the partition area located in the groove, and also forming a barrier layer protruding in the groove, the barrier layer covers the partition area and divides the space of the groove in the extension direction of the groove, so that after the fin is formed, the end of the fin facing the partition area is covered by the barrier layer, and the fin will not be formed in the partition area. Under the action of the barrier layer located at the end of the fin, isolation can be achieved between adjacent fins in the extension direction of the fin, which is conducive to suppressing the lattice strain relaxation problem of the fin formed by the channel material, thereby increasing the stress of the fin formed by the channel material, and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 to Figure 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 3 to Figure 4 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure;

[0013] Figure 5 to Figure 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0014] Figures 7 to 11 is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention;

[0015] Figures 12 to 15 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention;

[0016] Figures 16 to 18 It is a schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0017] At present, the performance of semiconductor structures needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.

[0018] Figure 1 to Figure 2 The present invention is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure. Specifically, Figure 1 and Figure 2 This is a top view.

[0019] refer to Figure 1 A substrate 10 is provided, the substrate 10 includes a partition region 18, and a fin portion 19 protrudes from the substrate 10. For example, the partition region 18 is a fin cut region.

[0020] refer to Figure 2 , the fin 19 on the partition area 18 is removed.

[0021] Figure 3 to Figure 4 is a schematic diagram of the structures corresponding to the steps in another method for forming a semiconductor structure. Specifically, Figure 3 and Figure 4 This is a top view.

[0022] refer to Figure 3 A substrate 20 is provided, the substrate 20 includes a partition region 21 , a fin 28 protrudes from the substrate 20 , and a metal gate 29 is formed on the substrate 20 and crosses the fin 28 , and the metal gate 29 covers a portion of the top and a portion of the sidewall of the fin 28 .

[0023] For example, the isolation region 21 is a single diffusion isolation region.

[0024] refer to Figure 4 , the metal gate 29 and the fin 28 of the isolation region 21 are removed.

[0025] Research has found that the current mainstream method of cutting fins occurs on the fins in the isolation area, that is, the fins are the objects to be etched. This leads to the problem of lattice strain relaxation in the remaining fins close to the cutting area after the fins are cut, which reduces the stress of the fins, thereby reducing the mobility of carriers and reducing the performance of the semiconductor structure.

[0026] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a partition region; forming a groove located in the substrate, and making the partition region located in the groove; forming a barrier layer protruding in the groove, the barrier layer covering the partition region and dividing the space of the groove in the extension direction of the groove; forming a channel material layer in the remaining space of the groove; patterning the channel material layer to form a fin, and along the extension direction of the fin, the end of the fin facing the partition region is covered by the barrier layer.

[0027] In the scheme disclosed in the embodiment of the present invention, the fin will not be formed in the isolation area. Under the action of the barrier layer located at the end of the fin, the fin can be prevented from being affected by the etching operation performed in the isolation area (for example, when a cutting process is required in the isolation area). The cutting process occurs on the barrier layer, which can correspondingly suppress the lattice strain relaxation of the fin, thereby improving the performance of the semiconductor structure.

[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 5 and Figure 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention, Figure 5 is a top view, where Figure 6 yes Figure 5 Cross-section along direction AA1.

[0030] The semiconductor structure includes: a substrate 200 including a partition region 200A; a fin 219 located on the substrate 200 and located on both sides of the partition region 200A along its extension direction; and a barrier layer 202 located on the end of the fin 219 facing the partition region 200A.

[0031] In this embodiment, a barrier layer 202 is formed on the side of the partition region 200A of the substrate 200 so that the barrier layer 202 covers the end of the fin 219 facing the partition region 200A. The fin 219 is not formed in the partition region 200A, and the partition of the fin 219 is achieved by the barrier layer 202. The reliability of the partition achieved by the barrier layer 202 is higher, and the barrier layer 202 can protect the end of the fin 219 (for example, the barrier layer 202 can suppress the lattice stress relaxation of the fin 219), so that the quality and performance of the fin 219 are guaranteed, thereby improving the performance of the semiconductor structure.

[0032] Specifically, in the formation process of the semiconductor structure, the barrier layer 202 can protect the end of the fin 219. Under the action of the barrier layer 202 located at the end of the fin 219, the fin 219 can be prevented from being affected by the etching operation performed in the partition area 200A (for example, when a cutting process is required in the partition area 200A, the cutting process occurs on the barrier layer 202 at the end of the fin 219), thereby suppressing the relaxation of the material lattice stress of the fin 219, thereby improving the performance of the semiconductor structure.

[0033] The substrate 200 is used to provide a process platform for forming a semiconductor structure.

[0034] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0035] In this example, the substrate 200 includes a partition region 200A. The partition region 200A refers to a region where a fin is not required to be formed, that is, a region for defining the fin 219 to be isolated in its extension direction.

[0036] The isolation region 200A includes one or both of a fin cut region and a single diffusion isolation region.

[0037] Here, the fin cut area refers to: the area where the fin is divided in its extension direction after the fin is formed; the single diffusion isolation area refers to: after the gate structure (for example, a metal gate structure) is formed, the specific gate structure and the area of ​​the fin at the bottom of the gate structure are removed.

[0038] In this embodiment, the substrate 200 includes a PMOS region 200B, and the PMOS region 200B has a partition region 200A. The PMOS region 200B is used to form a PMOS transistor.

[0039] It should be noted that the substrate 200 may also include an NMOS region 200C, where the NMOS region is used to form an NMOS transistor. Accordingly, the isolation region may also be located in the NMOS region.

[0040] In this embodiment, the semiconductor structure is a fin field effect transistor, and the discrete fins 219 on the substrate 200 are used to provide a channel of the fin field effect transistor.

[0041] In this embodiment, the fin 219 is located on the substrate 200 , and the fin 219 is located on both sides of the partition region 200A along the extension direction thereof, so the fin 219 is not formed in the partition region 200A.

[0042] The material of the fin 219 includes one or more of silicon, silicon germanium, germanium and III-V group semiconductor materials. The material of the fin 219 is determined according to the channel conductivity type and performance requirements of the transistor.

[0043] In this embodiment, the material of the fin 219 in the PMOS region 200B includes silicon germanium.

[0044] Specifically, the fin 219 in the PMOS region 200B includes the bottom fin 207 (eg, Figure 6 As shown), and a channel material layer 203 located on the bottom fin 207, the bottom fin 207 and the substrate 200 are an integral structure, the channel material layer 203 is epitaxially grown on the bottom fin 207, and the material of the channel material layer 203 is germanium silicon.

[0045] In this embodiment, the substrate 200 may further include an NMOS region, and the material of the fin 219 located in the NMOS region is silicon.

[0046] The barrier layer 202 is located on the end of the fin 219 facing the partition region 200A. The barrier layer 202 can protect the end of the fin 219 and suppress the lattice stress relaxation problem of the fin 219 to increase the stress of the fin 219 .

[0047] In this embodiment, the top of the barrier layer 202 is flush with the top of the fin 219 .

[0048] The material of the barrier layer 202 includes silicon or a material with a lattice constant greater than that of silicon. For example, the material with a lattice constant greater than that of silicon may include gallium arsenide, indium arsenide, gallium antimonide, and indium antimonide.

[0049] Specifically, the material of the barrier layer is silicon or a material with a lattice constant greater than that of silicon. When the fin cutting process occurs, the lattice of the barrier material layer will generate compressive stress on the lattice of the fin material, thereby inhibiting the relaxation of the fin lattice stress.

[0050] As an example, the material of the barrier layer 202 is silicon.

[0051] In this embodiment, the barrier layer 202 and the substrate 200 are an integrated structure.

[0052] Specifically, when the fin cutting process occurs, since the barrier layer 202 and the substrate 200 are an integrated structure, that is, the material lattice constant of the barrier layer 202 is consistent with the material lattice constant of the substrate 200, the lattice expansion of the fin 219 can be prevented, thereby suppressing the lattice stress relaxation of the fin 219. Moreover, using the material of the substrate 200 to prepare the barrier layer 202 is also conducive to reducing costs.

[0053] In other embodiments, the barrier layer and the substrate may not be an integral structure, and the barrier layer and the substrate may be made of different materials.

[0054] In this embodiment, the barrier layer 202 is located in the PMOS region 200B and on the end of the fin 219 facing the isolation region 200A.

[0055] Specifically, since the fin 219 of the PMOS region 200B includes the bottom 207, the bottom fin 207, and the channel material layer 203 located on the bottom fin 207, the channel material layer 203 is a germanium silicon material, which is used to increase the rate of hole migration in the fin field effect transistor. When the fin cutting process occurs, if the germanium silicon is directly etched, it is easy to cause lattice stress relaxation of the germanium silicon. Therefore, the barrier layer 202 is located in the PMOS region 200B, which can suppress the lattice stress relaxation of the germanium silicon, thereby improving the hole mobility.

[0056] In this embodiment, in the extension direction of the fins 219 , the barrier layer 202 is located at the side of the partition region 200A to ensure that adjacent fins 219 are completely isolated.

[0057] Moreover, the barrier layer 202 is located on the side of the partition area 200A, which means that the barrier layer 202 occupies the effective length of the fin 219. When the fin cutting process occurs, it is ensured that the barrier layer 202 in the partition area 200A is etched instead of the fin 219, and it is ensured that the end of the fin 219 is covered with the remaining barrier layer 202. The lattice of the remaining barrier layer 202 material will continue to squeeze the lattice of the fin 219, maintain stress, and inhibit the relaxation of the fin lattice stress, thereby improving the performance of the semiconductor structure.

[0058] It should be noted that the width W of the barrier layer 202 at the end of the fin 219 should not be too large or too small. The barrier layer 202 is located on the side of the partition region 200A, which means that the barrier layer 202 occupies the effective length of the fin 219. If the width W of the barrier layer 202 is too large, it is easy to cause the effective length of the fin 219 to be too small, and the barrier layer 202 is easy to inhibit the epitaxial growth of the subsequent source and drain doping layer formed in the fin 219, thereby affecting the performance of the semiconductor structure; if the width W of the barrier layer 202 is too small, it is easy to cause the barrier layer 202 on the end of the fin 219 to suppress the stress release of the fin 219. The effect is poor (for example, the barrier layer 202 is easily removed during the segmentation process of the partition region 200A, that is, it is easy to cause the end of the fin 219 to have no barrier layer 202, and the stress release of the fin 219 cannot be suppressed), thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, the width W of the barrier layer 202 at the end of the fin 219 is greater than or equal to 5 nm and less than or equal to the contacted poly pitch (CPP).

[0059] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 7 to 11is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention, Figures 7 to 11 It is a top view.

[0060] refer to Figure 7 , providing a substrate 200, the substrate 200 includes a partition area 200A.

[0061] The substrate 200 provides a process platform for subsequent process steps.

[0062] Specifically, the substrate 200 is used to form a fin.

[0063] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0064] In this example, the substrate 200 includes a partition region 200A. The partition region 200A refers to a region where a fin is not required to be formed, that is, a region for defining the fin 219 to be isolated in its extension direction.

[0065] The isolation region 200A includes one or both of a fin cut region and a single diffusion isolation region.

[0066] Here, the fin cut area refers to: the area where the fin is divided in its extension direction after the fin is formed; the single diffusion isolation area refers to: after the gate structure (for example, a metal gate structure) is formed, the specific gate structure and the area of ​​the fin at the bottom of the gate structure are removed.

[0067] The substrate 200 includes a PMOS region 200B, wherein the PMOS region 200B has a partition region 200A, wherein the PMOS region 200B is used to form a PMOS transistor.

[0068] It should be noted that the substrate 200 may also include an NMOS region 200C, which is used to form an NMOS transistor. Accordingly, the isolation region may also be located in the NMOS region 200C. In this embodiment, for the convenience of illustration, the isolation region 200A in the NMOS region 200C is not illustrated.

[0069] refer to Figure 8 and Fig. 9 , forming a groove 201 located in the substrate 200, and making the partition area 200A located in the groove 201; forming a barrier layer 202 protruding in the groove 201, the barrier layer 202 covers the partition area 200A, and divides the space of the groove 201 in the extension direction of the groove 201.

[0070] The groove 201 is used to provide a spatial location for the subsequent formation of a channel material layer.

[0071] In the present embodiment, in the step of forming the trench 201 in the substrate 200 , the trench 201 is formed in the substrate 200 in the PMOS region 200B.

[0072] A trench 201 is formed in the substrate 200 of the PMOS region 200B so as to subsequently form a channel material layer (eg, silicon germanium material) that can meet the performance requirements of the PMOS transistor.

[0073] It should be noted that before forming the channel material layer, a barrier layer 202 is first formed, and the subsequent channel material layer is automatically divided by the barrier layer 202. Correspondingly, after the channel material layer is subsequently patterned to form a fin, the end of the fin toward the isolation area is covered by the barrier layer 202 along the extension direction of the fin.

[0074] Among them, by forming a barrier layer 202 in the partition area 200A of the substrate 200, the barrier layer 202 covers the end of the fin facing the partition area 200A, and the fin will not be formed in the partition area 200A. The barrier layer 202 can protect the end of the fin. Under the action of the barrier layer 202 located at the end of the fin, the isolation of adjacent fins can be achieved in the extension direction of the fin, which is beneficial to suppress the lattice stress relaxation of the channel material layer 203 forming the fin, thereby improving the performance of the semiconductor structure.

[0075] In a specific embodiment, the fin can be prevented from being affected by the etching operation performed in the partition area 200A (for example, when a cutting process is required in the partition area 200A, the cutting process occurs on the barrier layer 202 at the end of the fin), thereby facilitating the suppression of lattice stress relaxation of the channel material layer 203 forming the fin.

[0076] The material of the barrier layer 202 includes silicon or a material having a lattice constant greater than that of silicon.

[0077] Specifically, the material of the barrier layer is silicon or a material with a lattice constant greater than that of silicon. When the fin cutting process occurs, the lattice of the barrier material layer will generate compressive stress on the lattice of the fin material, thereby inhibiting the relaxation of the fin lattice stress.

[0078] As an example, the material of the barrier layer 202 is silicon.

[0079] In this embodiment, the barrier layer 202 is formed in the PMOS region 200B.

[0080] Specifically, since the fin 219 of the PMOS region 200B includes a bottom fin 207 and a channel material layer 203 located on the bottom fin 207, the channel material layer 203 is a germanium silicon material, which is used to increase the rate of hole migration in the fin field effect transistor. When the fin cutting process occurs, if the germanium silicon is directly etched, it is easy to cause lattice stress relaxation of the germanium silicon. Therefore, the barrier layer 202 is located in the PMOS region 200B, which can suppress the lattice stress relaxation of the germanium silicon, thereby improving the hole mobility.

[0081] Since the channel material is germanium silicon material, it is used to increase the rate of hole migration in the fin field effect transistor. When the fin cutting process occurs, the barrier layer is located in the PMOS region, which can suppress the relaxation of the lattice stress of the fin, thereby improving the hole mobility.

[0082] In this embodiment, in the extension direction of the groove 201, the length of the barrier layer 202 is greater than the length L1 of the partition region 200A (eg Figure 7 That is to say, along the extension direction of the barrier layer 202, both sides of the barrier layer 202 exceed the boundary of the partition area 200A.

[0083] Specifically, the barrier layer 202 is located on the side of the partition area 200A, which means that the barrier layer 202 occupies the effective length of the fin 219. When the fin cutting process occurs, it is ensured that the barrier layer 202 in the partition area 200A is etched instead of the fin 219, and it is ensured that the end of the fin 219 is covered with the remaining barrier layer 202. The lattice of the remaining barrier layer 202 material will continue to squeeze the lattice of the fin, maintain stress, and inhibit the relaxation of the fin lattice stress, thereby improving the performance of the semiconductor structure.

[0084] It should be noted that the length of the barrier layer 202 extending beyond the partition area 200A on one side should not be too small or too large. The barrier layer 202 is located on the side of the partition area 200A, which means that the barrier layer 202 will occupy the effective length of the fin 219. Therefore, if the barrier layer 202 exceeds the partition area 200A on one side by too much, it is easy to cause the effective length of the fin 219 to be too short, and the barrier layer 202 is easy to inhibit the epitaxial growth of the subsequent source and drain doping layer when it is formed in the fin 219, thereby affecting the performance of the semiconductor structure; if the barrier layer 202 exceeds the partition area 200A on one side by too little, then when the barrier layer 202 is subsequently divided and a portion of the width of the remaining barrier layer 202 is retained at the end of the fin 219, it is easy to cause the remaining barrier layer 202 to suppress the stress release of the fin 219. The effect is poor (for example, the barrier layer 202 is easily removed during the division process of the partition area 200A, that is, it is easy to cause the end of the fin 219 to have no barrier layer 202, and the stress release of the fin 219 cannot be suppressed), thereby affecting the performance of the semiconductor structure. To this end, in this example, the length of the barrier layer 202 extending beyond the isolation region 200A on one side is greater than or equal to 5 nm and less than or equal to the contact gate spacing.

[0085] In this embodiment, the top of the barrier layer 202 is flush with the top of the substrate 200 outside the trench 201 .

[0086] In this embodiment, the height of the barrier layer 202 is greater than or equal to a preset effective fin height. Here, the preset effective fin height refers to: the height of the fin 219 covered by the gate structure.

[0087] The effective fin refers to the portion of the fin 219 covered by the gate structure. The effective fin is used to provide a channel for the device. The quality of the effective fin has a great influence on the performance of the device. To this end, the height of the barrier layer 202 is made greater than or equal to the preset effective fin height to ensure that the barrier layer 202 covers the end of the effective fin, thereby effectively suppressing the stress release of the effective fin.

[0088] In this embodiment, during the step of forming the trench 201 , the barrier layer 202 is formed simultaneously.

[0089] On the one hand, this is beneficial to simplify the process steps; on the other hand, this makes the barrier layer 202 and the substrate 200 an integrated structure.

[0090] Specifically, when the fin cutting process occurs, since the barrier layer 202 and the substrate 200 are an integrated structure, that is, the lattice constant of the barrier layer 202 material is consistent with the lattice constant of the substrate 200, the lattice expansion of the fin 219 covered by the barrier layer 202 can be prevented, thereby suppressing the relaxation of the lattice stress of the fin 219.

[0091] Therefore, in this embodiment, the step of forming the groove 201 and the barrier layer 202 includes: forming the groove 201 in the substrate 200 around the partition area 200A, and the remaining substrate 200 protruding from the groove 201 serves as the barrier layer 202 .

[0092] The steps of forming the trench 201 and the barrier layer 202 are described in detail below with reference to the accompanying drawings.

[0093] The steps of forming the trench 201 and the barrier layer 202 include: Figure 8 As shown, a mask layer 205 is formed on the substrate 200 in the partition region 200A; Fig. 9 As shown, the mask layer 205 is used as a mask to pattern the substrate 200 around the mask layer 205 to form a groove 201 , and the remaining substrate 200 protruding from the groove 201 serves as a blocking layer 202 .

[0094] In this embodiment, the process of forming the trench 201 includes a dry etching process.

[0095] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic characteristics, so its longitudinal etching rate is much greater than the lateral etching rate, which is conducive to accurately removing the substrate 200 around the partition area 200A, thereby improving the morphology quality and dimensional accuracy of the barrier layer 202.

[0096] It should be noted that the mask layer 205 also covers the substrate 200 in the NMOS region, so that the trench 201 is formed only in the PMOS region 200B.

[0097] It should also be noted that, in order to save masks, the same mask is used to form the mask layer 205 located in the partition area 200A and the mask layer 205 located in the NMOS area. In other embodiments, different masks can also be used to form the mask layer located in the partition area and the mask layer located in the NMOS area respectively.

[0098] refer to Fig.10 , a channel material layer 203 is formed in the remaining space of the trench 201 .

[0099] The channel material layer 203 is then patterned to form a fin.

[0100] The material of the channel material layer 203 includes one or more of silicon, silicon germanium, germanium and III-V group semiconductor materials. The material of the channel material layer 203 is determined according to the channel conductivity type and performance requirements of the transistor.

[0101] In this embodiment, the trench 201 is formed in the PMOS region 200B, and therefore, the material of the channel material layer 203 is germanium silicon material.

[0102] In this embodiment, the process of forming the channel material layer 203 includes an epitaxial process.

[0103] The epitaxial process has the characteristics of low cost and simple process, and can grow in a specific area and has the characteristics of regional selectivity. Moreover, the channel material layer 203 grown by the epitaxial process has high quality.

[0104] In this embodiment, after the channel material layer 203 is formed in the remaining space of the trench 201 , the method further includes: performing a planarization process on the channel material layer 203 so that the top surface of the channel material layer 203 is flush with the top surface of the barrier layer 202 .

[0105] The planarization process is helpful to improve the reliability of the subsequent graphic process.

[0106] The process of planarizing the channel material layer 203 includes a chemical mechanical polishing process.

[0107] The chemical mechanical polishing process can reduce the undulations on the surface of the material, improve the reliability, speed and yield of the device, and has the characteristics of improving the step coverage of the material and removing the surface defects of the material. Therefore, a relatively flat surface can be obtained, which is composed of the top surface of the channel material layer 203 and the barrier layer 202, and the probability of damage to the surface is low.

[0108] refer to Fig.11 , the channel material layer 203 is patterned to form a fin 219 , and along the extension direction of the fin 219 , the end of the fin 219 facing the partition region 200A is covered by the barrier layer 202 .

[0109] In this embodiment, the method is used to form a fin field effect transistor, and the fin 219 is used to provide a channel of the fin field effect transistor.

[0110] After the fin 219 is formed, the end of the fin 219 facing the partition area 200A is covered by the barrier layer 202, and the fin 219 will not be formed in the partition area 200A. Under the action of the barrier layer 202 located at the end of the fin 219, the fin 219 can be prevented from being affected by the etching operation performed in the partition area 200A, which is beneficial to suppressing the lattice strain relaxation problem of the fin 219 formed by the channel material 203, thereby increasing the stress of the fin 219 formed by the channel material 203, and further improving the performance of the semiconductor structure.

[0111] In this embodiment, in the step of patterning the channel material layer 203 , the barrier layer 202 is also patterned to retain the barrier layer 202 between the ends of adjacent fins 219 .

[0112] In this embodiment, in the step of patterning the channel material layer 203, the substrate 200 of the NMOS region 200C is also patterned, so as to form the fin 219 in the NMOS region 200C. Fig.11 In FIG. 1 , the fin 219 in the NMOS region 200C is not labeled.

[0113] In this embodiment, the fin 219 formed in the PMOS region 200B includes a bottom fin 207 and a channel material layer 203 located on the bottom fin 207. The material of the channel material layer 203 is silicon germanium. The material of the fin 219 formed in the NMOS region 200C is silicon.

[0114] Fins 219 and barrier layers 202 are formed in the PMOS region 200B. The fins 219 of the PMOS region 200B are made of silicon germanium, and the barrier layers 202 are made of silicon. Silicon germanium as a channel of the PMOS device can improve the mobility of hole carriers, thereby improving the performance of the semiconductor device.

[0115] At the same time, the germanium silicon material is grown on the silicon substrate through an epitaxial process, and is also grown on the side of the barrier layer 202. From a microscopic point of view, the silicon atoms and the germanium atoms are chemically connected together at this time, and the lattice of the germanium atoms will be squeezed by the lattice of the silicon atoms; and the fin 219 cutting process occurs on the barrier layer. After cutting, a residual barrier layer 202 of a certain width will be retained at the edge of the fin 219. From a microscopic point of view, the lattice of the silicon atoms in the barrier layer 202 will still maintain the squeezing of the lattice of the germanium atoms, thereby suppressing the stress relaxation of the lattice of the fin 219.

[0116] It should be noted that the forming method further includes: dividing the barrier layer 202, and leaving a portion of the width of the remaining barrier layer 202 at the end of the fin 219 (eg Figure 5 and Figure 6 shown).

[0117] The barrier layer 202 is divided so that the fins 219 can be better isolated from each other.

[0118] It should be noted that the substrate 200 further includes an NMOS region 200C, and therefore, the fins 219 of the isolation region may also be divided in the NMOS region 200C.

[0119] As an example, the partition region 200A is a fin cut region, and after the fin portion 219 is formed, a fin cut process is performed in the partition region 200A, so as to divide the barrier layer 202 .

[0120] In other embodiments, the partition region may also be a single diffusion partition region. Then, before the barrier layer is segmented, the method further includes: forming a gate structure (e.g., a metal gate structure) across the fin on the substrate. Accordingly, the step of segmenting the barrier layer includes: etching the gate structure covering the partition region and the barrier layer at the bottom of the gate structure to form a single diffusion partition groove. Accordingly, after the single diffusion partition groove is formed, the method further includes: forming a single diffusion partition structure in the single diffusion partition groove.

[0121] Figures 12 to 15 is a schematic structural diagram corresponding to each step in the second embodiment of the method for forming a semiconductor structure of the present invention, Figures 12 to 15 It is a top view.

[0122] The similarities between this embodiment and the first embodiment are not repeated here. The difference between this embodiment and the first embodiment is that: Fig.13 After that, a trench 301 is formed in the substrate 300 around the barrier layer 302 (as shown in FIG. Fig.15 shown).

[0123] refer to Figure 12 to Figure 13 , forming a groove 306 in the substrate 300 located in the partition area 300A; filling the groove 306 with a material of the barrier layer to form a barrier layer 30 covering the partition area 300A.

[0124] A groove 306 is formed in the substrate 300 of the partition area 300A to provide a space for the subsequent formation of the barrier layer 302 so as to fill the barrier layer 302 with material and to more flexibly select a suitable barrier layer 302 material according to the requirements.

[0125] The material of the barrier layer 302 includes silicon or a material having a lattice constant greater than that of silicon.

[0126] In this embodiment, along the width direction of the groove 306, the width of the groove 306 is greater than the length L3 of the partition region 300A, so that the width L4 of the barrier layer 302 is greater than the length L3 of the partition region 300A. In other words, along the width direction of the groove 306, the sidewalls on both sides of the groove 306 exceed the boundary of the partition region 300A.

[0127] Specifically, the steps of forming the groove 306 include: Fig.12 As shown, a first mask layer 305 is formed on the substrate 300 around the partition area 300A; using the first mask layer 305 as a mask, the substrate 300 of the partition area 300A is etched to form a groove 306 in the substrate 300 of the partition area 300A.

[0128] In this embodiment, the process of forming the groove 306 includes a dry etching process.

[0129] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic characteristics, so its longitudinal etching rate is much greater than the lateral etching rate, which is conducive to accurately removing the substrate 300 of the partition area 300A, thereby improving the dimensional accuracy of the groove.

[0130] In this embodiment, after the groove 306 is formed, the first mask layer 305 is removed to facilitate subsequent filling with the material of the barrier layer 302 .

[0131] In this embodiment, the process of filling the barrier layer 302 in the groove 306 includes an epitaxial process, a high-density plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process or a fluid chemical vapor deposition process.

[0132] The material of the barrier layer 302 is filled by an epitaxial process, so that the barrier layer 302 forms a structure with the substrate 300, so the barrier layer 302 will generate stress on the substrate 300. When the fin cutting process occurs, the cutting process occurs on the barrier layer 302. Since the barrier layer 302 generates stress on the substrate 300, the lattice of the barrier layer 302 material will continue to squeeze the lattice of the fin after cutting, maintain the stress, and inhibit the relaxation of the stress of the fin lattice.

[0133] It should be noted that after the barrier layer 302 material is filled in the groove 306 , the process may further include: performing a planarization process on the barrier layer 302 material to remove the barrier layer 302 material above the top of the substrate 300 .

[0134] refer to Fig.14 and Fig.15 After forming the barrier layer 302 , a groove 301 is formed in the substrate 300 around the barrier layer 302 , and the barrier layer 302 protrudes in the groove 301 .

[0135] The groove 301 is used to provide a spatial location for the subsequent formation of a channel material layer.

[0136] Specifically, the step of forming the trench 301 includes: forming a second mask layer 307 (eg, Fig.14 As shown in FIG. 1 , a mask opening (not shown) is formed in the second mask layer 307 on the substrate 300 around the barrier layer 302; the substrate 300 is etched along the mask opening using the second mask layer 307 as a mask to form a groove 301 (as shown in FIG. 1 ) in the substrate 300 around the barrier layer 302. Fig.15 shown).

[0137] In this embodiment, after the trench 301 is formed, the second mask layer 307 is removed to prepare for forming a channel filling material layer.

[0138] It should be noted that, in order to reduce damage to the barrier layer 302 , the second mask layer 307 may cover the barrier layer 302 , or, in order to increase the process window for forming the mask opening, the second mask layer may also expose the barrier layer 302 .

[0139] Figures 16 to 18 is a schematic structural diagram corresponding to each step in the third embodiment of the method for forming a semiconductor structure of the present invention, Figures 16 to 18 It is a top view.

[0140] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the method of forming the barrier layer is different.

[0141] refer to Fig.16 , forming a trench 501 in the substrate 500 , and positioning the partition region 500A in the trench 501 .

[0142] The groove 501 is used to provide a spatial location for the subsequent formation of a channel material layer.

[0143] It should be noted that before forming the barrier layer, the groove 501 is formed first, and then the subsequent barrier material layer 503 is filled into the groove 501. The barrier material layer 503 is patterned to form a barrier layer 502, and then the subsequent barrier layer 502 protrudes in the groove and divides the groove 501. Correspondingly, the channel material subsequently filled in the groove 501 will also be divided by the barrier layer.

[0144] Forming the trench 501 first and then filling the barrier material layer 503 in the trench 501 is beneficial to increasing the process window for filling the barrier material layer 503 and improving the filling quality of the barrier material layer 503 .

[0145] In the present embodiment, in the step of forming the trench 501 in the substrate 500 , the trench 501 is formed in the substrate 500 in the PMOS region 500B.

[0146] refer to Fig.17 , a barrier material layer 503 is filled in the trench 501 .

[0147] The barrier layer 502 is formed by filling the barrier material layer 503 in the trench 501 and then patterning the barrier material layer 503 .

[0148] In this embodiment, the process of filling the barrier material layer 503 in the trench 501 includes an epitaxial process, a high-density plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process or a fluid chemical vapor deposition process.

[0149] The barrier material layer 503 is filled by an epitaxial process, so that the barrier layer 502 forms a structure with the substrate 500, so the barrier layer 502 will generate stress on the substrate 500. When the fin cutting process occurs, the cutting process occurs on the barrier layer 502. Since the barrier layer 502 generates stress on the substrate 500, the lattice of the barrier material layer 503 after cutting will continue to squeeze the lattice of the fin 519, maintain the stress, and inhibit the relaxation of the lattice stress of the fin 519.

[0150] It should be noted that after the barrier material layer 503 is filled in the trench 501 , the process may further include: performing a planarization process on the barrier material layer 503 to remove the barrier material layer 503 above the top of the substrate 500 .

[0151] refer to Fig.18 , patterning the blocking material layer 503 to form a blocking layer 502 covering the partition area 500A.

[0152] In this embodiment, the process of patterning the blocking material layer 503 includes a dry etching process.

[0153] The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has anisotropic characteristics, so its longitudinal etching rate is much greater than the lateral etching rate, which is beneficial to improving the morphology quality and dimensional accuracy of the barrier layer 502.

[0154] It should be noted that the semiconductor structure of the embodiment of the present invention may be formed by any of the formation methods of the aforementioned embodiments, or may be formed by other formation methods.

[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a partition region; A fin portion, located on the substrate, and the fin portion is located on both sides of the partition area along its extension direction; The barrier layer is located on the end of the fin facing the partition area.

2. The semiconductor structure according to claim 1, wherein: The barrier layer and the substrate are an integrated structure.

3. The semiconductor structure according to claim 1, wherein: The material of the barrier layer includes silicon or a material having a lattice constant greater than that of silicon.

4. The semiconductor structure according to claim 1, wherein: In an extending direction of the fin, the barrier layer is located at a side of the partition region.

5. The semiconductor structure according to claim 4, characterized in that In the extension direction of the fin, the width of the barrier layer at the end of the fin is greater than or equal to 5 nm and less than or equal to the contact gate spacing.

6. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The substrate comprises a PMOS region, wherein the PMOS region has a partition region; The barrier layer is located in the PMOS region and on the end of the fin facing the isolation region; The material of the fin located in the PMOS region includes silicon germanium.

7. The semiconductor structure according to any one of claims 1 to 5, characterized in that: The isolation region includes one or both of a fin cut region and a single diffusion isolation region.

8. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a partition region; forming a trench in the substrate and locating the partition region in the trench; forming a barrier layer protruding in the groove, wherein the barrier layer covers the partition area and divides the space of the groove in the extending direction of the groove; forming a channel material layer in the remaining space of the trench; The channel material layer is patterned to form a fin portion, and along an extension direction of the fin portion, an end portion of the fin portion facing the isolation region is covered by the barrier layer.

9. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the groove and the barrier layer includes: forming a groove in the substrate around the isolation area, and the remaining substrate protruding from the groove serves as a barrier layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the barrier layer comprises: forming a groove in the substrate of the partition area; filling the groove with a barrier material layer to form a barrier layer covering the partition area; After the barrier layer is formed, a groove is formed in the substrate around the barrier layer, and the barrier layer protrudes in the groove.

11. The method for forming a semiconductor structure according to claim 8, wherein: The step of forming the barrier layer includes: filling a barrier material layer in the groove; and patterning the barrier material layer to form a barrier layer covering the partition area.

12. The method for forming a semiconductor structure according to claim 10 or 11, characterized in that: The process of filling the barrier material layer includes an epitaxial process, a high-density plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process or a fluid chemical vapor deposition process.

13. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: In the extension direction of the groove, the length of the barrier layer is greater than the length of the partition region; The forming method further comprises: dividing the barrier layer, and leaving a portion of the width of the remaining barrier layer at the end of the fin.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming the barrier layer, the length of the barrier layer extending beyond the isolation region on one side is greater than or equal to 5 nm and less than or equal to the contact gate spacing.

15. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: The height of the barrier layer is greater than or equal to a preset effective fin height.

16. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: The process of forming the trench includes a dry etching process.

17. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: The material of the barrier layer includes silicon or a material having a lattice constant greater than that of silicon.

18. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: The process of forming the channel material layer includes an epitaxial process.

19. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: The forming method further includes: performing a planarization process on the channel material layer so that a top surface of the channel material layer is flush with a top surface of the barrier layer.

20. The method for forming a semiconductor structure according to any one of claims 8 to 11, characterized in that: In the step of providing a substrate, the substrate includes a PMOS region, and the PMOS region has a partition region; In the step of forming a trench in the substrate, a trench is formed in the substrate of the PMOS region.

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