Method of transferring patterned micro-LED die onto silicon carrier for wafer-to-wafer hybrid bonding to CMOS backplane

Abstract

Optoelectronic structures and methods of formation are described. In one embodiment, an optoelectronic structure includes a backplane having a driver circuit and an array of contact pads, and a device layer bonded to the backplane. The device layer may include an array of micro-diodes and landing pads and a reconfiguration wiring layer including an array of via contacts connected to the array of landing pads. The reconstitution wiring layer can be directly bonded to the array of contacts by metal-metal bonds. The placement profile of the landing array can be decoupled from the position profile of the via contact array.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to U.S. Patent Application No. 18 / 450,664, filed on August 16, 2023, and U.S. Provisional Application No. 63 / 376,039, filed on September 16, 2022, which are incorporated herein by reference. Background Art Technical Field

[0003] Embodiments described herein relate to optoelectronic structures. More particularly, embodiments relate to optoelectronic structures having micro-sized light emitting or sensing diodes.

[0004] Background Information

[0005] Prior art displays for portable electronic devices, computers, and televisions typically utilize glass substrates with thin film transistors (TFTs) to control the transmission of backlight through pixels based on liquid crystals. More recently, emissive displays, such as those based on organic light emitting diodes (OLEDs), have been introduced. More recently, it has been proposed to integrate micro-LEDs based on emissive inorganic semiconductors into displays. However, micro-LED integration may require mass transfer technology of micro-LEDs from growth substrates based on non-silicon materials such as sapphire, gallium nitride, etc. In one embodiment, it has been proposed to perform mass transfer using a transfer head array. In other embodiments, it has been proposed to perform mass transfer using wafer bonding technology. Summary of the invention

[0006] In one embodiment, an optoelectronic structure includes a backplane having a drive circuit and a contact pad array, and a device layer bonded to the backplane. The device layer may include a microdiode and a landing pad array, and an array of via contacts connected to the landing pad array. The via contact array may be part of a reconstructed wiring layer that is directly bonded to the backplane contact pad array via metal-metal bonds. The placement distribution of the landing pad array may be decoupled from the position distribution of the via contact array by a reconstructed process, wherein a reconstructed substrate is formed and then bonded to the backplane.

[0007] In one embodiment, a method of assembling optoelectronic structures includes: patterning a microdiode array into a pn diode layer on a growth substrate; forming a landing pad array on top of the microdiode array; transferring the microdiode array and the landing pad array to a first carrier substrate; cutting the microdiode array, the landing pad array, and the first carrier substrate into a plurality of sample blocks, each sample block including a microdiode sub-array and a landing pad sub-array; reconstructing the sample block array on a second carrier substrate to form a reconstructed substrate; hybrid bonding the reconstructed substrate to a backplane; and cutting a plurality of optoelectronic structures.

[0008] In one embodiment, the cut microdiode carrier substrate comprises a silicon or sapphire wafer, and the reconstructed substrate and the backplane each comprise a silicon wafer. Reconstructing the sample block array on the second carrier substrate may include die-to-wafer bonding of the sample block array to the second carrier substrate. Hybrid bonding of the reconstructed substrate to the backplane may include wafer-to-wafer bonding.

[0009] The optoelectronic structure and manufacturing method can overcome several challenges associated with bonding a high-density microdiode array to a backplane, including allowing high temperature processing of the microdiodes to be completed on a growth substrate, mitigating particle contamination during slicing by not cutting through the growth substrate, testing known good die, reducing coefficient of thermal expansion (CTE) risks during die-to-wafer bonding utilizing silicon-silicon systems, utilizing oversized landing pads to relax die-to-wafer alignment tolerances, and decoupling wafer-to-wafer bonding alignment from die-to-wafer bonding alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional side view illustration of a microdiode reconstruction and wafer-to-wafer bonding sequence according to an embodiment.

[0011] Figure 2 is a schematic top view illustration of an optoelectronic structure with misaligned coupons according to an embodiment.

[0012] Figure 3 is a schematic cross-sectional side view illustration of an optoelectronic structure according to an embodiment.

[0013] Figure 4A is a schematic cross-sectional side view illustration of an optoelectronic structure stack including a microdiode with a diffused sidewall passivation layer according to an embodiment.

[0014] FIG. 4B to FIG. 4C is a schematic cross-sectional side view illustration of an optoelectronic structure stack including a microdiode with a regrown sidewall passivation layer according to an embodiment.

[0015] Figure 5Ais a schematic cross-sectional side view illustration of an optoelectronic structure including a plurality of coupons according to an embodiment.

[0016] Figure 5B is a close-up schematic cross-sectional side view illustration of an optoelectronic structure including a single coupon according to an embodiment.

[0017] Figure 5C According to the implementation plan Figure 5B Schematic top view illustration of the top opaque electrode layer.

[0018] FIG. 6A to FIG. 6N is a cross-sectional side view illustration of a microdiode reconstruction and wafer-to-wafer bonding sequence according to an embodiment.

[0019] FIG. 7A to FIG. 7L is a cross-sectional side view illustration of a microdiode reconstruction and wafer-to-wafer bonding sequence according to an embodiment. DETAILED DESCRIPTION

[0020] Embodiments describe optoelectronic structures and manufacturing methods in which high-density microdiodes (such as microLEDs or photodetectors) can be bonded to substrates, such as complementary metal-oxide-semiconductor (CMOS) substrates or substrates including pixel driver chip arrays, at high pixel density and landing pad spacing. For example, embodiments can be used to produce pixel densities greater than 5,000ppi and backplane landing pad spacings of 5μm or less. This can be achieved using a reconstruction process in which a microLED array from a growth substrate is transferred to a synthetic silicon carrier wafer and reconstructed to form via contacts as part of a reconstructed wiring layer, followed by wafer-to-wafer bonding to a CMOS substrate (or a substrate including a pixel driver chip array), and finally cutting the optoelectronic structure. In addition, embodiments can overcome several challenges involved in various bonding processes, including wafer size mismatch, bonding stress induced by coefficient of thermal expansion (CTE) mismatch, yield reduction due to cutting particles, yield reduction due to bonding misalignment, and thermal budget.

[0021] As used herein, the term "micro diode" or "micro LED" may refer to the maximum lateral dimension of the device. In some embodiments, the "micro" type diode may have a maximum lateral dimension of less than 100 μm, such as less than 10 μm, such as 5 μm, 0.5 μm or less. In a specific embodiment, the maximum lateral dimension of the micro LED is 1 μm. The processing sequence according to the embodiment can be used to form both monochrome and full-color optoelectronic structures such as displays and sensors.

[0022] In an exemplary embodiment, an optoelectronic structure and process flow for reconstructing a sample block (or die) of a patterned array of micro LED devices onto a synthetic 300mm silicon carrier to prepare these dies for 300mm copper inlay processing and 300mm wafer-to-wafer hybrid bonding to a CMOS backplane wafer is described. Such a process flow can allow very high temperature sidewall passivation processes to be performed on the initial LED growth substrate, relax the standards for die-to-wafer bonding placement accuracy, and have a higher product yield due to the use of mature 300mm wafer copper inlays and 300mm wafer-to-wafer bonding to a CMOS backplane wafer to create the final electrical connection to the micro LED device. Although the embodiments described herein are made with respect to micro LED devices, it should be understood that the embodiments are also applicable to other devices such as, for example, photodetectors for sensor arrays. In addition, although the embodiments are described with respect to a 300mm wafer process, this is exemplary for prior art silicon processing facilities, and the embodiments are not limited thereto. Additionally, while embodiments are described with respect to a silicon CMOS backplane wafer, it will be appreciated that alternative backplane structures may be utilized, such as a backplane substrate including an embedded array of silicon pixel driver chips and electrical wiring that supports similar functionality as a monolithic silicon CMOS backplane.

[0023] Regarding wafer size mismatch, substrates used for micro-LED device manufacturing (e.g., 100 mm, 150 mm, 200 mm wafers) may currently be smaller than substrates used for the highest performance and latest design CMOS technology nodes (e.g., 300 mm wafers). According to an embodiment, slicing of the growth substrate and direct die-to-wafer bonding to a larger CMOS wafer is avoided through a reconstruction process.

[0024] Regarding CTE mismatch induced bonding stress, the two substrates used for micro-LED epitaxy typically include GaAs and sapphire, both of which have a CTE factor that is approximately twice that of silicon. It has been observed that this CTE factor difference can cause die / wafer warpage during bonding and also contribute to bonding misalignment. According to an embodiment, this is mitigated by a reconfiguration process prior to wafer-to-wafer bonding to a CMOS backplane wafer (or substrate including an embedded pixel driver chip array).

[0025] With respect to yield degradation due to cutting particles, achieving zero dead pixels on the final product may require extremely high die-to-wafer or wafer-to-wafer contact pad bonding yields. This may require a flat and particle-free surface during bonding, particularly for the die-to-wafer bonding step, where particles and debris generated during cutting must be mitigated or completely removed in a cleaning step prior to bonding. In one embodiment, avoidance of cutting particles can be mitigated by a reconstruction process in which the cut growth substrate (e.g., GaAs, sapphire) is not bonded to a backplane substrate (e.g., a CMOS wafer or a substrate comprising an array of pixel driver chips). According to an embodiment, the growth substrate can be removed prior to any cutting.

[0026] With respect to degradation due to bonding misalignment, embodiments facilitate implementation of fine pitch density that is capable of approaching prior art limits of die-to-wafer and wafer-to-wafer bonding. In one embodiment, this is achieved using a wafer reconstruction method in which oversized pads are formed on each micro-LED on the LED growth substrate before cutting the coupon (die). The LED coupon is then reconstructed on a 300mm silicon wafer in which an array of via contacts is formed to connect to the oversized pad array. The reconstructed wafer is then bonded to a backplane substrate (e.g., a CMOS wafer or a substrate including an array of pixel driver chips). In this way, wafer-to-wafer bonding alignment is decoupled from the die-to-wafer process.

[0027] With respect to thermal budget, in some embodiments, a high temperature (e.g., greater than 400°C) micro-LED sidewall passivation process or a high temperature p / n contact formation anneal is required for device performance and electrical contact reasons. In one aspect, it has been observed that in order to achieve high brightness and high efficiency micro-LEDs, the Shockley-Reed-Hall (SRH) non-radiative recombination effect at the device sidewalls can be addressed. For example, it has been observed that SRH recombination can be mitigated by various high temperature processing techniques such as sidewall diffusion (e.g., zinc, magnesium, carbon, silicon, tellurium, etc.) at elevated temperatures or semiconductor regrowth deposition at elevated temperatures. In this case, the micro-LED device layers and substrates need to be compatible with high temperatures. However, due to the temperature stability of the low-k interlayer dielectric, the maximum allowable temperature of the backplane substrate (e.g., a CMOS wafer or substrate including an array of pixel driver chips) can be about 400°C. In addition, it has been observed that if the epitaxial LED layer has been bonded to a new carrier substrate, there may be a CTE mismatch between the epitaxial layer and the new carrier substrate during any subsequent high temperature exposure. Finally, it has been observed that thermal budget and / or outgassing of bonding materials (which are typically annealed at temperatures below 400° C. upon wafer bonding) can be an issue. According to embodiments, due to the coefficient of thermal expansion (CTE) mismatch between the epitaxial LED device layers and silicon, micro-LED sidewall passivation or high temperature p / n contact formation anneals can be performed on the initial LED growth substrate as opposed to the silicon substrate and avoid outgassing or bond line voids that may occur with many bonding layers used for epitaxial layer transfer when subjected to post-bonding processing temperatures above 400° C.

[0028] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and structures. In the following description, many specific details such as specific configurations, sizes and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, constructions or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, constructions or characteristics may be combined in one or more embodiments in any appropriate manner.

[0029] As used herein, the terms "on," "over," "to," "between," "spanning," and "over" may refer to the relative position of one layer relative to other layers. A layer that is "on," "over," "spanning," or "on" relative to another layer or bonded "to" or "in contact with" another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0030] Reference now Figure 1 , a cross-sectional side view illustration of a micro diode reconstruction and wafer to wafer bonding sequence according to an embodiment is provided. In the following description, various operations are mentioned that illustrate various nodes of wafer flipping or die to wafer or wafer to wafer bonding in the process sequence. Therefore, many processes may have occurred between each operation or node.

[0031] As shown, the processing sequence can start with a bulk LED substrate 100 including a pn diode layer 102 formed on a growth substrate 104. For example, the pn diode layer 102 can be designed to emit primary red light (e.g., 600nm-700nm wavelength), primary green light (e.g., 495nm-570nm wavelength), or primary blue light (e.g., 450nm-495nm wavelength), although embodiments are not limited to these exemplary emission spectra. The pn diode layer 102 can be formed of a plurality of compound semiconductors having band gaps corresponding to specific regions in the spectrum. For example, the pn diode layer 102 can include one or more layers based on II-VI materials (e.g., ZnSe) or III-V materials (including III-V nitride materials (e.g., GaN, AlN, InN, InGaN and alloys thereof), III-V phosphide materials (e.g., GaP, AlGaInP and alloys thereof), and III-V arsenide alloys (AlGaAs)). The growth substrate 104 can include any suitable substrate, such as, but not limited to, SiC, GaAs, GaN, sapphire, and silicon.

[0032] By way of example, in one embodiment, the pn diode layer 102 is designed to emit red light, and the material is based on phosphorus. The following list of materials for red light emission is intended to be exemplary and not limiting. For example, the layer forming the pn diode layer 102 may include AlInP, AlInGaP, AlGaAs, GaP, and GaAs. In such embodiments, suitable growth substrates 104 may include, but are not limited to, SiC and GaAs. In specific embodiments, the growth substrate is a 100 mm, 150 mm, or 200 mm GaAs substrate.

[0033] By way of example, in one embodiment, the pn diode layer 102 is designed to emit blue or green light, and the material is nitride-based. The following list of materials for blue or green light emission is intended to be exemplary and not limiting. For example, the layers forming the pn diode layer 102 may include GaN, AlGaN, InGaN. In such embodiments, a suitable growth substrate 104 may include, but is not limited to, sapphire. In a specific embodiment, the growth substrate is a 100 mm, 150 mm, or 200 mm sapphire substrate.

[0034] At operation 1010, the pn diode layer 102 is patterned to form an array of micro diodes 106, landing pads 108, and a back dielectric layer 110. Many additional structures and processes may be performed. The growth substrate may then be flipped and bonded to another carrier and prepared to be cut into sample blocks (or bare chips) for reconstruction. In this way, particles may be reduced by first removing the growth substrate 104. In a first variation, at operation 1020A, the back dielectric layer 110 is bonded to a carrier substrate 112, such as a 100 mm, 150 mm, or 200 mm silicon substrate. The carrier substrate 112 may be the same size as the original growth substrate 104, so that wafer-to-wafer bonding technology is used. In one embodiment, bonding is achieved by post-bonding annealing followed by oxide-oxide direct bonding. The growth substrate 104 is then removed using suitable techniques such as wet etching and chemical mechanical polishing (CMP), laser lift-off (LLO), etc. This can be followed by the deposition of a top contact layer 116, which can be a transparent conductive oxide, such as indium tin oxide (ITO) or a transparent conductive polymer. The top contact layer 116 can then be covered with a protective dielectric layer 118, which can also be transparent. In one embodiment, the carrier substrate 112 of the first variant is a sapphire wafer. In a second variant, at operation 1020B, the back dielectric layer 110 is instead bonded to the carrier substrate 112 with a curable bonding layer 114 such as benzocyclobutene (BCB). Curing can be thermally based, or UV based, for more CTE mismatched material systems. This can be followed by the deposition of a top contact layer 116 and a protective dielectric layer 118. In one embodiment, the carrier substrate 112 of the second variant is a sapphire wafer.

[0035] For both variants, at operations 1030A and 1030B, the light emitting structure is cut into sample blocks 120 (also referred to as bare chips). As shown in the figure, the growth substrate 104 has been removed at this time, and thus the process flow eliminates the introduction of growth substrate 104 particles generated during cutting into subsequent facilities. Exemplary cutting methods include saw cutting, stealth cutting, plasma etching cutting, etc.

[0036] Referring now to operations 1040A and 1040B, the sample block 120 array may then be bonded to a second carrier substrate 122. The sample block 120 may be formed from a plurality of LED substrates 100. Specifically, the second carrier substrate 122 may be a silicon wafer, more specifically a 300 mm silicon wafer that may be processed using current industry standards. As shown, after plasma surface activation, the protective dielectric layer 118 is bonded directly to the thin oxide top surface of the second carrier substrate 122 using oxide-oxide bonds. This is followed by the removal of the first carrier substrate 112. For example, a grinding technique may be used for a silicon first carrier substrate, while an LLO technique may be used for a sapphire first carrier substrate.

[0037] Still referring to operations 1040A and 1040B, misaligned coupon 120M is additionally illustrated. As will become apparent in the following description, the reconstruction sequence and oversized landing pads 108 can allow for relaxed tolerances in the placement distribution of coupons, and therefore the array of microdiodes 106.

[0038] Referring now to operation 1050, a gap fill layer 128 is formed over the coupons 120 and laterally between the coupons. For example, the gap fill layer 128 can be an oxide layer or other suitable dielectric. This can be followed by planarization and an industry standard 300 mm copper damascene process to form one or more metal layers. In the illustrated process, a single damascene via contact 130 is formed as part of a reconstructed wiring layer 131 to connect with the landing pad 108. Dual damascene and other processes may also be used to form the reconstructed wiring layer 131. It should be understood that the damascene process is decoupled from the placement of the coupons 120 by including an oversized landing pad 108. In the final stage of the copper damascene process, the reconstructed substrate 135 is reconstructed using a CMP process to provide a planar dielectric surface 132 and a planar metal contact surface 134 of the reconstructed wiring layer 131, which surfaces may correspond to via contacts 130 or other redistribution layers, etc. within the reconstructed wiring layer 131.

[0039] Still referring to operation 1050, the location distribution of via contacts 130 may be defined by the 300 mm copper damascene process and therefore not constrained by the placement distribution of coupons 120. As shown, the oversized landing pads 108 for the misaligned coupons 120M allow contact with the via contacts 130.

[0040] Then, at operation 1060, the reconstructed substrate 135 may be bonded to a backplane 140, such as a CMOS substrate or a substrate including a plurality of embedded pixel driver chips. According to an embodiment, the bonding may be wafer-to-wafer hybrid bonding. Figure 1As shown, the backplane 140 may include a silicon substrate 142 and a top dielectric layer 144 having vias 146. The top surface may be planarized to form a planarized top contact pad 148 of the via 146 and a planarized top surface 145 of the top dielectric layer 144. In one embodiment, hybrid bonding may achieve metal-metal (e.g., copper-copper) bonding with the contact pad 148 and the planar contact surface 134, and dielectric-dielectric (e.g., oxide-oxide) bonding with the planar dielectric surface 132 and the top surface 145 of the top dielectric layer 144. The second carrier substrate 122 may then be removed, followed by deposition of additional optics and dicing into optoelectronic structures.

[0041] Figure 2 is a schematic top view illustration of an optoelectronic structure 150 with misaligned coupons 120M according to an embodiment. Specifically, Figure 2 An optoelectronic structure 150 after dicing is illustrated. As shown, an array of coupons 120, including misaligned coupons 120M, is arranged on a backplane 140. The xy position of the misaligned coupons 120M has shifted from the nominal position, as evidenced by the position of the landing pads 108. However, the positions of the via contacts 130 and the contact pads 148 (illustrated as the same position) are determined using a 300 mm copper damascene process and wafer-to-wafer bonding accuracy, both of which may be higher than the die-to-wafer bonding accuracy of the coupons. In one embodiment, the placement distribution of the array of landing pads 108 on the backplane 140 is characterized by the first order standard deviation of the displacement values ​​of the array of landing pads to the array of contact pads 148, and the position distribution of the array of via contacts 130 on the backplane is characterized by the first order standard deviation of the displacement values ​​of the array of via contacts 130 to the corresponding array of contact pads 148, and the first order standard deviation for the placement distribution of the array of landing pads 108 on the backplane is greater than the first order standard deviation for the position distribution of the array of via contacts 130 on the backplane. For convenience, the distribution can be measured from the geometric center (or centroid) point of the structure.

[0042] Figure 3 is a schematic cross-sectional side view illustration of an optoelectronic structure 150 according to an embodiment. In particular, Figure 1 The process sequence shown in the example is used to manufacture Figure 31. An optoelectronic structure 150 is illustrated in FIG. 1. In one embodiment, the optoelectronic structure 150 includes: a backplane 140 including a drive circuit 141 (e.g., a CMOS drive circuit, or a pixel driver chip including a drive substrate) and an array of contact pads 148; and a device layer 155 bonded to the backplane 140. The device layer 155 can be formed as part of a reconstruction process and includes: an array of microdiodes 106 (e.g., microLEDs, photodetectors); an array of landing pads 108 below the array of microdiodes 106, wherein each landing pad corresponds to a microdiode; and an array of via contacts 130 connected to the array of landing pads 148, wherein each via contact 130 corresponds to a landing pad 148. According to an embodiment, the array of via contacts 130 is part of a reconstruction wiring layer 131, which is directly bonded to the array of contact pads 148 by metal-metal bonds (e.g., copper-copper).

[0043] The array of via contacts 130 can be formed using a damascene process (including single damascene, dual damascene). The array of via contacts 130 can be formed as a portion of a single metal layer or a multi-metal layer within the reconstruction wiring layer 131 for wiring distribution. In the illustrated specific embodiment, a single damascene and a single metal layer are shown, although the embodiment is not limited thereto. The array of via contacts 130 can also be embedded in a dielectric build-up layer 129. For example, this can be a portion of a gap fill layer 128 or a separate layer formed on top of the gap fill layer 128 and the sample block 120 during the reconstruction sequence. As shown, the dielectric build-up layer 129 can be directly bonded to the top dielectric layer 144 of the backplane 140 using a dielectric-dielectric bond (e.g., oxide-oxide).

[0044] According to an embodiment, the array of microdiodes 106 can be part of a plurality of coupons 120, wherein each coupon includes a subarray of microdiodes 106. In addition, a gap fill layer 128 can laterally surround each coupon 120 and be laterally located between adjacent coupons. Each coupon 120 may include a back dielectric layer 110. Thus, the array of via contacts 130 includes a plurality of subarrays of via contacts 130, wherein each subarray of via contacts extends through a corresponding back dielectric layer 110. In one embodiment, the spacing between via contacts 130 within each via contact subarray is 5 μm or less, although embodiments are not limited thereto.

[0045] The optoelectronic structure 150 may optionally include a plurality of dummy vias 130D formed simultaneously and laterally adjacent to the array of via contacts 130. The dummy vias 130D may extend through the dielectric build-up layer 129 and optionally partially into the gap fill layer 128. Likewise, the backplane 140 may optionally include a plurality of contact pads 148D to facilitate wafer-to-wafer bonding. The plurality of dummy vias 130D may be arranged between the coupons so that the dummy vias are not directly above the plurality of coupons 120. This may facilitate, for example, mechanical and thermal balance, although other arrangements are possible.

[0046] Still referring to the embodiment according to Figure 3 After removing the second carrier substrate 122, additional processing may be performed, such as final power and data routing, and forming additional optical features, such as microlens fabrication. In one embodiment, the microlenses are formed by depositing an optical layer 164 followed by embossing to form hemispherical features 166 or the like. The following description will describe in more detail the microlenses. Figure 3 Additional features are shown but not labeled, such as alignment key 168.

[0047] Reference now FIG. 4A to FIG. 4C , Figure 4A is a schematic cross-sectional side view illustration of an optoelectronic structure stack including a microdiode 106 having a diffused sidewall passivation layer 170 according to an embodiment; FIG. 4B to FIG. 4C 1 is a schematic cross-sectional side view illustration of an optoelectronic structure stack including a microdiode with a regrown sidewall passivation layer 172 according to an embodiment. In the illustrated exemplary embodiment, each microdiode 106 may include a bottom doped layer 174 (e.g., p-doped), a top doped layer 176 (e.g., n-doped) having a doping opposite to the bottom doped layer, and an active layer 178 between the bottom doped layer and the top doped layer. For example, the active layer 178 may include one or more quantum well layers and barrier layers separating the quantum well layers.

[0048] A dielectric insulating layer 180 may be formed on the sidewall 175, along the sidewall, and between the microdiodes 106 to provide electrical insulation. An opening may be formed in the dielectric insulating layer 180 on the bottom side of the bottom doped layer 174 to allow a bottom electrical contact 182 to make electrical contact with the bottom doped layer 174 (or an intervening current spreading layer). For example, the bottom electrical contact 182 may be a single layer or a multi-layer metal layer stack. A reflector layer 184 may be optionally formed on the dielectric insulating layer 180, and optionally formed on the bottom electrical contact 182. The reflector layer 184 may be formed of a suitable material (e.g., Au, Ag, Al, Ru, etc.) to reflect the peak emission / absorption wavelength of the microdiode 106. In the illustrated embodiment, the landing pad 108 is formed directly on the reflector layer 184. A dielectric fill layer 186 may be located around the microdiode 106, and optionally around the landing pad 108. The dielectric fill layer 186 may be formed of a suitable material such as BCB, and may be transparent or opaque.

[0049] exist Figure 4A In the specific embodiment illustrated in , the diffused sidewall passivation layer 170 can be formed by, for example, thermal plasma or ion implantation techniques. In one embodiment, dopants such as zinc, magnesium, carbon, silicon, tellurium, etc. are diffused into the sidewalls 175 to promote mixing of components in the active layer 178 and increase the overall bandgap, thereby reducing carrier diffusion to the sidewalls 175 and overall non-radiative recombination. Such processes can be performed at elevated temperatures and can include additional anneals at elevated temperatures, such as greater than 500°C.

[0050] Reference now FIG. 4B to FIG. 4C , two different regrowth options are illustrated, where the sidewall passivation layer 172 is grown on and lattice-matched to the sidewalls 175. Figure 4B In the embodiment illustrated in FIG. 1 , regrowth is performed around and below the bottom doped layer 174. Figure 4C 175, the regrowth is confined to the sidewalls 175. In either configuration, the sidewall passivation layer 172 can be lattice matched to the microdiode 106 and satisfy dangling bonds at the sidewalls 175. Thus, the sidewall passivation layer 172 having a higher bandgap or insulating quality than the quantum well layers within the active layer 178 can reduce carrier diffusion through the sidewalls 175 and overall non-radiative recombination at the outer surface of the regrown sidewall passivation layer 172. In one embodiment, the sidewall passivation layer 172 is doped to the same conductivity as the bottom doped layer 174.

[0051] exist FIG. 4A to FIG. 4CIn each of the figures, the diffused sidewall passivation layer 170 can be diffused into any combination of the active layer, the n-doped layer, and the p-doped layer and the regrown sidewall passivation layer 172 can be grown in any combination of the active layer, the n-doped layer, and the p-doped layer. Figure 4A In the embodiment illustrated in , the diffused sidewall passivation layer can diffuse into and span over the sidewalls of the p-doped layer (e.g., bottom doped layer 174), the active layer, and the n-doped layer (e.g., top doped layer 176). FIG. 4B to FIG. 4C In the embodiment illustrated in , the regrown passivation spans over the sidewalls of the p-doped layer, the active layer, and the n-doped layer. In other embodiments, the sidewall passivation layer can be selectively diffused into the active layer or grown onto the active layer, or combined with other layers forming the sidewalls.

[0052] Reference now FIG. 5A to FIG. 5C , Figure 5A is a schematic cross-sectional side view illustration of an optoelectronic structure including a plurality of coupons according to an embodiment; Figure 5B is a close-up schematic cross-sectional side view illustration of an optoelectronic structure including a single coupon according to an embodiment; Figure 5C According to the implementation plan Figure 4B Schematic top view illustration of the top opaque electrode layer. Figure 5A The embodiments illustrated in Figure 3 The embodiments illustrated and described share many general features. Therefore, the following description is directed to the structural differences and can be understood by FIG. 5B to FIG. 5C Close-up icons are provided to assist.

[0053] like FIG. 5A to FIG. 5B As shown, in the illustrated embodiment, the landing pad 108 can be integrated into the corresponding reflector layer 184. This can be achieved by further integrating the pattern of the intermediate pn diode layer material 101 laterally between the microdiodes 106 of the microdiode subarray, wherein the microdiode 106 is defined by a groove 107 that at least partially passes through the pn diode layer 102. The groove 107 additionally separates the intermediate pn diode layer material 101 from the microdiode 106. In addition, the reflector layer 184 conformally wraps around the corresponding microdiode 106 and a portion of the adjacent pattern of the intermediate pn diode layer material 101. Such a construction can provide several structural properties. In one aspect, the reflector layer 184 also acts as a landing pad 108 for the via contact 130. As shown Figure 5AAs shown, the reflector layer 184 for the misaligned coupon 120M can be wider than the via contact 130 and allow for landing of the via contact 130 for the misaligned coupon 120. For example, the via contact 130 can optionally partially or completely overlap a portion of the trench 107. In another aspect, the volume of semiconductor material in the intermediate pn diode layer material 101 can potentially improve planarity during wafer-to-wafer bonding of the device layer to the first carrier substrate 112.

[0054] Reference now Figure 5B , illustrates a supplemental via contact 130X that can provide an electrical connection between the working circuit 141 of the backplane 140 and the top side of the microdiode 106. As shown, the via contact 130X can optionally land on the reflector layer 184, or even on one of the layers used to form the reflector layer 184. This can pass through the opening 103 in and on the lower side of the pn diode layer 102 and make contact with the conductive top electrode layer 115 on the top side of the pn diode layer 102. The top electrode layer 115 can optionally be formed within the opening 179 in the top side of the pn diode layer 102. Exemplary materials for the top electrode layer 115 include metallic materials such as Ni, Ge, Al, Pt, Ru, Au, including their metal stack combinations and their alloys. Therefore, the top electrode layer 115 can be opaque. As Figure 5C As shown, the top electrode layer 115 can be patterned into a grid or lattice configuration with openings above each microdiode 106. In this way, the metal material forming the top electrode layer 115 is located above the intermediate pn diode layer material 101 and does not absorb a significant amount of light emitted by the functional microdiodes 106. Electrical connection can be facilitated by a doped current spreading layer 177 (e.g., n++ doped III-V material) within the pn diode layer 102.

[0055] In the illustrated embodiment, the supplemental via contact 130X can land on the reflector layer 184 on the spare microdiode 106X. Such a construction can realize the use of a mask set that supports LED redundancy or spare combination physically and electrically, while also supporting the use of the same mask for top-side contact connection. For example, individual microdiodes can be optically tested at an intermediate stage during manufacturing to determine any irregularities. At this time, a decision can be made as to whether to utilize the spare microdiode 106X to replace the emitting microdiode 106 with the via contact 130 connection or as a support structure for the supplemental via contact 130X. The result of this decision can determine whether to pattern the dielectric insulating layer 180 and form the bottom electrical contact 182. In the case where the dielectric insulating layer 180 is not patterned and the bottom electrical contact 182 is not formed, the supplemental via contact 130X does not make electrical contact with the spare microdiode 106X on which the supplemental via contact lands. It should be understood that the supplemental via contact 130X may instead land on the intermediate pn diode layer material 101. Additionally, such a structure may be implemented in other optoelectronic structures described herein, including Figure 3 and related descriptions and drawings.

[0056] In one embodiment, the array of via contacts 130 (and supplemental via contacts 130X) extends through a portion of the gap fill layer 128, but this is not required. FIG. 5A to FIG. 5B As shown, in one embodiment, the sample block 120 may include a pn diode layer including a corresponding micro-diode 106 sub-array (the micro-diode may include a spare micro-diode 106X) and an intermediate pn diode layer material 101 pattern laterally located between the micro-diodes 106 of the micro-diode sub-array, wherein the intermediate pn diode layer material 101 pattern is separated from the micro-diode 106 sub-array by a trench 107. Figure 5B As shown in , the minimum width (Ws) of the intermediate pn diode layer material 101 pattern positioned laterally between adjacent microdiodes 106 of the microdiode subarray can be greater than the minimum width (Wu) of the adjacent microdiode 106. The maximum trench 107 width (Wt) can be customized according to the device density and the layer thickness of the layers to be formed therein (such as the dielectric insulation layer 180 and the reflector layer 184). According to an embodiment, the sample block 120 may include a reflector layer 184 subarray conformally wrapped around a subarray of microdiodes 106 (including spare microdiodes 106X) and a portion of the intermediate pn diode layer material 101 pattern. Each reflector layer 184 may include or correspond to a landing pad 108 of the landing pad array.

[0057] Still reference FIG. 5A to FIG. 5BIn one embodiment, the optoelectronic structure 150 includes an opaque top electrode layer 115 spanning over the pattern of the intermediate pn diode layer material 101. An opening 103 can be formed through the back side of the pn diode layer, and a back contact layer 183 is formed within the opening and is in electrical contact with the top electrode layer 115. The back contact layer 183 can be formed of a variety of materials, including the same layer used to form the bottom electrical contact 182 or the reflector layer 184. The back contact layer 183 can also be a discrete layer with a different composition and thickness than the surrounding conductive layers. According to an embodiment, the back contact layer 183 is electrically connected to a supplementary via contact 130X, which is bonded to a contact pad 148 of an array of contact pads 148 of the back plate 140. The supplementary via contact 130X can be additionally connected to a reflector layer 184, which in turn is connected to the back contact layer 183. A variety of possibilities for electrically connecting the back plate 140 to the top electrode layer 115 are envisioned.

[0058] FIG. 6A to FIG. 6N is a cross-sectional side view illustration of a microdiode reconstruction and wafer-to-wafer bonding sequence according to an embodiment. FIG. 6A to FIG. 6N and Figure 1 The sequence exemplified in Figure 3 The optoelectronic structure 150 is complementary and supplementary. Fig. 6A As shown, the sequence can start with a body LED substrate 100 including a pn diode layer 102, which includes a bottom doped layer 174 (e.g., p-doped), a top doped layer 176 having a doping opposite to the bottom doped layer (e.g., n-doped), and an active layer 178 between the bottom doped layer and the top doped layer.

[0059] By way of example, in one embodiment, pn diode layer 102 is designed to emit red light, and the material is based on phosphorus. The following list of materials for red light emission is intended to be exemplary rather than restrictive. For example, the layer forming pn diode layer 102 may include AlInP, AlInGaP, AlGaAs, GaP and GaAs. In one embodiment, top doped layer 176 includes n-AlInGaP and bottom doped layer 174 includes p-AlGaInP. Active layer 178 can be formed by a variety of materials, such as but not limited to AlGaInP, AlGaAs and InGaP. In such embodiments, suitable growth substrate 104 may include but is not limited to silicon, SiC and GaAs. Sacrificial layer 105 can be formed by suitable buffer material, such as AlGaInP can be formed for subsequent removal.

[0060] By way of example, in one embodiment, the pn diode layer 102 is designed to emit blue or green light, and the material is based on nitride. The following list of materials for blue or green light emission is intended to be exemplary and not restrictive. For example, the layers forming the pn diode layer 102 may include GaN, AlGaN, InGaN. In one embodiment, the top doped layer 176 includes n-AlGaN and the bottom doped layer 174 includes p-AlGaN. The active layer 178 can be formed of a variety of materials, such as but not limited to InGaN. In such embodiments, suitable growth substrates 104 may include but are not limited to silicon and sapphire. The sacrificial layer 105 can be formed of a suitable buffer material, such as AlGaN can be formed for subsequent removal.

[0061] Reference now Figure 6B , the pn diode layer 102 is etched to form an array of micro diodes 106 separated by trenches 107. The pattern of walls 109 may optionally be retained. Walls 109 may not be active diode regions, although they may be retained in the structure to provide, for example, mechanical stability. Walls 109 may be formed around the perimeter of the patterned bulk LED substrate 100 or retained at strategic locations that may end up in the display / detection region of the optoelectronic structure. After forming the micro diodes 106, additional sidewall passivation treatments may optionally be performed, such as with respect to FIG. 4A to FIG. 4C As described, a dielectric insulating layer 180 (eg, Al2O3, SiO2, etc.) is then deposited. The dielectric insulating layer 180 may then be patterned to expose the pn diode layer 102, followed by the deposition of a bottom electrical contact 182 and a reflector layer 184.

[0062] exist Figure 6B In the specific embodiment illustrated in FIG. 1 , the etching of the pn diode layer 102 does not completely penetrate the top doped layer 176, which may optionally remain connected between the micro-diodes 106. However, this is exemplary, and in other embodiments, the etching of the pn diode layer 102 completely penetrates the top doped layer 176 to completely isolate the micro-diodes 106 (similar to FIG. Figure 1 ).

[0063] like Figure 6C As shown, a dielectric filling layer 186 may be formed around and over the micro diode 106. The dielectric filling layer 186 may be formed of a suitable material, such as silicon dioxide, silicon nitride, SiC x N y O z, BCB, epoxy, acrylic, etc., and can be transparent or opaque. For example, the dielectric fill layer 186 can be deposited using a solvent-based technique such as slot coating or spin coating. Other suitable deposition techniques can also be used for other materials, such as plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD) followed by CMP planarization. The dielectric fill layer 186 can then be patterned to form openings 188, such as Fig.6D As shown, the opening exposes the reflector layer 184 when present, or alternatively, the opening exposes another electrical connector (eg, bottom contact 182 ) for the microdiode 106 .

[0064] Reference now Fig. 6E , a bulk metal layer 111 is deposited on the underlying structure. This can be accomplished, for example, by electroplating. The bulk metal layer 111 can include one or more layers of materials, such as Ta, TaN, and W. The bulk metal layer 111 can be thick enough to completely fill the opening 188. This can be followed by a planarization operation, such as CMP, to remove any remaining bulk metal layer 111 outside of the opening 188, thereby producing a Fig. 6F Landing pad 108 is shown. In one embodiment, after planarization, a gap fill layer 186 optionally covers the walls 109.

[0065] refer to Figure 6G The planarized surface can then be covered with a back dielectric layer 110 (e.g., a SiO2 film) and then planarized and bonded to a first carrier substrate 112 using a dielectric-dielectric (oxide-oxide) bond. Such a processing sequence is similar to Figure 1 The process sequence of operation 1020A is consistent with that of operation 1020A, although the process sequence of operation 1020B may also be utilized.

[0066] Then you can Figure 6H As shown, the growth substrate 104 and sacrificial layer 105 are removed, and then the top contact layer 116 metal alignment key 168 for die-to-wafer bonding is formed. Various wiring layers can also be deposited at this time. The alignment key 168 can optionally be deposited and patterned using a lift-off technique. Then, the protective dielectric layer 118 can be deposited and planarized to form a planar surface 169.

[0067] like Fig.6I As shown, a protective coating 190 may then be deposited on the protective dielectric layer 118 before the substrate is thinned and cut into individual coupons 120. Such coatings may help prevent particles from adhering to the surfaces of the coupons 120. Exemplary coatings may include solvent / water cleanable films such as polymethyl methacrylate (PMMA), water soluble resins, and the like.

[0068] According to an embodiment, the protective coating 190 may be removed prior to testing the known good die (KGD) or coupon 120. Fig.6I KGD test can also be performed after the cut shown in Figure 6H In both embodiments, the KGD test may be performed after the growth substrate is removed, so that the epitaxial device layers are located on a first carrier substrate 112 (e.g., a silicon carrier). In this way, the process flow allows the option of reconstructing only KGD coupons, and in particular KGD coupons on silicon, rather than a growth substrate with a CTE mismatch with silicon.

[0069] Reference now Figure 6J , the sample block 120 can be bonded to the top surface 123 of the second carrier substrate 122. The bonding can be a die-to-wafer bonding process, which includes sample block cleaning, sample block plasma activation, top surface 123 activation, and dielectric-dielectric (oxide-oxide) bonding. As shown, the alignment key 168 of the sample block 120 can be aligned with the alignment mark 191 on the second carrier substrate 122, which can be formed using suitable techniques, such as etching marks on the silicon substrate or depositing metal marks on the silicon substrate, followed by dielectric (oxide) filling and CMP to form the top surface 123.

[0070] A gap fill layer 128 may then be deposited on the second carrier substrate 122 and the coupon 120, thereby filling the lateral space between the coupons 120 and laterally surrounding the coupons 120. The gap fill layer 128 may be an oxide layer or other suitable dielectric, including a polymer. This may be followed by a planarization operation that may remove a portion of the second carrier substrate 122 and expose the back dielectric layer 110 of the coupon, such as Figure 6K Described in.

[0071] Reference now Figure 6L, the partially reconstructed substrate can be processed with an industry standard 300mm copper damascene process to form one or more metal layers (including two or more metal layers). For ease of illustration, a single metal layer with both single and dual damascene options is illustrated. It should be understood that this is for illustrative purposes only and that a variety of routing options are available. In both processes, a via contact 130 is formed to connect to the landing pad 108. As shown, a dielectric build-up layer 129 can be formed over the gap fill layer 128 and the coupon 120. The dielectric build-up layer 129 may include one or more dielectric layers 127a, 127b, etc. and one or more metal (e.g., Cu) layers for forming redistribution lines and vias of the reconstructed wiring layer 131. The redistribution lines and vias of the reconstructed wiring layer 131 can be formed using a single damascene process, in which the trenches 192 and the vias 130 are formed as two metal layers; or formed using a dual damascene method (as illustrated in the figure), in which the trenches 192 and the vias 130 are formed as a single metal layer. As previously described, the damascene process is decoupled from the placement of the coupon 120 by including oversized landing pads. After the damascene process, the reconstituted substrate 135 can be planarized to provide a planar dielectric surface 132 and a planar contact surface 134 for the metal layer.

[0072] Still reference Figure 6L , according to an embodiment, a dummy via 130D (and optionally a dummy trench) may be formed, optionally including a dummy planar contact surface 134D. Multiple dummy vias 130D may be arranged between the coupons so that they do not vertically overlap with the multiple coupons 120. This may facilitate, for example, mechanical and thermal balance, although other arrangements are possible. The dummy planar contact surface 134D may also improve the topography to facilitate metal-to-metal (copper-to-copper) bonding to the backplane. As described with respect to Figure 1 As described, the oversized landing pad 108 may decouple the damascene process and final wafer-to-wafer alignment from the coupon 120 placement.

[0073] like Figure 6MAs shown, the reconstructed substrate 135 can then be bonded to a backplane 140, such as a CMOS substrate. According to an embodiment, the bonding can be a wafer-to-wafer hybrid bonding using copper-copper metal interconnects. The backplane 140 can include a silicon substrate 142 and a top dielectric layer 144 having a via 146. The top surface can be planarized to form a planarized top contact pad 148 of the via 146 and a planarized top surface 145 of the top dielectric layer 144. In one embodiment, hybrid bonding can achieve metal-metal (e.g., copper-copper) bonding with the contact pad 148 and the planar contact surface 134, and dielectric-dielectric (e.g., oxide-oxide) bonding with the planar dielectric surface 132 and the top surface 145 of the top dielectric layer 144. The second carrier substrate 122 can then be removed using suitable techniques, such as CMP followed by wafer grinding, or a wet chemical etching process followed by wafer grinding.

[0074] The final power and data wiring circuits can then be added as well as Figure 6N Any optical structure such as the microlens array shown. For example, an optical layer 164 such as a transparent polymer can be deposited and then embossed to form hemispherical features 166 or the like. Individual optoelectronic structures 150 can then be cut from the stack.

[0075] FIG. 7A to FIG. 7L is a cross-sectional side view illustration of a microdiode reconstruction and wafer-to-wafer bonding sequence according to an embodiment. FIG. 7A to FIG. 7L and Figure 1 and FIG. 6A to FIG. 6N The sequences exemplified in have similarity, with some modifications to achieve about FIG. 5A to FIG. 5C The optoelectronic structure shown and described. Fig. 6A As shown, the sequence can start with a bulk LED substrate 100 including a pn diode layer 102, which includes a bottom doped layer 174 (e.g., p-doped), a top doped layer 176 having a doping opposite to the bottom doped layer (e.g., n-doped), and an active layer 178 between the bottom doped layer and the top doped layer. The pn diode layer 102 can optionally include a current spreading layer 177 (e.g., n++ doped), which can be doped with a similar dopant type as the top doped layer 176 (and optionally more highly doped). For example, the current spreading layer 177 can be formed of a similar material as the top doped layer 176. Similar to the previous description, the pn diode layer 102 can be designed to emit red light, green light, blue light, etc.

[0076] Reference now Figure 7B, the pn diode layer 102 is etched to form micro diodes 106 separated by trenches 107 and an optional array of spare micro diodes 106. Openings 103 may additionally be formed to facilitate backside contact. Figure 7B In the specific embodiment illustrated in FIG. 1 , the etching of the pn diode layer 102 does not completely pass through the current spreading layer 177, which may optionally remain connected between the micro-diodes 106. However, this is exemplary, and in other embodiments, the etching of the pn diode layer 102 completely passes through the current spreading layer 177 to completely isolate the micro-diodes 106. The pattern of the wall may be maintained as shown in the pattern of the intermediate pn diode layer material 101 to provide, for example, mechanical stability. After forming the pattern of the micro-diodes 106, the optional spare micro-diodes 106, and the intermediate pn diode layer material 101, the etching may be performed as described above. FIG. 4A to FIG. 4C The additional sidewall passivation process described above is followed by deposition of a dielectric insulating layer 180 (e.g., Al2O3, SiO2, etc.). The dielectric insulating layer 180 may then be patterned to expose the pn diode layer 102, followed by deposition of a bottom electrical contact 182 and a reflector layer 184. Figure 7B As shown, the back contact layer 183 can be deposited in the opening 103 simultaneously, in parallel or separately with the bottom electrical contact 182, and can share the same layer stack, partial layers or be completely different layers. Figure 7C As shown in , the reflector layer can be formed over the bottom electrical contact 182 and the back contact layer 183 and within the trench 107 and partially across portions of the pn diode layer material 101 .

[0077] like Fig.7D As shown, a dielectric fill layer 186 may be formed around and over the micro diode 106. The dielectric fill layer 186 may be formed of a suitable material, such as silicon dioxide, silicon nitride, SiCxNyOz, BCB, epoxy, acrylic, etc., and may be transparent or opaque. For example, the dielectric fill layer 186 may be deposited using a solvent-based technique such as slot coating or spin coating. Other suitable deposition techniques may also be used for other materials, such as plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD), followed by CMP planarization.

[0078] refer to Fig. 7E The planarized surface can then be bonded to the first carrier substrate 112 using a dielectric-dielectric (oxide-oxide) bond. Figure 7FAs shown, the growth substrate 104 and sacrificial layer 105 can then be removed, followed by forming an opening 179 in the pn diode layer above the back contact layer 183, and forming the opening 103 below. As shown, the etching of the opening 179 can stop on the dielectric insulating layer 180. A second operation can then be performed to selectively remove the dielectric insulating layer 180 within the opening 179, exposing the back contact layer 183. This can be followed by forming the top electrode layer 115, the metal alignment key 168 for die-to-wafer bonding, and the protective dielectric layer 118, as shown. Figure 7G The protective dielectric layer 118 may then be planarized to form a planar surface 169 .

[0079] According to an embodiment, KGD testing can be performed before forming the protective dielectric layer 118 and before cutting into coupons. KGD testing can also be performed after cutting. In this way, the process flow allows the option of reconstructing only KGD coupons, and in particular KGD coupons on silicon, rather than growth substrates with CTE mismatched to silicon.

[0080] Reference now Figure 7H , the sample block 120 can be bonded to the top surface 123 of the second carrier substrate 122. The bonding can be a die-to-wafer bonding process, which includes sample block cleaning, sample block plasma activation, top surface 123 activation, and dielectric-dielectric (oxide-oxide) bonding. As shown, the alignment key 168 of the sample block 120 can be aligned with the alignment mark 191 on the second carrier substrate 122, which can be formed using suitable techniques, such as etching marks on the silicon substrate or depositing metal marks on the silicon substrate, followed by dielectric (oxide) filling and CMP to form the top surface 123.

[0081] A gap fill layer 128 may then be deposited on the second carrier substrate 122 and the coupons 120 to fill the lateral spaces between the coupons 120 and to laterally surround the coupons 120, such as Fig.7I 1. The gap fill layer 128 may be an oxide layer or other suitable dielectric, including a polymer. In the illustrated embodiment, the gap fill layer 128 covers the dielectric fill layer 186 for each of the coupons 120, although this is optional. In addition, a dielectric build-up layer 129 may be formed over the gap fill layer 128 and the coupons 120. The dielectric build-up layer 129 may be used, for example, in a dual damascene process, although the embodiments are not limited thereto.

[0082] Reference now Figure 7J, the partially reconstructed substrate can be processed with an industry standard 300mm copper damascene process to form one or more metal layers (including two or more metal layers) 131 as part of the reconstructed wiring layer 131. Similar to the previous discussion, for example, single damascene and dual damascene manufacturing sequences can be used. In the illustrated specific embodiment, a dual damascene process is shown, although this is not required. It should be understood that this is for illustrative purposes only and that a variety of wiring options are available. In both processes, via contacts 130 are formed to connect to landing pads 108 formed by reflector layer 184. As previously described, the damascene process is decoupled from the placement of the sample block 120 by including an oversized landing pad formed by the reflector layer 184. After the damascene process, the reconstructed substrate 135 can be planarized to provide a planar dielectric surface 132 and a planar contact surface 134 for the metal layer.

[0083] Still reference Figure 7J , according to an embodiment, a dummy via 130D (and optionally a dummy trench) may be formed, optionally including a dummy planar contact surface 134D. Multiple dummy vias 130D may be arranged between the coupons so that the dummy vias are not directly above the multiple coupons 120. This may facilitate, for example, mechanical and thermal balance, although other arrangements are possible. The dummy planar contact surface 134D may also improve the topography to facilitate metal-metal (copper-copper) bonding to the backplane.

[0084] like Figure 7K As shown, the reconstructed substrate 135 can then be bonded to a backplane 140, such as a CMOS substrate or a substrate with an embedded pixel driver chip. According to an embodiment, the bonding can be a wafer-to-wafer hybrid bonding using a copper-copper metal interconnect. The backplane 140 can include a silicon substrate 142 and a top dielectric layer 144 having a via 146. The top surface can be planarized to form a planarized top contact pad 148 of the via 146 and a planarized top surface 145 of the top dielectric layer 144. In one embodiment, hybrid bonding can achieve metal-metal (e.g., copper-copper) bonding with the contact pad 148 and the planar contact surface 134, and dielectric-dielectric (e.g., oxide-oxide) bonding with the planar dielectric surface 132 and the top surface 145 of the top dielectric layer 144. The second carrier substrate 122 can then be removed using suitable techniques, such as CMP after wafer grinding, or a wet chemical etching process after wafer grinding.

[0085] The final power and data wiring circuits can then be added as well as Figure 7LAny optical structure such as the microlens array shown. For example, an optical layer 164 such as a transparent polymer can be deposited and then embossed to form hemispherical features 166 or the like. Individual optoelectronic structures 150 can then be cut from the stack.

[0086] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming optoelectronic structures. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. Instead, the specific features and acts disclosed should be understood as embodiments of the claims for purposes of illustration.

Claims

1. A photoelectric structure, comprising: a backplane, the backplane comprising a drive circuit and an array of contact pads; A device layer, the device layer is bonded to the backplane, the device layer comprising: micro diode arrays; an array of landing pads, the array of landing pads being located below the array of microdiodes, each landing pad corresponding to a microdiode; and an array of via contacts connected to the array of landing pads, each via contact corresponding to a landing pad; The via contact array is part of a reconstructed wiring layer, and the reconstructed wiring layer is directly bonded to the contact pad array through a metal-metal bond.

2. The optoelectronic structure of claim 1, wherein the via contact array is a damascene array.

3. The optoelectronic structure of claim 1, wherein the array of via contacts is at least partially embedded within a dielectric build-up layer.

4. The optoelectronic structure of claim 3, wherein the dielectric build-up layer is directly bonded to the top dielectric layer of the backplane.

5. The optoelectronic structure of claim 1, wherein the microdiode array is composed of a plurality of coupons, each coupon comprising a microdiode sub-array.

6. The optoelectronic structure of claim 5, wherein each sample block comprises a dielectric fill layer beneath a corresponding micro diode subarray, and the via contact array comprises a plurality of via contact subarrays, and each via contact subarray extends through the corresponding dielectric fill layer.

7. The optoelectronic structure of claim 6, wherein the pitch between the via contacts within each via contact subarray is 5 μm or less.

8. The optoelectronic structure of claim 5, further comprising a gap-fill layer laterally surrounding each coupon and laterally between adjacent coupons.

9. The optoelectronic structure of claim 8, wherein the array of via contacts extends through a portion of the gap fill layer.

10. The optoelectronic structure of claim 8, wherein a coupon of the plurality of coupons comprises a pn diode layer, the pn diode layer comprising: corresponding micro diode subarrays; an intermediate pn diode layer material pattern, the intermediate pn diode layer material pattern being laterally located between the microdiodes of the microdiode subarray; The intermediate pn diode layer material pattern is separated from the micro diode sub-array by a trench.

11. The optoelectronic structure of claim 10, wherein a minimum width of the intermediate pn diode layer material pattern laterally located between immediately adjacent microdiodes of the microdiode subarray is greater than a minimum width of the immediately adjacent microdiodes.

12. The photovoltaic structure of claim 10, wherein: The coupon also includes a reflector layer subarray conformally wrapped around the microdiode subarray and a portion of the intermediate pn diode layer material pattern; And each reflector layer includes a corresponding landing pad of the landing pad array.

13. The optoelectronic structure of claim 10, further comprising an opaque top electrode layer spanning over the intermediate pn diode layer material pattern.

14. The photovoltaic structure of claim 13, further comprising an opening through the pn diode layer, and a back contact layer located within the opening and in electrical contact with the top electrode layer.

15. The optoelectronic structure of claim 14, wherein the back contact layer is electrically connected to a supplemental via contact, and the supplemental via contact is electrically connected to a contact pad of the contact pad array.

16. The optoelectronic structure of claim 15, wherein the supplemental via contact is connected to a reflector layer of the reflector layer subarray.

17. An optoelectronic structure according to claim 5, wherein the placement distribution of the landing pad array on the backplane is characterized by the first-order standard deviation of the displacement values ​​of the landing pad array to the contact pad array, and the position distribution of the via contact array on the backplane is characterized by the first-order standard deviation of the displacement values ​​of the via contact array to the corresponding contact pad array, and the first-order standard deviation for the placement distribution of the landing pad array on the backplane is greater than the first-order standard deviation for the position distribution of the via contact array on the backplane.

18. The optoelectronic structure of claim 5, further comprising a plurality of dummy vias adjacent to the array of via contacts.

19. The optoelectronic structure of claim 18, wherein the plurality of dummy vias do not vertically overlap the plurality of coupons.

20. The optoelectronic structure of claim 1, wherein the microdiodes of the microdiode array are light emitting diodes (LEDs).

21. The optoelectronic structure of claim 1, wherein the microdiodes of the microdiode array are photodetectors (PDs).

22. The optoelectronic structure of claim 1, wherein the driver circuit comprises a CMOS driver circuit.

23. The optoelectronic structure of claim 1, wherein the drive circuit comprises an array of pixel driver chips.

24. The optoelectronic structure of claim 1, wherein the microdiode comprises a regrown microdiode subarray, each regrown microdiode comprising a p-doped layer, an n-doped layer, an active layer between the p-doped layer and the n-doped layer, and a regrown layer spanning the side walls of the p-doped layer, the active layer, and the n-doped layer.

25. A method of assembling an optoelectronic structure, the method comprising: patterning a micro diode array as a pn diode layer on a growth substrate; forming a landing pad array on top of the micro diode array; transferring the microdiode array and the landing pad array to a first carrier substrate; cutting the micro diode array, the landing pad array and the first carrier substrate into a plurality of coupons, each coupon comprising a micro diode sub-array and a landing pad sub-array; reconstructing the array of coupons on a second carrier substrate to form a reconstructed substrate; hybrid bonding the reconstructed substrate to a backplane; and Cutting multiple optoelectronic structures.

26. The method of claim 25, wherein the first carrier substrate, the second carrier substrate, and the backplane each comprise a silicon wafer.

27. The method of claim 25, wherein reconstructing the coupon array on the second carrier substrate comprises die-to-wafer bonding the coupon array to the second carrier substrate.

28. The method of claim 27, wherein hybrid bonding the reconstituted substrate to the backplane comprises wafer-to-wafer bonding.

29. The method of claim 25, wherein the backplane comprises CMOS driver circuitry.

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