Circuit board and method of manufacturing the same

Abstract

A circuit board and a manufacturing method thereof, the method comprising providing a main board, the main board comprising a first base layer, a first circuit pattern layer and a second circuit pattern layer, the first circuit pattern layer being located in a current transmission area, the second circuit pattern layer being located in an electromagnetic transmission area, then providing a sub-board, the sub-board comprising a second base layer and a third circuit pattern layer, then pre-pressing the main board and the sub-board, so that the third circuit pattern layer is located on part of the second circuit pattern layer to form a laminated structure, then hot-pressing the main board and the sub-board, so that the second base layer is transformed from a glass state to a molten liquid state and flows towards the laminated structure to coat the laminated structure. The advantage of the present application is that after the sub-board is pressed on the main board, multiple electroplating is not required, thereby effectively shortening the production time.

Description

Technical Field

[0001] This invention relates to a circuit board with current transmission and electromagnetic transmission functions and a method for manufacturing the same. Background Technology

[0002] Wireless charging is gaining popularity in the consumer electronics market and is a mainstream trend for future development. This poses challenges to the delivery cycle and process capabilities of printed circuit boards.

[0003] Currently, the general manufacturing method for circuit boards with Universal Serial Bus (USB) area and wireless charging area is drilling, electroplating, etching, multiple electroplating, and applying a protective film (CVL).

[0004] However, current PCB manufacturing processes have the following problems: 1. The wireless charging area requires multiple electroplating processes to meet the copper thickness (i.e., line thickness) requirements, and there are thickness limitations for electroplated copper, resulting in long and cumbersome manufacturing times. 2. The uniformity of electroplated copper in the wireless charging area is poor, and the distance between lines is too large. 3. The flowability of the cover film (CVL) is limited, and air bubbles may be generated during filling, which may affect reliability testing.

[0005] Therefore, how to solve the above problems is a focus of attention for those in this field. Summary of the Invention

[0006] One aspect of the present invention is to provide a circuit board with current transmission and electromagnetic transmission functions and a method for manufacturing the same, in order to solve the problems caused by the aforementioned prior art.

[0007] According to one embodiment of the present invention, a method for manufacturing a circuit board includes the following steps: providing a main board, the main board including a first base layer, a first circuit pattern layer and a second circuit pattern layer, the first base layer including a current transmission region and an electromagnetic transmission region adjacent to each other, the first circuit pattern layer being located in the current transmission region and the second circuit pattern layer being located in the electromagnetic transmission region; providing a sub-board, the sub-board including a second base layer and a third circuit pattern layer disposed on the second base layer; performing a pre-pressing process on the main board and the sub-board, such that the third circuit pattern layer forms a stacked structure on a portion of the second circuit pattern layer; performing a hot-pressing process on the main board and the sub-board, such that the second base layer changes from a glassy state to a molten liquid state and flows toward the stacked structure and covers the stacked structure.

[0008] According to one or more embodiments of the present invention, the first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, and the third circuit pattern layer includes a plurality of third circuits. Each second circuit includes a trapezoidal bump, and each third circuit includes an arcuate groove. During the pre-pressing process of the motherboard and the sub-board, the arcuate grooves of the plurality of third circuits are located on a portion of the trapezoidal bumps of the plurality of second circuits. A portion of each trapezoidal bump is located in the corresponding arcuate groove, and there is a gap between each trapezoidal bump and the corresponding arcuate groove.

[0009] According to one or more embodiments of the present invention, during the hot-pressing process of the main board and the sub-board, the arc-shaped groove of each third line and the trapezoidal protrusion of the corresponding second line are combined with each other, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal protrusion.

[0010] According to one or more embodiments of the present invention, the arcuate groove of each of the third lines and the trapezoidal protrusion of the corresponding second line are joined to each other by diffusion welding.

[0011] According to one or more embodiments of the present invention, before the pre-pressing process of the motherboard and the sub-board described above, the following steps are further included: forming a first metal layer on the second circuit pattern layer; and forming a second metal layer on the third circuit pattern layer; during the hot pressing process of the motherboard and the sub-board, the first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump, the arc-shaped groove of each third circuit is bonded to each other with the trapezoidal bump of the corresponding second circuit through the eutectic metal layer, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

[0012] According to one or more embodiments of the present invention, the above-mentioned method for manufacturing the sub-board includes the following steps: providing a second substrate, the second substrate including a second base layer and a metal layer, the second base layer including an upper surface and a lower surface opposite to each other, the metal layer being disposed on the lower surface; etching the metal layer to form a patterned metal layer on the lower surface of the second base layer; and forming a third electroplated metal layer on the patterned metal layer to form a third circuit pattern layer.

[0013] According to one or more embodiments of the present invention, the first base layer includes a first surface and a second surface opposite to each other, the first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer, the first upper circuit pattern layer and the first lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the current transmission region, the second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer, the second upper circuit pattern layer and the second lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the electromagnetic transmission region, and during the pre-pressing process, a third circuit pattern layer is located on the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer form a stacked structure.

[0014] According to another embodiment of the present invention, a circuit board includes a main board and a sub-board. The main board includes a first base layer, a first circuit pattern layer, and a second circuit pattern layer. The first base layer includes adjacent current transmission regions and electromagnetic transmission regions. The first circuit pattern layer is located in the current transmission region, and the second circuit pattern layer is located in the electromagnetic transmission region. The sub-board includes a second base layer and a third circuit pattern layer disposed on the second base layer. The third circuit pattern layer and a portion of the second circuit pattern layer form a stacked structure, and the second base layer covers the stacked structure.

[0015] According to one or more embodiments of the present invention, the first circuit pattern layer includes a plurality of first circuits, the second circuit pattern layer includes a plurality of second circuits, and the third circuit pattern layer includes a plurality of third circuits. Each second circuit includes a trapezoidal bump, and each third circuit includes an arcuate groove.

[0016] According to one or more embodiments of the present invention, the arcuate grooves of the plurality of third lines correspond to the trapezoidal protrusions of the plurality of second lines, a portion of each trapezoidal protrusion is located in the corresponding arcuate groove, and there is a gap between each trapezoidal protrusion and the corresponding arcuate groove, and a portion of the second base layer is located in the gap between the arcuate groove and the trapezoidal protrusion.

[0017] According to one or more embodiments of the present invention, the motherboard further includes a first metal layer, and the sub-board further includes a second metal layer. The first metal layer is disposed on a second circuit pattern layer, and the second metal layer is disposed on a third circuit pattern layer. The first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump.

[0018] According to one or more embodiments of the present invention, the first base layer includes a first surface and a second surface opposite to each other, the first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer, the first upper circuit pattern layer and the first lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the current transmission region, the second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer, the second upper circuit pattern layer and the second lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the electromagnetic transmission region, the third circuit pattern layer corresponds to the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer form a stacked structure. Attached Figure Description

[0019] The accompanying drawings illustrate one or more embodiments of this disclosure and, together with the written description, serve to explain the principles of this disclosure. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein:

[0020] Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0021] Figure 2 for Figure 1 A top view of the electromagnetic transmission area of ​​the circuit board shown.

[0022] Figure 3 This is a cross-sectional view of a circuit board according to another embodiment of the present invention.

[0023] Figures 4A to 4J for Figure 1 The diagram shows a flowchart of the circuit board manufacturing process.

[0024] Figures 5A to 5F for Figure 3 The diagram shows a flowchart of the circuit board manufacturing process. Detailed Implementation

[0025] The following description, with reference to the accompanying drawings, discloses several embodiments of the present invention. For clarity, many practical details will be described in the following description. However, those skilled in the art will understand that these practical details are not essential in some embodiments of the present invention and are therefore not intended to limit the invention. Furthermore, for the sake of simplicity, some conventionally used structures and elements are illustrated in a simplified schematic manner in the drawings. Additionally, for ease of viewing, the dimensions of the elements in the drawings are not drawn to scale.

[0026] Please see Figure 1 and Figure 2 , Figure 1 This is a cross-sectional view of a circuit board according to an embodiment of the present invention. Figure 2 for Figure 1A top view of the electromagnetic transmission area of ​​the circuit board shown.

[0027] like Figure 1 As shown, the circuit board 1 in this embodiment includes a main board 11 and a sub-board 12. The main board 11 includes a first base layer 110, a first circuit pattern layer 111, and a second circuit pattern layer 112. The first base layer 110 includes a current transmission region R1 and an electromagnetic transmission region R2 adjacent to each other. The first circuit pattern layer 111 is disposed on the first base layer 110 and located within the current transmission region R1. The second circuit pattern layer 112 is disposed on the first base layer 110 and located within the electromagnetic transmission region R2. The sub-board 12 includes a second base layer 120 and a third circuit pattern layer 121 disposed on the second base layer 120. In this embodiment, the third circuit pattern layer 121 and a portion of the second circuit pattern layer 112 form a stacked structure L, and the second base layer 120 covers the stacked structure L formed by the third circuit pattern layer 121 and a portion of the second circuit pattern layer 112.

[0028] In this embodiment, the first circuit pattern layer 111 includes a plurality of first circuits 1110. The second circuit pattern layer 112 includes a plurality of second circuits 1120, and each second circuit 1120 of the second circuit pattern layer 112 includes a trapezoidal bump C1. The third circuit pattern layer 121 includes a plurality of third circuits 1210, and each third circuit 1210 of the third circuit pattern layer 121 includes an arcuate groove C2.

[0029] As described above, in this embodiment, the third circuit pattern layer 121 of the sub-board 12 corresponds to the second circuit pattern layer 112 of the main board 11, and a portion of the trapezoidal bump C1 of each second circuit 1120 is located within the arcuate groove C2 of the corresponding third circuit 1210, with a gap G between the arcuate groove C2 and the trapezoidal bump C1. In this embodiment, each trapezoidal bump C1 contacts the corresponding arcuate groove C2, that is, after each trapezoidal bump C1 extends into the corresponding arcuate groove C2, the two ends of the trapezoidal bump C1 will contact the arcuate groove C2.

[0030] In this embodiment, the material of the first base layer 110 is, for example, polyimide (PI), but the present invention is not limited thereto. In other embodiments, the material of the first base layer 110 may also be selected from polyethylene terephthalate (PET) and polyethylene naphthalate (PEN).

[0031] In this embodiment, the material of the second base layer 120 is, for example, liquid crystal polymer (LCP), but the present invention is not limited thereto.

[0032] The following is a further detailed description of the other structures of the circuit board 1 in this embodiment.

[0033] like Figure 1 As shown, in this embodiment, the second base layer 120 of the sub-plate 12 covers the stacked structure L formed by the third circuit pattern layer 121 and a portion of the second circuit pattern layer 112, and a portion of the second base layer 120 is located in the gap G between the arcuate groove C2 of each third circuit 1210 and the trapezoidal protrusion C1 of the corresponding second circuit 1120.

[0034] In detail, the first base layer 110 of this embodiment includes a first surface 1101 and a second surface 1102 opposite to each other. The first circuit pattern layer 111 includes a first upper circuit pattern layer 1111 and a first lower circuit pattern layer 1112. The first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 are respectively disposed on the first surface 1101 and the second surface 1102 and located within the current transmission region R1. The second circuit pattern layer 112 includes a second upper circuit pattern layer 1121 and a second lower circuit pattern layer 1122. The second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122 are respectively disposed on the first surface 1101 and the second surface 1102 and located within the electromagnetic transmission region R2.

[0035] In this embodiment, the third circuit pattern layer 121 of the sub-board 12 corresponds to the second upper circuit pattern layer 1121 located within the electromagnetic transmission region R2. That is, the third circuit pattern layer 121 and the second upper circuit pattern layer 1121 constitute the aforementioned stacked structure L. It should be specifically noted that after the third circuit pattern layer 121 and the second upper circuit pattern layer 1121 within the electromagnetic transmission region R2 constitute the stacked structure L, the thickness of the stacked structure L is greater than that of the first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 located within the current transmission region R1. Furthermore, the aforementioned stacked structure L is configured as follows: Figure 2 The coil structure shown.

[0036] like Figure 1 As shown, the circuit board 1 in this embodiment also includes a cover film 13. The cover film 13 is adhered to the first upper circuit pattern layer 1111 of the first circuit pattern layer 111. Specifically, the cover film 13 in this embodiment includes an insulating layer 131 and an adhesive layer 132. The adhesive layer 132 is located between the insulating layer 131 and the first upper circuit pattern layer 1111. The insulating layer 131 is adhered to the first upper circuit pattern layer 1111 through the adhesive layer 132.

[0037] like Figure 1As shown, each second line 1120 of the second line pattern layer 112 in this embodiment has a top surface S1, a bottom surface S2, a first inclined surface S3, and a second inclined surface S4. The top surface S1 and the bottom surface S2 of the second line 1120 are opposite to each other, the first inclined surface S3 and the second inclined surface S4 are connected between the top surface S1 and the bottom surface S2, and the first inclined surface S3 and the second inclined surface S4 are inclined towards each other.

[0038] In this embodiment, the top surface S1, bottom surface S2, first inclined surface S3, and second inclined surface S4 of the second line 1120 together form a trapezoidal protrusion C1. The top surface S1 has a first width W1, and the bottom surface S2 has a second width W2, with the second width W2 being greater than the first width W1. Therefore, the lower line width of the second line 1120 is greater than the upper line width. Under this structural design, when the thickness of the second line 1120 is 35 μm, the minimum line spacing between any two adjacent second lines 1120 is 65 μm.

[0039] like Figure 1 As shown, each third line 1210 of the third line pattern layer 121 in this embodiment has a bottom surface F1, a first side surface F2, and a second side surface F3. The bottom surface F1 of the third line 1210 is opposite to the arc-shaped groove C2, and the first side surface F2 and the second side surface F3 are connected between the bottom surface F1 and the arc-shaped groove C2. In this embodiment, there is a third width W3 between the first side surface F2 and the second side surface F3, and the third width W3 is equal to the second width W2 and greater than the first width W1.

[0040] Therefore, the line width of the third line 1210 is equal to the lower line width of the second line 1120, and the line width of the third line 1210 is greater than the upper line width of the second line 1120. Under this structural design, when the thickness of the third line 1210 is 35μm, the minimum line spacing between any two adjacent third lines 1210 is 65μm.

[0041] Please see Figure 3 This is a cross-sectional structural diagram of a circuit board according to another embodiment of the present invention.

[0042] like Figure 3 As shown, the circuit board 1a in this embodiment and Figure 1The circuit board 1 shown has a similar structure, but the difference lies in that the main board 11a in this embodiment further includes a first metal layer 113, and the sub-board 12a further includes a second metal layer 114. The first metal layer 113 is disposed on the second circuit pattern layer 112, meaning the first metal layer 113 is formed on the outer surface of each second circuit 1120 of the second circuit pattern layer 112. The second metal layer 114 is disposed on the third circuit pattern layer 121, meaning the second metal layer 114 is formed on the outer surface of each third circuit 1210 of the third circuit pattern layer 121. In this embodiment, the first metal layer 113 and the second metal layer 114 form a eutectic metal layer 115 within the gap G between the arcuate groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120.

[0043] In this embodiment, the first metal layer 113 is, for example, gold (Au) or silver (Ag), but the invention is not limited thereto. The second metal layer 114 is, for example, tin (Sn) or nickel-gold, but the invention is not limited thereto.

[0044] The manufacturing process of circuit board 1 in this embodiment will be further described below.

[0045] Please see Figures 4A to 4J , it is Figure 1 The diagram shows a flowchart of the circuit board manufacturing process.

[0046] like Figures 4A to 4J As shown, and please refer to the following: Figure 1 The method for manufacturing circuit board 1 in this embodiment includes the following steps: First, as... Figure 4A As shown, a first substrate 100 is provided. The first substrate 100 includes a first base layer 110, a first metal layer 101, and a second metal layer 102. The first metal layer 101 is disposed on a first surface 1101 of the first base layer 110, and the second metal layer 102 is disposed on a second surface 1102 of the first base layer 110. Then, as... Figure 4B As shown, a through-hole 103 is formed in the first substrate 100, and the through-hole 103 penetrates the first base layer 110 and the second metal layer 102; then, as Figure 4C As shown, a first electroplated metal layer 104 is formed on the surface of the first metal layer 101 away from the first base layer 110, and a second electroplated metal layer 105 is formed on the surface of the second metal layer 102 away from the first base layer 110. The second electroplated metal layer 105 extends into the through hole 103 and contacts the first metal layer 101.

[0047] It should be noted that the first substrate 100 in this embodiment may be a double-sided copper-clad substrate, that is, the first metal layer 101 and the second metal layer 102 may be, for example, copper foil layers. However, the present invention is not limited thereto. In other embodiments, the first substrate 100 may also be a single-sided copper-clad substrate. In addition, the first electroplated metal layer 104 and the second electroplated metal layer 105 may be, for example, electroplated copper layers. However, the present invention is not limited thereto.

[0048] Next, as Figure 4D As shown, the stacked structure formed by the first metal layer 101 and the first electroplated metal layer 104, and the stacked structure formed by the second metal layer 102 and the second electroplated metal layer 105 are etched to form a first upper circuit pattern layer 1111 and a first lower circuit pattern layer 1112 on a portion of the first surface 1101 and a portion of the second surface 1102 of the first base layer 110, respectively, and a second upper circuit pattern layer 1121 and a second lower circuit pattern layer 1122 on another portion of the first surface 1101 and another portion of the second surface 1102 of the first base layer 110, respectively. Next, as... Figure 4E As shown, a cover film 13 is bonded to the first upper circuit pattern layer 1111.

[0049] In this embodiment, the first upper circuit pattern layer 1111 and the first lower circuit pattern layer 1112 constitute the first circuit pattern layer 111, and the second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122 constitute the second circuit pattern layer 112. Since the appearance shape of each first line 1110 in the first circuit pattern layer 111 is different from the appearance shape of each second line 1120 in the second circuit pattern layer 112, two functionally different current transmission regions R1 and electromagnetic transmission regions R2 are defined on the first base layer 110. For example, the current transmission region R1 is a region with USB transmission function, and the electromagnetic transmission region R2 is a region with wireless charging function.

[0050] At Figures 4A to 4E After the steps are completed, it will form as follows Figure 1 The structure of the motherboard 11 shown.

[0051] Next, as Figure 4F As shown, a second substrate 200 is provided, which includes a second base layer 120 and a metal layer 201. The second base layer 120 includes an upper surface 1201 and a lower surface 1202 opposite to each other, and the metal layer 201 is disposed on the lower surface 1202 of the second base layer 120. Next, as shown in Figure 4G, the metal layer 201 is etched to form a patterned metal layer 202 on the lower surface 1202 of the second base layer 120; next, as shown in Figure 4H, a third electroplated metal layer 203 is formed on the patterned metal layer 202 to form a third circuit pattern layer 121 having an arc-shaped groove C2.

[0052] It should be noted that, at Figure 4H In the manufacturing process, an arc-shaped groove C2 can be formed on the third electroplated metal layer 203 by adjusting the ratio of copper sulfate to sulfuric acid in the copper plating solution. The depth of this arc-shaped groove C2 can be further controlled. Therefore, after electroplating, each third line 1210 of the third circuit pattern layer 121 has an arc-shaped groove C2, meaning that each third line 1210 has an appearance similar to an arched bridge-shaped recess. For example, in this embodiment, the copper plating solution formula is copper sulfate (CuSO4·5H2O), sulfuric acid (H2SO4), and chloride ions (Cl). - Before adjusting the formulation ratio of the copper plating solution, the components were: copper sulfate 225–245 g / L, sulfuric acid 30–50 ml / L, chloride ions 60–80 ppm, brightener 15–25 ml / L, inhibitor 2–4 ml / L, and leveling agent 15–25 ml / L. After adjusting the formulation ratio, the components were: copper sulfate 150–220 g / L, sulfuric acid 40–100 ml / L, chloride ions 60–80 ppm, brightener 15–25 ml / L, inhibitor 2–4 ml / L, and leveling agent 10–20 ml / L.

[0053] At Figures 4F to 4H After the steps are completed, it will form as follows Figure 1 The structure of the sub-plate 12 shown.

[0054] Next, as Figure 4I As shown, the motherboard 11 and the sub-board 12 are pre-pressed so that the third circuit pattern layer 121 on the sub-board 12 corresponds to a portion of the second circuit pattern layer 112 on the motherboard 11. That is, the third circuit pattern layer 121 corresponds to the second upper circuit pattern layer 1121 and forms a stacked structure L. A portion of the trapezoidal bump C1 of each second circuit 1120 is located in the arc-shaped groove C2 of the corresponding third circuit 1210 for positioning. A gap G is formed between each arc-shaped groove C2 and the corresponding trapezoidal bump C1.

[0055] Then, as Figure 4J As shown, the motherboard 11 and the sub-board 12 are subjected to a hot-pressing process, so that the arc-shaped groove C2 of each third circuit 1210 and the trapezoidal bump C1 of the corresponding second circuit 1120 are welded together. During the hot-pressing process, the second base layer 120 changes from a glassy state to a molten liquid state and flows towards the stacked structure L, covering the stacked structure L. Furthermore, the second base layer 120 flows into the gap G between the arc-shaped groove C2 and the trapezoidal bump C1, thereby forming a structure as shown. Figure 1 The structure of circuit board 1 shown.

[0056] It should be noted that, in this embodiment, the material of the second base layer 120 is, for example, a thermoplastic dielectric material. Specifically, the second base layer 120 can be made of liquid crystal polymer (LCP). Liquid crystal polymer has fluidity at high temperatures. During the hot-pressing process, the liquid crystal polymer transforms from a glassy state to a molten liquid state, thereby encapsulating each third line 1210 and its corresponding second line 1120, and further filling the gap G between the arcuate groove C2 of each third line 1210 and the trapezoidal protrusion C1 of the corresponding second line 1120. Furthermore, soft magnetic ferrite is added to the liquid crystal polymer to shield against external electromagnetic interference and to reduce magnetic resistance.

[0057] It should be noted that, in this embodiment, during the hot-pressing process between the main board 11 and the sub-board 12, the arc-shaped groove C2 of each third line 1210 and the trapezoidal bump C1 of the corresponding second line 1120 are bonded to each other, for example, by diffusion bonding technology, but the present invention is not limited thereto. Furthermore, filling the gap G between each third line 1210 and the corresponding second line 1120 with liquid crystal polymer material can also increase the bonding strength between each third line 1210 and the corresponding second line 1120.

[0058] It is worth mentioning that, in this embodiment, since the line width of the third line 1210 is greater than the upper line width of the second line 1120, and each third line 1210 of the sub-board 12 has an arc-shaped groove C2, during the pre-pressing process, the top of the trapezoidal protrusion C1 of each second line 1120 will be confined within the corresponding arc-shaped groove C2. Even if the second line 1120 and the third line 1210 are not accurately aligned, the subsequent hot pressing process can still be carried out, and each third line 1210 can be combined with the corresponding second line 1120 by diffusion welding, effectively preventing the main board 11 and the sub-board 12 from shifting to each other during the hot pressing process.

[0059] It is worth mentioning that, after the main board 11 and the sub-board 12 are hot-pressed together in this embodiment, the line spacing in the electromagnetic transmission area R2 (wireless charging area) is about 65 μm when the line thickness is 70 μm. Compared with the prior art process of multiple electroplating of lines in the wireless charging area, the line spacing is about 135 μm when the line thickness in the wireless charging area is 70 μm. That is to say, with the same thickness, the line spacing of the embodiment of the present invention is reduced by 50% compared with the prior art process of multiple electroplating of lines. In addition, the line thickness in the wireless charging area of ​​the embodiment of the present invention can be higher than the line thickness of the prior art process of multiple electroplating of lines. The higher the thickness, the greater the current. Since the prior art process of multiple electroplating of lines is limited by the thickness and filling properties of the dry film, it is not possible to further increase the line thickness.

[0060] Please see Figures 5A to 5F , it is Figure 3 The diagram shows a flowchart of the circuit board manufacturing process.

[0061] like Figures 5A to 5F As shown, and please refer to the following: Figure 3 The method for manufacturing circuit board 1a in this embodiment includes the following steps: First, as... Figure 5A As shown, a motherboard 11a is provided. The motherboard 11a includes a first base layer 110, a first circuit pattern layer 111, a second circuit pattern layer 112, and a cover film 13. The first base layer 110 includes adjacent current transmission regions R1 and electromagnetic transmission regions R2. The first circuit pattern layer 111 is located in the current transmission region R1, and the second circuit pattern layer 112 is located in the electromagnetic transmission region R2. The first circuit pattern layer 111 includes a plurality of first circuits 1110, and the second circuit pattern layer 112 includes a plurality of second circuits 1120, and each second circuit 1120 includes a trapezoidal bump C1. The cover film 13 is attached to the first upper circuit pattern layer 1111 of the first circuit pattern layer 1111.

[0062] Next, as Figure 5B As shown, a sub-board 12a is provided. The sub-board 12a includes a second base layer 120 and a third circuit pattern layer 121 disposed on the second base layer 120. The third circuit pattern layer 121 includes a plurality of third circuits 1210, and the first third circuit 1210 includes an arc-shaped groove C2.

[0063] It should be noted that the detailed manufacturing method of the motherboard 11a in this embodiment is the same as that in the previous embodiment. Figures 4A to 4F The manufacturing process steps shown are the same, so they will not be repeated. The detailed manufacturing method of the sub-plate 12a in this embodiment is the same as... Figures 4G to 4I The production method and steps shown are the same, so they will not be repeated.

[0064] Next, as Figure 5C As shown, a first metal layer 113 is formed on the second circuit pattern layer 112 of the motherboard 11a, that is, the first metal layer 113 is formed simultaneously on the second upper circuit pattern layer 1121 and the second lower circuit pattern layer 1122. Next, as... Figure 5D As shown, a second metal layer 114 is formed on the third circuit pattern layer 121 of the sub-board 12a.

[0065] Next, as Figure 5E As shown, the motherboard 11a and the sub-board 12a are pre-pressed so that the third circuit pattern layer 121 on the sub-board 12a corresponds to a portion of the second circuit pattern layer 112 on the motherboard 11a. That is, the third circuit pattern layer 121 corresponds to the second upper circuit pattern layer 1121 and forms a stacked structure L. The trapezoidal bump C1 of each second circuit 1120 is positioned in the arc-shaped groove C2 of the corresponding third circuit 1210, and a gap G is formed between each arc-shaped groove C2 and the corresponding trapezoidal bump C1.

[0066] Next, as Figure 5F As shown, the motherboard 11a and the sub-board 12a are subjected to a hot-pressing process, so that the first metal layer 113 and the second metal layer 114 form a eutectic metal layer 115 in the gap G between the arc-shaped groove C2 and the trapezoidal bump C1. The arc-shaped groove C2 of each third line 1210 is bonded to the corresponding trapezoidal bump C1 of the second line 1120 through the eutectic metal layer 115. During the hot-pressing process, the second base layer 120 changes from a glassy state to a molten liquid state and flows towards the direction of the stacked structure L and covers the stacked structure L. The second base layer 120 further flows into the gap G between the arc-shaped groove C2 and the trapezoidal bump C1, thereby forming the structure as shown. Figure 3 The structure of circuit board 1a shown.

[0067] It should be noted that in this embodiment, since the first metal layer 113 and the second metal layer 114 will still generate multiple small pores in the gap G between the arc-shaped groove R2 and the trapezoidal protrusion C1 when the second base layer 120 changes from a glassy state to a molten liquid state and flows into the gap G between the arc-shaped groove R2 and the trapezoidal protrusion C1, the liquid second base layer 120 will fill these small pores and prevent bubbles from forming in the gap G.

[0068] In summary, this invention provides a method for manufacturing a circuit board with USB transmission and wireless charging functions. Specifically, it provides a main board and a secondary board coated with liquid crystal polymer (LCP). The secondary board is pressed onto the electromagnetic transmission area of ​​the main board (i.e., the area with wireless charging function) using a thermo-pressing process to manufacture the circuit board. This replaces the existing technology that requires multiple electroplating processes on the main board to increase copper content. The advantages of this circuit board manufacturing method are that multiple electroplating is not required after pressing the secondary board onto the main board, effectively shortening production time. Furthermore, the etched lines on the secondary board exhibit better uniformity and smaller line spacing compared to existing copper-enhancing processes on the main board. The liquid crystal polymer (LCP) flows at high temperatures, filling gaps and reducing air bubbles. Additionally, the addition of soft magnetic ferrite to the LCP provides magnetic shielding and magnetic resistance reduction.

[0069] The selected and illustrated embodiments are intended to explain the content of this disclosure and their practical application, thereby inspiring others skilled in the art to utilize this disclosure and various embodiments, and to make various modifications to suit a particular intended use. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of this disclosure is defined by the appended claims, and not by the foregoing description and the exemplary embodiments described therein.

[0070] [Symbol Explanation]

[0071] 1, 1a: Circuit board

[0072] 11, 11a: Motherboard

[0073] 12, 12a: Sub-plate

[0074] 13: Covering film

[0075] 100: First substrate

[0076] 101: First metal layer

[0077] 102: Second metal layer

[0078] 103: Through hole

[0079] 104: First electroplated metal layer

[0080] 105: Second electroplated metal layer

[0081] 110: The First Grassroots Unit

[0082] 111: First line pattern layer

[0083] 112: Second line pattern layer

[0084] 113: First metal layer

[0085] 114: Second metal layer

[0086] 115: Eutectic metal layer

[0087] 120: Second grassroots

[0088] 121: Third line pattern layer

[0089] 131: Insulation layer

[0090] 132: Adhesive layer

[0091] 200: Second substrate

[0092] 201: Metal layer

[0093] 202: Patterned Metal Layer

[0094] 203: Third electroplated metal layer

[0095] 1101: First Surface

[0096] 1102: Second Surface

[0097] 1110: Route 1

[0098] 1111: First upper circuit pattern layer

[0099] 1112: First lower circuit pattern layer

[0100] 1120: Second Line

[0101] 1121: Second upper line pattern layer

[0102] 1122: Second lower line pattern layer

[0103] 1201: Upper surface

[0104] 1202: Lower surface

[0105] 1210: Third Line

[0106] C1: Trapezoidal bump

[0107] C2: Arc-shaped groove

[0108] F1: Bottom surface

[0109] F2: First side view

[0110] F3: Second side

[0111] G: Gap

[0112] L: Layered structure

[0113] R1: Current transmission region

[0114] R2: Electromagnetic transmission area

[0115] S1: Top surface

[0116] S2: Bottom surface

[0117] S3: First inclined surface

[0118] S4: Second inclined surface

[0119] W1: First width

[0120] W2: Second width

[0121] W3: Third width.

Claims

1. A method for manufacturing a circuit board, characterized in that, Includes the following steps: A motherboard is provided, the motherboard including a first base layer, a first circuit pattern layer and a second circuit pattern layer, the first base layer including a current transmission region and an electromagnetic transmission region adjacent to each other, the first circuit pattern layer being located in the current transmission region and the second circuit pattern layer being located in the electromagnetic transmission region; A sub-board is provided, the sub-board including a second base layer and a third circuit pattern layer disposed on the second base layer; The motherboard and the sub-board undergo a pre-pressing process, such that the third circuit pattern layer forms a stacked structure with respect to a portion of the second circuit pattern layer; and The motherboard and the sub-board are subjected to a hot-pressing process, which causes the second base layer to change from a glassy state to a molten liquid state and flow toward the stacked structure and cover the stacked structure.

2. The method for manufacturing a circuit board according to claim 1, characterized in that, The first circuit pattern layer includes multiple first circuits, the second circuit pattern layer includes multiple second circuits, and the third circuit pattern layer includes multiple third circuits. Each second circuit includes a trapezoidal bump, and each third circuit includes an arc-shaped groove. During the pre-pressing process of the motherboard and the sub-board, the arc-shaped grooves of the multiple third circuits are located on a portion of the trapezoidal bumps of the multiple second circuits. A portion of each trapezoidal bump is located within the corresponding arc-shaped groove, and there is a gap between each trapezoidal bump and the corresponding arc-shaped groove.

3. The method for manufacturing a circuit board according to claim 2, characterized in that, During the hot-pressing process between the motherboard and the sub-board, the arc-shaped groove of each third circuit and the trapezoidal protrusion of the corresponding second circuit are coupled to each other, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal protrusion.

4. The method for manufacturing a circuit board according to claim 3, characterized in that, The arcuate groove of each of the third lines is joined to the trapezoidal protrusion of the corresponding second line by diffusion welding.

5. The method for manufacturing a circuit board according to claim 2, characterized in that, Before the pre-pressing process is performed on the motherboard and the sub-board, the following steps are also included: A first metal layer is formed on the second circuit pattern layer; and A second metal layer is formed on the third circuit pattern layer; During the hot-pressing process between the motherboard and the subboard, the first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump. The arc-shaped groove of each third circuit is bonded to the trapezoidal bump of the corresponding second circuit through the eutectic metal layer, and the second base layer flows into the gap between the arc-shaped groove and the trapezoidal bump.

6. A circuit board, characterized in that, include: The motherboard includes a first base layer, a first circuit pattern layer, and a second circuit pattern layer. The first base layer includes a current transmission region and an electromagnetic transmission region that are adjacent to each other. The first circuit pattern layer is located in the current transmission region, and the second circuit pattern layer is located in the electromagnetic transmission region. as well as The sub-board includes a second base layer and a third circuit pattern layer disposed on the second base layer, wherein the third circuit pattern layer and a portion of the second circuit pattern layer form a stacked structure, and the second base layer covers the stacked structure.

7. The circuit board according to claim 6, characterized in that, The first line pattern layer includes a plurality of first lines, the second line pattern layer includes a plurality of second lines, and the third line pattern layer includes a plurality of third lines. Each second line includes a trapezoidal bump, and each third line includes an arc-shaped groove.

8. The circuit board according to claim 7, characterized in that, The arc-shaped grooves of the plurality of third lines correspond to the trapezoidal protrusions of the plurality of second lines. A portion of each trapezoidal protrusion is located within the corresponding arc-shaped groove, and there is a gap between each trapezoidal protrusion and the corresponding arc-shaped groove. A portion of the second base layer is located within the gap between the arc-shaped groove and the trapezoidal protrusion.

9. The circuit board according to claim 8, characterized in that, The motherboard further includes a first metal layer, and the sub-board further includes a second metal layer. The first metal layer is disposed on the second circuit pattern layer, and the second metal layer is disposed on the third circuit pattern layer. The first metal layer and the second metal layer form a eutectic metal layer in the gap between the arc-shaped groove and the trapezoidal bump.

10. The circuit board according to claim 6, characterized in that, The first base layer includes a first surface and a second surface opposite to each other. The first circuit pattern layer includes a first upper circuit pattern layer and a first lower circuit pattern layer. The first upper circuit pattern layer and the first lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the current transmission region. The second circuit pattern layer includes a second upper circuit pattern layer and a second lower circuit pattern layer. The second upper circuit pattern layer and the second lower circuit pattern layer are respectively disposed on the first surface and the second surface and located in the electromagnetic transmission region. The third circuit pattern layer corresponds to the second upper circuit pattern layer, and the third circuit pattern layer and the second upper circuit pattern layer constitute the stacked structure.

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