Preparation method of island and beam membrane structure micro differential pressure sensor with IC

Abstract

The invention provides a preparation method of an island and beam film structure micro differential pressure sensor with an IC (Integrated Circuit), which comprises the following steps: arranging an N-type buried layer, a P-type buried layer and an island film structure on an SOI (Silicon On Insulator) silicon wafer, then connecting the SOI silicon wafer with a double-parabolic silicon wafer, and arranging a medium isolation groove, an N-type buried layer connecting region, a P well, a P-type buried layer connecting region, a sensitive resistor, a P-type base region, an N-type base region, an N-type emitter region and a P-type emitter region on the SOI silicon wafer. According to the invention, the preparation of the complementary bipolar transistor double-buried layer is completed by combining a semiconductor manufacturing technology and an MEMS manufacturing technology under the condition of not using an epitaxial process; the process flow is integrally simplified, and the preparation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and specifically to a method for fabricating a micro differential pressure sensor with an island and beam film structure with an IC. Background Art

[0002] The MEMS pressure chip is an important achievement in the application and development of microelectromechanical system (MEMS) technology. It is a new type of micro pressure measurement system produced by the combination of microelectronics and micromechanics. The MEMS pressure chip is a super-small pressure measurement system. The piezoresistors in this system can convert the external pressure into resistance changes under the action of the micro mechanical structure, so as to achieve the purpose of measuring pressure.

[0003] With the expansion of application scenarios, the demand for MEMS pressure chips in micro pressure measurement is getting higher and higher. Especially in the fields of medical devices, consumer electronics, industrial control, etc., the requirements for precision, sensitivity and small size are constantly increasing. However, due to the limitations of process capabilities, the stability and measurement accuracy of MEMS pressure chips in the micro pressure range often fail to meet these requirements. Specifically, the miniaturized manufacturing of pressure sensors is difficult, the signal output is weak and vulnerable to noise interference, resulting in inaccurate measurement.

[0004] And the external signal amplification device will increase the overall volume and weight of the device and also increase the difficulty of the process, and the yield rate and so on are also significantly affected. Summary of the Invention

[0005] The present invention is to overcome the deficiencies in the prior art. By using the complementary bipolar process, NPN and PNP transistors with complementary performance are obtained in the same IC (Integrated Circuit), and at the same time, JFET devices are compatible. It has a large bandwidth, high input impedance, low bias current, low noise, low power consumption, wide output range, large output current and low distortion, etc., which meet the requirements of high-speed operational amplifiers. A method for fabricating a micro differential pressure sensor with an island and beam film structure with an IC is provided.

[0006] The present application provides the following technical solutions: A method for fabricating a micro differential pressure sensor with an island and beam film structure with an IC, characterized in that: it includes the following steps: S1. Take an N-type top silicon SOI silicon wafer, and use photolithography and ion implantation processes to fabricate an N-type buried layer and a P-type buried layer on the N-type top silicon; S2. On the N-type top silicon between the N-type buried layer and the P-type buried layer, a set of grooves is also fabricated by using photolithography and ion implantation processes, and an island film structure is formed on the N-type top silicon through the set of grooves; S3. Take a double-polished silicon wafer with an oxide layer, and bond it to the N-type top silicon of the SOI silicon wafer by using a bonding process; S4. Remove the substrate silicon and buried oxide layer of the SOI wafer by the CMP humidification process, exposing the bottom surface of the N-type top silicon; S5. On the N-type top silicon on both sides of the N-type buried layer and P-type buried layer, a pair of dielectric isolation grooves are prepared by using oxidation, film formation, photolithography, dielectric etching, deep silicon etching, sidewall oxidation, polysilicon filling and annealing, CMP planarization, hot phosphoric acid corrosion, and oxide layer corrosion processes in sequence; S6. On the N-type top silicon above the N-type buried layer, an N-type buried layer connection region is formed by photolithography, phosphorus implantation, and ion diffusion processes in sequence; On the N-type top silicon above the P-type buried layer, a P well is formed in the N-type top silicon by photolithography, boron implantation, and diffusion processes in sequence, and then a P-type buried layer connection region is formed on the P well by photolithography, boron implantation, and diffusion processes in sequence; A group of sensitive resistors are formed on the N-type top silicon by photolithography, phosphorus implantation, and ion diffusion processes in sequence; S7. On the N-type top silicon on one side of the N-type buried layer connection region, a P-type base region is formed by boron implantation and ion diffusion processes in sequence; on the P well, an N-type base region is formed by phosphorus implantation and diffusion processes in sequence; S8. An N-type emitter region is formed on the P-type base region by phosphorus implantation process; a P-type emitter region is formed on the N-type base region by boron implantation process; S9. Deposit an oxide layer on the entire surface of the N-type top silicon to form an interlayer dielectric layer; S10. On the interlayer dielectric layer, contact holes corresponding to the N-type buried layer connection region, P-type base region, N-type emitter region, sensitive resistor, P-type buried layer connection region, N-type base region, and P-type emitter region are completed by photolithography, etching, and corrosion processes in sequence, and conductive electrodes 13 are completed in the contact holes by metal sputtering, photolithography, and etching processes all the time; S11. On the double-polished wafer, through holes communicating with the island film structure are completed by dielectric etching, photolithography, deep silicon etching, and corrosion processes in sequence.

[0007] On the basis of the above technical solutions, the following further technical solutions can also be available: In the step S10, a contact hole corresponding to the distribution is provided on both sides of the N-type emitter region and P-type emitter region.

[0008] In the step S6, the sensitive resistor and the groove body are corresponding distributed.

[0009] Advantages of the invention: The processing technology provided by the present invention is simple and practical, and the prepared sensor has the advantages of high integration, high signal sensitivity, high structural strength, easy sensor integration, etc. Moreover, the processing technology is a common process with good consistency, can realize batch manufacturing, simplifies the process flow, and improves the preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic structural diagram of the SOI wafer in step S1 of the present invention; Figure 2 is a schematic diagram after step S1 of the present invention is completed; Figure 3 is a schematic diagram of step S2 of the present invention; Figure 4 is a schematic diagram after step S3 of the present invention is completed; Figure 5 is a schematic diagram after step S4 of the present invention is completed; Figure 6 is a schematic diagram after step S5 of the present invention is completed; Figure 7 is a schematic diagram after step S6 of the present invention is completed; Figure 8 is a schematic diagram after step S7 of the present invention is completed; Figure 9 is a schematic diagram after step S8 of the present invention is completed; Figure 10 is a schematic diagram after step S9 of the present invention is completed; Figure 11 is a schematic diagram after step S10 of the present invention is completed; Figure 12 is a schematic diagram after step S11 of the present invention is completed. DETAILED DESCRIPTION OF THE INVENTION

[0011] In order to make the present invention more clearly understood, the following further describes a method for preparing a complementary bipolar device based on a bonding process with reference to the accompanying drawings. The specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0012] As Figures 1-12 shown, a method for fabricating a micro differential pressure sensor with an island and beam film structure with an IC includes the following steps: S1. Take an N-type top silicon SOI wafer 100, the SOI wafer 100 has an N-type top silicon 101 on the upper side, a substrate silicon 102 on the lower side, and an insulating layer 103 located between the N-type top silicon 101 and the substrate silicon 102.

[0013] On the upper surface of the N-type top silicon 101, a first silicon thin film 105 is grown on the surface of the N-type top silicon 101 by thermal oxidation to reduce the damage caused by high-energy implantation.

[0014] Subsequently, a photolithography process and an ion implantation process are successively used to fabricate an N-type buried layer 1 and a P-type buried layer 2 on the N-type top silicon 101. The N-type buried layer 1 and the P-type buried layer 2 are spaced apart by a certain distance and are respectively distributed at the left and right ends of the N-type top silicon 101.

[0015] S2. A pair of spaced-apart grooves 14 are also fabricated on the N-type top silicon 101 between the N-type buried layer 1 and the P-type buried layer 2 by using a photolithography process and an ion implantation process. An island film structure 104 is formed on the N-type top silicon 101 by dividing through the pair of grooves 14.

[0016] S3. Take a double-polished silicon wafer 200, and an oxide layer 201 is fabricated on the upper and lower surfaces of the double-polished silicon wafer 200 by using a thermal oxidation process. Subsequently, the double-polished silicon wafer 200 is bonded to the N-type top silicon 101 of the SOI silicon wafer by using a bonding process, so that the first silicon thin film 105 is connected to the oxide layer 201 on the double-polished silicon wafer 200.

[0017] S4. The substrate silicon 102 and the buried oxide layer 103 of the SOI silicon wafer 100 are removed by using a CMP wet method process, so that the bottom surface of the N-type top silicon 101 is exposed.

[0018] S5. Dielectric isolation grooves 3 are successively fabricated on the N-type top silicon 101 on both sides of the N-type buried layer 1 and the P-type buried layer 2 by using oxidation, film formation, photolithography, dielectric etching, deep silicon etching, sidewall oxidation, polysilicon filling and annealing, CMP planarization, hot phosphoric acid etching, and oxide layer etching processes. The N-type buried layer 1 and the P-type buried layer 2 are respectively distributed between a pair of dielectric isolation grooves 3.

[0019] S6. An N-type buried layer connection region 4 is formed on the N-type top silicon 101 above the N-type buried layer 1 by using photolithography, phosphorus implantation, and ion diffusion processes successively.

[0020] On the N-type top silicon 101 above the P-type buried layer 2, a P well 6 is formed in the N-type top silicon by using photolithography, boron implantation, and diffusion processes successively. Then, a P-type buried layer connection region 5 is formed on the P well 6 by using photolithography, boron implantation, and diffusion processes successively.

[0021] A pair of sensitive resistors 7 are formed on the N-type top silicon 101 between the two pairs of dielectric isolation grooves 3 by using photolithography, phosphorus implantation, and ion diffusion processes successively. The positions where the sensitive resistors 7 are distributed correspond to the grooves 14.

[0022] S7. A P-type base region 8 is formed on the N-type top silicon 101 on one side of the N-type buried layer connection region 4 by using boron implantation and ion diffusion processes successively. Then, an N-type base region 9 is formed on the P well 6 by using phosphorus implantation and diffusion processes successively.

[0023] S8. An N-type emitter region 11 is formed in the middle of the P-type base region 8 by means of phosphorus implantation. A P-type emitter region 10 is formed in the middle of the N-type base region 11 by means of boron implantation.

[0024] S9. An interlayer dielectric layer 12 is formed by depositing an oxide layer over the entire upper surface of the N-type top silicon 101.

[0025] S10. On the interlayer dielectric layer 12, contact holes are respectively fabricated over the N-type buried layer connection region 4, P-type base region 8, sensitive resistor 7, P-type buried layer connection region 5, and N-type base region 9 through photolithography, etching, and corrosion processes in sequence. Corresponding distributed contact holes are provided on both sides of the N-type emitter region 11 and P-type emitter region 10.

[0026] Conductive electrodes 13 are completed in each contact hole through metal sputtering, photolithography, and etching processes, so that the corresponding N-type buried layer connection region 4, P-type base region 8, sensitive resistor 7, P-type buried layer connection region 5, N-type base region 9, N-type emitter region 11, and P-type emitter region 10 can form electrical signal connection and cooperation with the outside through the conductive electrodes 13.

[0027] S11. A tapered through-hole 211 communicating with the island film structure 104 is fabricated on the double-polished silicon wafer 200 through dielectric etching, photolithography, deep silicon etching, and corrosion processes in sequence, thus completing the fabrication of the complementary bipolar device.

[0028] In the present invention, N-type and P-type buried layers are formed by implantation and annealing on the top silicon of the SOI silicon wafer, then one side of the top silicon is bonded to another oxidized silicon wafer, and the original substrate silicon of the SOI silicon wafer is removed by debonding. In this way, an SOI silicon wafer with buried layers is formed on the remaining silicon wafer. The fabrication of the double buried layers of the complementary bipolar transistor is completed without using the epitaxial process by combining semiconductor manufacturing technology and MEMS manufacturing technology.

Claims

1. A method for preparing an island-beam membrane structure micro-pressure differential sensor with an IC, characterized in that: It includes the following steps: S1. Take an N-type top silicon SOI silicon wafer (100), and prepare an N-type buried layer (1) and a P-type buried layer (2) on the N-type top silicon (101) by photolithography and ion implantation process; S2. A group of grooves (14) are prepared on the N-type top silicon (101) between the N-type buried layer (1) and the P-type buried layer (2) by photolithography and ion implantation processes, and an island film structure (104) is formed on the N-type top silicon (101) by the group of grooves (14); S3. Take a double-polished silicon wafer (200) with an oxide layer (201), and bond it to the N-type top silicon (101) of the SOI silicon wafer by a bonding process; S4. Using a CMP wet process to remove the substrate silicon (102) and the buried oxide layer (103) of the SOI silicon wafer (100), so that the bottom surface of the N-type top silicon (101) is exposed; S5. A pair of dielectric isolation grooves (3) are prepared on the N-type top silicon (101) on both sides of the N-type buried layer (1) and the P-type buried layer (2) by sequentially using oxidation, film formation, photolithography, dielectric etching, deep silicon etching, sidewall oxidation, polysilicon filling and annealing, CMP planarization, hot phosphoric acid etching and oxide layer etching processes; S6. Forming an N-type buried layer connection region (4) on the N-type top silicon (101) above the N-type buried layer (1) by sequentially performing photolithography, phosphorus implantation, and ion diffusion processes; On the N-type top silicon (101) above the P-type buried layer (2), a P-well (6) is formed in the N-type top silicon by sequentially performing photolithography, boron implantation and diffusion processes, and then a P-type buried layer connection region (5) is formed on the P-well (6) by sequentially performing photolithography, boron implantation and diffusion processes; A group of sensitive resistors (7) are formed on the N-type top silicon (101) by sequentially performing photolithography, phosphorus implantation and ion diffusion processes; S7. Forming a P-type base region (8) on the N-type top silicon (101) on one side of the N-type buried layer connection region (4) by sequentially implanting boron and ion diffusion processes; and forming an N-type base region (9) on the P well (6) by sequentially implanting phosphorus and diffusion processes; S8. Forming an N-type emitter region (11) on the P-type base region (8) by a phosphorus implantation process; forming a P-type emitter region (10) on the N-type base region by a boron implantation process; S9, depositing an oxide layer on the entire surface of the N-type top silicon (101) to form an interlayer dielectric layer (12); S10, contact holes corresponding to the N-type buried layer connection region (4), the P-type base region (8), the N-type emitter region (11), the sensitive resistor (7), the P-type buried layer connection region (5), the N-type base region (9) and the P-type emitter region (10) are formed on the interlayer dielectric layer (12) by photolithography, etching and corrosion processes in sequence, and conductive electrodes (13) are formed in the contact holes by metal sputtering, photolithography and etching processes; S11, completing a through hole (211) connected to the island film structure (104) on the double-polished silicon wafer (200) by sequentially performing dielectric etching, photolithography, deep silicon etching and corrosion processes.

2. The method for preparing a micro-pressure differential sensor with an island and beam membrane structure having an IC according to claim 1, characterized in that: In the step S10, a correspondingly distributed contact hole is provided on both sides of the N-type emitter region (11) and the P-type emitter region (10).

3. The method for preparing a micro-pressure differential sensor with an island and beam membrane structure having an IC according to claim 1, characterized in that: In the step S6, the sensitive resistor (7) and the slot body (14) are distributed correspondingly.

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