Method and device for generating controller of multiple Flash memories and electronic equipment

Abstract

The invention relates to the technical field of vehicles, in particular to a method and a device for generating a controller of a multi-chip Flash memory and electronic equipment. The method comprises the following steps: acquiring a control parameter written based on a SpinalHDL programming language; wherein the control parameters comprise a first configuration parameter of a register bus, a second configuration parameter of a data reading bus, third configuration parameters of a register unit, a clock management unit, a control unit and a plurality of driving units in the controller, and fourth configuration parameters of at least one Flash memory controlled by the controller; generating a control circuit of the controller based on the control parameter; wherein the control circuit comprises a register bus, a data reading bus and a controller, the controller comprises a register unit, a clock management unit, a control unit and a plurality of driving units, and one driving unit corresponds to one Flash memory.

Description

Technical Field

[0001] The present disclosure relates to the technical field of vehicles, and particularly to a method, an apparatus, and an electronic device for generating a controller for a multi-chip Flash memory. Background Art

[0002] As a core component for storing data codes, the importance of the Flash memory is self-evident. The automotive electronic system not only requires the Flash memory to provide high-speed and stable storage services, but also requires it to maintain the integrity and reliability of data in complex and changeable working environments such as high temperature, low temperature, and vibration.

[0003] In order to meet the storage requirements of the automotive electronic system, the number of Flash memories installed in the automotive electronic system is also increasing, and how to manage multiple Flash memories in the automotive electronic system has become an urgent problem to be solved. Summary of the Invention

[0004] To solve the above technical problems, the present disclosure provides a method, an apparatus, and an electronic device for generating a controller for a multi-chip Flash memory.

[0005] In a first aspect, the present disclosure provides a method for generating a controller for a multi-chip Flash memory, including: obtaining control parameters written in the SpinalHDL programming language; wherein, the control parameters include a first configuration parameter of a register bus, a second configuration parameter of a data read bus, a third configuration parameter of a register unit, a clock management unit, a control unit, and a plurality of driver units in the controller, and a fourth configuration parameter of at least one Flash memory controlled by the controller; based on the control parameters, generating a control circuit of the controller; wherein, the control circuit includes a register bus, a data read bus, and a controller, the controller includes a register unit, a clock management unit, a control unit, and a plurality of driver units, and one driver unit corresponds to one Flash memory.

[0006] In a second aspect, the present disclosure provides an apparatus for generating a controller for a multi-chip Flash memory, including: an obtaining unit, configured to obtain control parameters written in the SpinalHDL programming language; wherein, the control parameters include a first configuration parameter of a register bus, a second configuration parameter of a data read bus, a third configuration parameter of a register unit, a clock management unit, a control unit, and a plurality of driver units in the controller, and a fourth configuration parameter of at least one Flash memory controlled by the controller; a processing unit, configured to generate a control circuit of the controller based on the control parameters obtained by the obtaining unit; wherein, the control circuit includes a register bus, a data read bus, and a controller, the controller includes a register unit, a clock management unit, a control unit, and a plurality of driver units, and one driver unit corresponds to one Flash memory.

[0007] In a third aspect, the present disclosure provides an electronic device, which includes: a memory and a processor, where the memory is used to store a computer program; the processor is used to cause the electronic device to implement the method for generating a controller of multiple Flash memories according to any one of the first aspect when executing the computer program.

[0008] In a fourth aspect, the present disclosure provides a computer-readable storage medium, including: a computer program stored on the computer-readable storage medium, and the computer program is executed by a controller to implement the method for generating a controller of multiple Flash memories according to any one of the first aspect.

[0009] In a fifth aspect, the present disclosure provides a computer program product, which causes a computer to execute the method for generating a controller of multiple Flash memories according to any one of the first aspect when the computer program product runs on the computer.

[0010] These aspects or other aspects of the present disclosure will be more clearly understood in the following description.

[0011] The technical solution provided by the present disclosure has the following advantages compared with the prior art: for the method for generating a controller of multiple Flash memories provided by the present disclosure, by obtaining control parameters written in the SpinalHDL programming language; then, based on the control parameters, a control circuit of the controller is generated; in this way, multiple Flash memories can be controlled based on the generated control circuit. Then, when the control circuit of the controller generated by the method for generating a controller of multiple Flash memories provided in the embodiments of the present disclosure is applied to an automotive electronic system, the automotive electronic system can control multiple Flash memories based on this control circuit, solving the problem of how to manage multiple Flash memories in the automotive electronic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure.

[0013] To more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the accompanying drawings required for describing the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0014] Figure 1 It is a schematic flowchart of a method for generating a controller of multiple Flash memories provided in an embodiment of the present disclosure;

[0015] Figure 2 One of the schematic structural diagrams of a controller for multiple Flash memories provided by an embodiment of the present disclosure;

[0016] Figure 3 Another schematic structural diagram of a controller for multiple Flash memories provided by an embodiment of the present disclosure. Detailed implementation manners

[0017] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0018] Many specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure, but the present disclosure may be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0019] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0020] SpinalHDL in the embodiments of the present disclosure is a high-level hardware description language (HDL) based on Scala, created by Charles Papon in 2014. It aims to provide an efficient and easy-to-use hardware design tool, especially suitable for the development of large-scale SoC systems.

[0021] The AXI-Lite bus in the embodiments of the present disclosure is a lightweight on-chip bus standard, mainly used for the transmission of small amounts of data and does not support burst transmission.

[0022] The AXI4-RO bus in the embodiments of the present disclosure is not an independent bus type, but a specific configuration or usage scenario of the AXI4 bus.

[0023] The ECC check (Error Checking and Correcting) in the embodiments of the present disclosure is an error checking and correcting technology widely used in the computer field, mainly used to ensure the accuracy and integrity of data.

[0024] The MEM storage area in the embodiments of the present disclosure refers to the memory (Memory) area in a computer, which is used to temporarily store data and instructions.

[0025] Verilog in the embodiments of the present disclosure is a hardware description language (HDL), which is used to describe the design and behavior of digital circuits and systems.

[0026] The BOOT information in the embodiments of the present disclosure refers to a series of operations performed by a computer during the startup process, including starting the BIOS, loading the operating system, etc.

[0027] Single-bit ECC error in the embodiments of the present disclosure: This error refers to an error in one bit of the data, but it can be corrected by parity check.

[0028] Multi-bit ECC error in the embodiments of the present disclosure: This error refers to errors in multiple bits of the data, and it cannot be repaired by parity check.

[0029] Embodiment 1

[0030] Figure 1 The flowchart of the generation method of the controller of multiple Flash memories is exemplarily shown. The execution subject of this example can be an electronic device, such as Figure 1 As shown, the method includes:

[0031] S11. Obtain control parameters written in the SpinalHDL programming language; wherein, the control parameters include the first configuration parameter of the register bus, the second configuration parameter of the data read bus, the third configuration parameter of the register unit, the clock management unit, the control unit and multiple driving units in the controller, and the fourth configuration parameter of at least one Flash memory controlled by the controller.

[0032] In some examples, the control parameters include the configuration parameters shown in Table 1, Table 2, Table 3, Table 4 and Table 5.

[0033] Table 1

[0034]

[0035] Table 2

[0036]

[0037]

[0038]

[0039] In some examples, the control logic parameters are different from the data bit width and the parity bit width. For example, taking the AXI-RO bus as an example, if DataWidth = 64, then the data bit width of the bus is 64 bits. When a data read is initiated on the AXI-RO bus, there is a TSTRB signal in the bus. This signal can select the amount of data required for the current access. If the TSTRB signal selects 16-bit data, then the read channel control logic will send 48-bit 0 + 16-bit data (48 + 16 = 64).

[0040] Table 3

[0041]

[0042] Table 4

[0043]

[0044]

[0045] In some examples, when configuring the Flash, only when the user configures the ProtectEnable parameter to true will the read / write protection and the security key verification take effect. Otherwise, the corresponding circuit will not be generated and the corresponding function will not be supported.

[0046] (Security key verification: When the key configured through the register interface is the same as the key stored in the Flash, the read protection can be lifted.)

[0047] Table 5

[0048]

[0049] S12. Generate a control circuit of the controller based on control parameters; wherein, the control circuit includes a register bus, a data read bus, and a controller, and the controller includes a register unit, a clock management unit, a control unit, and a plurality of driving units, and one driving unit corresponds to one Flash memory.

[0050] As can be seen from the above, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure obtains control parameters written in the SpinalHDL programming language; then, based on the control parameters, a control circuit of the controller is generated; in this way, multiple Flash memories can be controlled based on the generated control circuit. Then, when the control circuit of the controller generated by the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure is applied to an automotive electronic system, the automotive electronic system can control multiple Flash memories based on this control circuit.

[0051] In some feasible examples, the first configuration parameter includes a register type, a first decoding logic of a register bus corresponding to the register type, an address bit width, and a data bit width; wherein, the register type includes any one of an AXI-Lite bus, an Advanced High Performance Bus, and a peripheral bus.

[0052] In some feasible examples, the second configuration parameter includes a read bus type, a second decoding logic of a data read bus corresponding to the read bus type, an address bit width of the data read bus, a data bit width, a second quantity, a data bit width of a Memory (MEM), a data bit width and a quantity of a First Input First Output (FIFO); wherein, the data bit width of the first-in-first-out queue is the same as the data bit width of the data read bus, and the quantity of the data read bus is the same as the quantity of the first-in-first-out queue.

[0053] In some feasible examples, the third configuration parameter includes a register type of a register unit, a second indication information for indicating whether the register unit enables write protection, a base address of a non-volatile memory (Flash memory), a first parameter configuration of a clock management unit, a second parameter configuration of a control unit, and a third parameter configuration of a driving unit.

[0054] In some feasible examples, the fourth configuration parameter includes a data bit width of a non-volatile memory, a third quantity, and a third indication parameter for indicating whether to enable a redundant driving unit.

[0055] In some feasible examples, the second configuration parameter includes a data read amount; the control parameter further includes a fifth configuration parameter for generating a prefetch buffer, and the fifth configuration parameter includes one or more of a first indication information for indicating whether to generate a prefetch buffer, a first quantity of the smallest storage unit in the prefetch buffer generated when the first indication information indicates to generate a prefetch buffer, and a third quantity of cache blocks (CacheLines) in a cache (Cache); wherein, the product of the first quantity and the data amount of the smallest storage unit is the same as the data read amount.

[0056] Figure 2 FIG. 1 schematically shows the structure of a controller 1 of a multi-chip Flash memory, including a register bus 10, a data read bus 11, a register unit 12, a clock management unit 13, a control unit 14, and a plurality of driver units 15.

[0057] Among them, one driver unit 15 corresponds to one Flash memory 2. The register unit 12 is connected to the register bus 10, the clock management unit 13, and the control unit 14. The control unit 14 is connected to the data read bus 11, a plurality of driver units 15, and the register unit 12. The clock management unit 13 is connected to the register unit 12 and a plurality of driver units 15.

[0058] In some examples, the total number of data read buses is the same as the total number of read channel control logics, the total number of prefetch buffers is the same as the total number of data read buses, and the total number of Flash state arbitrators is the same as the total number of data read buses.

[0059] In some examples, the main functions of the register unit 12 include: performing read operations through the register bus 10 to achieve the configuration and reading of internal registers. This part is written using the regif function of SpinalHDL. The register bus type can be parameter-configured according to user requirements, and buses such as AXI4-Lite, AHB, and APB can be selected. After completing the parameter configuration, the SpinalHDL code can automatically generate the corresponding bus decoding logic to complete the register reading operation.

[0060] In some examples, the register unit stores various configuration information and status information required by the controller 1 according to the register type. Among them, the register type includes one or more of a status register, an unlock register, a configuration register, a Flash operation register, and a security register.

[0061] In some examples, the status register is used to store the status of the controller 1 and the Flash memory. Among them, the status of the Flash memory includes one or more of a controller lock status flag, a Flash busy flag, a Flash operation completion flag, a Flash operation error flag, a Flash ECC (Error Correcting Code) error flag, a Flash write protection error flag, and a Flash check error flag.

[0062] In some examples, the unlock register is used to implement the unlock and lock functions of Controller 1. Other operations of the Flash memory except data reading, such as programming operations and erasing operations, need to be implemented through the register interface configuration. Therefore, to avoid accidental modification of the Flash memory data caused by the user's incorrect operation, the register interface is provided with an unlock register. After Controller 1 is reset, the register interface is in the locked state. Only when the user sequentially inputs the correct keys into the unlock register can the register interface be unlocked and the register bus can write data to other registers. Otherwise, the register bus cannot operate on other registers. If the user writes an incorrect key to the register interface, the controller can be locked and operations such as erasing and programming cannot be performed.

[0063] In some examples, the configuration register mainly stores important information such as the interrupt enable configuration and clock frequency of Controller 1. Since operations such as programming and erasing of the Flash memory hardware require a pulse signal with a period of 1 us for time counting, the user can set the clock frequency in the configuration register to inform Controller 1 of the current clock frequency.

[0064] In some examples, the Flash operation register is a register group, which includes a Flash command register (used to specify operations such as erasing, programming, and data verification), an address register, a data length register, a data register, a command trigger register, etc. When the user wants to perform operations such as erasing presence, programming, and data verification on the Flash memory, the corresponding commands, operation addresses, operation data lengths, and data to be programmed need to be configured. After the above configuration is completed, the configured command triggers the Flash operation register to start working.

[0065] In some examples, the security register is a register group, which includes a write protection register, a read protection register, an ECC error address register, a security key register, etc. The user can enable the write protection function of each area in the Flash memory by configuring the write protection register. After enabling, the area cannot be programmed or erased. The read protection register is a set of read-only status registers. This information is stored in the user-defined information storage area of the Flash memory and cannot be modified through the register. The ECC error address register is used to indicate the operation address of the Flash memory when an ECC error occurs. The security key register is used in the security key verification operation. The user can input a security key, and the controller will determine whether the key is consistent with the key stored in the user-defined information storage area for verification. After the verification is passed, the read protection function can be temporarily unlocked.

[0066] In some examples, in addition to bus decoding and register storage, the register unit also implements a series of detection logics and interrupt handling logics:

[0067] a. Unlock logic: Such as an unlock register, this logic is used to detect whether the key configured by the user is correct. Only when the key is correct can register operations be performed. Conversely, this logic will prevent any register operations, such as the first operation.

[0068] b. Check logic: This part is the basis for ensuring the correct operation of the controller. This part of the circuit will check information such as the instructions, addresses, data lengths, and written data configured by the user to determine whether there are instruction errors, unaligned addresses or address out-of-bounds errors, data length inconsistent with the actual data volume, instruction and address conflicts, or operations on write-protected areas. The register unit will perform the above checks after the user configures and triggers the command. Only when the checks are error-free will the operation information be sent to the control unit for processing.

[0069] c. Interrupt handling: If the user enables the corresponding interrupt enable, the register module will also send relevant interrupt signals.

[0070] In some examples, in addition to the register bus of the register unit being configurable according to parameters, operations such as its read-write protection register and address judgment of the check unit are also completed in a parameterized manner. If the user has read-write protection requirements, this function can be enabled through parameter configuration, and the register unit will generate relevant read-write protection registers and their check logic circuits. In addition, the address judgment of the check logic also depends on the parameter information configured by the user. The user can configure the number of Flash memories, the capacity of a single Flash memory, the base address of the Flash memory, etc. according to their own needs. When the controller generates Verilog / Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) code, it will automatically calculate and allocate the address space of each Flash memory. Subsequent read-write protection and address checks depend on this allocation result.

[0071] In some implementable examples, the control unit 14 is the core of the controller 1, which mainly includes a write channel control logic, a read channel control logic, a prefetch buffer (a corresponding circuit will only be generated when the user configures the parameter to enable the prefetch buffer), a MEM storage area, a First Input First Output (FIFO) storage area, a Flash status arbiter, etc.

[0072] (1) Write channel control logic:

[0073] The write channel control logic mainly consists of a state machine. After the system is powered on and reset, the state machine will automatically perform an initialization process, which mainly completes operations such as power-on, reading Flash configuration information, Flash configuration, and obtaining read / write protection information in the user-defined information storage area. After completing the above operations, the controller will send an initialization completion signal. During the initialization phase, the controller cannot perform any other operations. After initialization, the write channel control logic will receive operation information from the register unit, determine the number of the target Flash memory according to this information, and send the corresponding operation request to the Flash status arbiter. The operations that this control logic can receive mainly include erase, program, and verify. When it is in the verification operation, the state machine will also obtain data from the FIFO after the Flash completes data reading, and determine whether the data is consistent with the expected value (if it is an erase verification, determine whether the data is all F; if it is a security key verification, determine whether the data is consistent with the key in the user-defined information storage area).

[0074] (2) Read channel control logic:

[0075] The read channel control logic mainly consists of a bus decoder. The read channel control logic generates the corresponding bus decoder according to the type and quantity of the data reading bus configured by the user. The read channel control logic realizes functions such as communication with the data reading bus and read protection judgment. After parsing the bus operation and obtaining the bus operation address, the read channel control logic will determine whether the read protection logic is valid according to the BOOT information obtained from other control modules of the chip. If the instruction of the Central Processing Unit (CPU) is obtained from the Flash memory, that is, the CPU starts from the Flash memory, the read protection logic will not take effect. If the CPU is currently in the JTAG (Joint Test Action Group) debugging mode or starts from other storage areas, the read protection logic will take effect. The read channel control logic determines whether the read protection is enabled. If it is enabled, it will return invalid data to the bus and send an operation error message; if the read protection is not enabled, it will normally return data. After receiving the bus operation, the read channel control logic sends the corresponding data reading operation to the Flash status arbiter, and after determining that there is enough data in the corresponding FIFO, it sends the data in the FIFO to the bus.

[0076] (3) Prefetch buffer:

[0077] The prefetch buffer is composed of a cache memory (Cache). Only when the user configures and enables the parameters of the prefetch buffer, will the controller generate the circuit and control logic of the prefetch buffer. The prefetch buffer depends on the bus address parsed by the read channel control logic. If the prefetch buffer is enabled, the operation on the Flash status arbiter will no longer be generated by the read channel control logic, but by the prefetch buffer. After transmitting the data length of the bus request, the prefetch buffer will continue to send a read data request to the Flash status arbiter until all the prefetch lines are filled.

[0078] (4) MEM storage area:

[0079] The MEM storage area is mainly composed of a random access memory (Random Access Memory, RAM). It is mainly used for programming functions, storing data from the register unit, and performing ECC encoding processing on the data. When the drive module sends data, it will send a request to the MEM storage area. The MEM storage area will send the ECC-encoded data through the drive unit to the Flash. The ECC encoding logic will be automatically generated according to the data bit width of the Flash memory.

[0080] (5) FIFO storage area:

[0081] The FIFO storage area is mainly used for data reading functions. After the bus initiates a data reading operation, the corresponding drive module will transfer the data into the FIFO. The FIFO storage area will perform ECC decoding on the data. If a single-bit ECC error is found, the data will be corrected; if a multi-bit ECC error is found, the FIFO storage area will send the ECC error and the current address to the read channel control logic and the register unit. The ECC decoding logic is similar to the ECC encoding logic and will also be automatically generated according to the data bit width of the Flash memory. Like the read channel control logic, the number of FIFO storage areas is also automatically generated by the number of buses configured by the user, that is, each data reading bus corresponds to a read channel control logic and a FIFO.

[0082] (6) Flash status arbiter:

[0083] The Flash status arbiter consists of a status lookup table that records the status within multiple Flash drive units, i.e., what operation the drive unit is performing and whether it is in an idle state. The Flash status arbiter receives operation requests from the write channel control logic and the read channel control logic (or prefetch buffer), and determines whether the Flash corresponding to the operation is in an idle state. If so, it sends the operation request to the drive unit; otherwise, it remains in a waiting state. This arbiter is essentially an m-to-n arbitration device, where m is the number of data read buses + 1 (1 for the write channel) and n is the number of Flash memories. Through this arbiter, the Flash memory controller can achieve the RWW (Read While Write) operation. For example, the register bus controls Flash3 for erasure, data read bus 0 reads Flash0, and data read bus 1 reads Flash2, and these three operations can be performed simultaneously. If the operation initiated by the register bus is a full-chip erasure, then all Flash memories perform the erasure operation, and data cannot be read at this time.

[0084] In some examples, the drive unit mainly consists of a state machine and a redundancy repair unit. Its important function is to receive the operation requests sent by the Flash status arbiter and implement read, write, and erase operations on the Flash memory through the Flash interface. There are multiple sub-state machines inside the drive unit to implement various operations of the Flash memory. During this period, the drive unit reads data from the MEM through the data transfer channel, the MEM interface, or the FIFO interface and writes it into the Flash, or reads data from the Flash and writes it into the FIFO. If the Flash interfaces are inconsistent, only a simple modification of the state machine of the drive unit is required to complete the support for different Flash memories. The function of the redundancy repair unit is to judge the operation address based on the bad block information and address read from the user-defined information storage area. If the operation address hits the bad block area, it maps the address to the redundant storage area of the Flash memory and performs a read operation on the redundant storage area to achieve the Auto-Repair function.

[0085] In some examples, such as Figure 2As shown, each Flash memory includes a Main Array, an NVR Array, an NVR-CFG Array, and an RDN Array. Among them, the Main Array is the main storage area for storing CPU running programs or important data; the NVR Array is the NVR storage area, which is defined as the information area in this controller design and is used to store key system configuration data of the CPU, Flash write protection information, read protection enable, security key enable, security keys, and Flash bad block addresses, etc.; the NVR-CFG Array is the Flash configuration storage area, which is the area where the Flash stores its own configuration information. Generally, after the Flash is verified during machine testing, the Flash configuration information is written into this area according to the manufacturer's requirements. During user use, modification of this area is not allowed; the RDN Array is the redundant storage area.

[0086] In some examples, the Flash memory usually has a preset number of sectors as the redundant storage area for users. If bad blocks are found in the Flash memory during machine testing, the original bad block addresses can be mapped to the redundant storage area, and this area can be used to store data to achieve fault repair.

[0087] In some examples, the type of the register bus includes any one of the AXI-Lite bus, the Advanced High Performance Bus (AHB), and the Advanced Peripheral Bus (APB).

[0088] In some examples, the type of the data read bus includes any one of AXI4-RO, AHB, and APB.

[0089] In some examples, the number of Flash memories controlled by Controller 1 can be configured based on actual needs, and the corresponding address parameters of the Flash memories can also be configured based on actual needs, which are not limited here.

[0090] The register unit 12 is used to receive a first operation through the register bus 10. Among them, the first operation includes any one of a programming operation, an erase operation, and a data verification operation.

[0091] In some examples, the erase operation includes one or more of sector erase, block erase, write protection information erase, and full chip erase operation.

[0092] In some examples, the programming operation includes page programming.

[0093] In some examples, the data verification operation includes one or more of specified length erasure verification, block erasure verification, full chip erasure verification, and security key verification.

[0094] Exemplarily, taking the data verification operation as the specified length erasure verification as an example, the execution logic is as follows:

[0095] The register bus sends a data verification instruction containing the specified length erasure verification to the register unit. The register unit sends the data verification instruction to the write channel control logic. The write channel control logic determines the verification address and data length based on the data verification instruction. The write channel control logic controls the driving unit corresponding to the verification address through the target interface to read the stored data corresponding to the verification address and data length in the Flash memory. The driving unit corresponding to the verification address stores the stored data read from the Flash memory into the FIFO storage area through the target interface. Then, the write channel control logic reads the stored data from the FIFO storage area. The write channel control logic determines the data verification result based on the stored data. For example, when each data in the stored data is empty, the verification result is marked as erasure completed.

[0096] The control unit 14 is used to receive the second operation through the data reading bus 11. Among them, the second operation of the reading operation includes a reading operation.

[0097] In some examples, before the register unit 12 controls the control unit 14 to execute the first operation, it is necessary to perform unlocking logic and check logic discrimination on the first operation. When it is determined that the unlocking logic is correct and there is no error in the check logic, the register unit 12 controls the control unit 14 to execute the first operation.

[0098] The control unit 14 is further used to control the driving unit corresponding to the target memory to drive the target memory to execute the operation instruction based on the target memory corresponding to the storage address in the target operation. Among them, the target operation includes one or more of the first operation and the second operation, and the target memory includes any one of the Flash memories.

[0099] In some examples, the programming language of the controller 1 in the embodiments of the present disclosure may be a preset language, such as: SpinalHDL language.

[0100] As can be seen from the above, a controller for a multi-chip Flash memory provided by the embodiments of the present disclosure, through the controller for a multi-chip Flash memory designed based on the SpinalHDL language, provides significant performance improvement and flexibility enhancement for the automotive electronic system, specifically manifested in the following aspects:

[0101] 1. Significantly improve the flexibility of the controller:

[0102] Using the parametric design ability of SpinalHDL, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure can quickly generate a customized controller circuit according to the specific requirements of different automotive electronic systems. This greatly shortens the development cycle, reduces the development cost, and improves the adaptability of the controller to the requirements of complex automotive electronic systems.

[0103] 2. Greatly enhance the scalability of the controller:

[0104] Through the rich bus library and function library of SpinalHDL, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure realizes the comprehensive support of the controller for multiple bus interfaces and multiple Flash memories. This provides a great deal of expansion space for users, making it simple and efficient to add or replace Flash memories in automotive electronic systems.

[0105] 3. Simplify the design and modification process of the controller:

[0106] The method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure utilizes the modular design characteristics of SpinalHDL to divide the controller into multiple independent modules. This design enables each module to be designed and modified separately, thus greatly simplifying the design and modification process. In addition, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure also provides ECC encoding and decoding modules for different data bit widths, further simplifying the design and implementation process.

[0107] 4. Improve data reliability and security:

[0108] The method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure integrates an ECC verification mechanism, which can detect and correct errors that may occur during data transmission, improving data reliability. At the same time, by supporting security key verification and read / write protection functions, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure provides a higher level of security protection for automotive electronic systems.

[0109] 5. Optimize system performance:

[0110] The method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure supports the Cache prefetch function, which can load data in the Flash into the Cache in advance, thereby reducing data access latency and improving system performance. In addition, through the design of the state arbiter, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure realizes the RWW (Read While Write) operation, enabling read and write operations to be performed simultaneously, further enhancing system performance.

[0111] 6. Reduce development and maintenance costs:

[0112] Since the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure adopts parametric design and modular design, the development and maintenance of the controller become simpler and more efficient. Users can easily configure the controller parameters according to their needs without significantly modifying the hardware circuit. This greatly reduces the development and maintenance costs and improves the maintainability of the system.

[0113] In summary, the method for generating a controller for multiple Flash memories provided by the embodiments of the present disclosure, through the design scheme of a multi-chip EFlash controller based on the SpinalHDL language, not only solves the deficiencies of existing EFlash controllers in terms of flexibility and scalability, but also provides a storage controller solution with high performance, high reliability, and high security for automotive electronic systems.

[0114] In some feasible examples, the target operation includes a first operation, the first operation includes a programming operation, the control unit includes write channel control logic, a MEM storage area, and a target interface, and the driving unit includes a state machine;

[0115] When the control unit executes the target memory corresponding to the storage address based on the target operation and controls the driving unit corresponding to the target memory to drive the target memory to execute the operation instruction, it is further configured to:

[0116] The MEM storage area is used to write the write data in the programming operation into the MEM storage area in response to the programming operation sent by the register unit;

[0117] The write channel control logic is used to control the state machine in the driving unit corresponding to the target memory to enter the write state through the target interface in response to the programming operation sent by the register unit;

[0118] The driving unit that enters the write state is used to read the write data from the MEM storage area and control the target memory to write the write data.

[0119] In some examples, the target interface includes one or more of a MEM interface and a FIFO interface.

[0120] In some examples, the controller 1 provided by the embodiments of the present disclosure supports a write protection function. For example, when the write protection function of the controller 1 is enabled, if the write channel control logic determines that the write address in the programming operation falls within the write protection area, writing data is prohibited. At this time, the write channel control logic returns a write error to the register bus through the register unit. The write protection area may be an area preset by the user in the Flash memory, or an area where data writing is prohibited in the Flash memory when the Flash memory is in a preset state (such as a test state). In some examples, the controller 1 provided by the embodiments of the present disclosure supports ECC verification with a configurable bit width (the data length of the data in the Flash). For example, when the controller 1 enables ECC verification with a configurable bit width, the register unit controls the MEM storage area to perform ECC encoding on the write data in the programming operation in response to the programming operation sent by the register unit to obtain encoded data, and stores the encoded data in the MEM storage area. Then, the write channel control logic is used to control the state machine in the driving unit corresponding to the target memory to enter the write state in response to the programming operation sent by the register unit through the target interface. The driving unit that enters the write state is used to read the encoded data from the MEM storage area and control the target memory to write the encoded data.

[0121] In some implementable examples, the driving unit further includes a redundant repair unit. The redundant repair unit is used to read the bad block information in the target memory. The redundant repair unit is further used to map the address corresponding to the address information in the target operation to the redundant storage area when the address corresponding to the address information in the target operation is within the address area corresponding to the block information.

[0122] In some examples, the redundant repair unit supports the bad block screening and Auto-Repair automatic repair functions of the Flash memory.

[0123] In some implementable examples, the target operation includes a first operation, the first operation includes an erase operation, and the control unit includes a write channel control logic and a target interface. When the control unit executes the target memory corresponding to the storage address in the target operation and controls the driving unit corresponding to the target memory to drive the target memory to execute the operation instruction, it is further configured to:

[0124] The write channel control logic is used to control the driving unit corresponding to the target memory to enter the erase state through the target interface in response to the erase operation sent by the register unit.

[0125] The driving unit that enters the erase state is used to control the target memory to erase the data corresponding to the erase operation.

[0126] In some implementable examples, the target operation includes a first operation, the first operation includes a data verification operation, the control unit includes write channel control logic and a target interface; when the control unit executes the target memory corresponding to the storage address in the target operation and controls the driving unit corresponding to the target memory to drive the target memory to execute the operation instruction, it is further configured as:

[0127] The write channel control logic is used to respond to the data verification operation sent by the register unit and control the target memory to read the memory state of the verification address through the driving unit corresponding to the target interface;

[0128] The target interface is used for the corresponding driving unit to receive the memory state sent by the target memory;

[0129] The write channel control logic is further used to obtain the data verification result of the target memory based on the memory state received by the target interface.

[0130] In some implementable examples, the target operation includes a second operation, the second operation includes a read operation, the control unit includes read channel control logic and a target interface; when the control unit executes the target memory corresponding to the storage address in the target operation and controls the driving unit corresponding to the target memory to drive the target memory to execute the operation instruction, it is further configured as:

[0131] The read channel control logic is used to respond to the read operation input by the data read bus and control the driving unit corresponding to the target memory to enter the read state through the control target interface.

[0132] The driving unit entering the read state is used to read the read / write data corresponding to the read / write address in the read operation from the target memory.

[0133] In some examples, the controller 1 provided by the embodiments of the present disclosure supports a read protection function. For example, when the controller 1 enables the read protection function, when the read channel control logic determines that the read address in the read operation falls into the read protection area, the data reading is prohibited, and at this time, the read channel control logic returns a read error to the data read bus. Among them, the read protection area can be an area preset by the user in the Flash memory, or the Flash memory prohibits data access when the Flash memory is in a preset state (such as the debug state), or the Flash memory prohibits data access when there is an external memory.

[0134] In some examples, the controller 1 provided by the embodiments of the present disclosure supports the function of temporarily unlocking read protection with a security key. For example, when the controller 1 enables the function of temporarily unlocking read protection with a security key, if the register unit receives the security key input from the register bus at this time, the register unit controls the write channel control logic to obtain the theoretical key stored in the Flash memory. For example, the write channel control logic receives the verification request sent by the register unit, and the write channel control logic instructs the drive unit corresponding to the verification request to obtain the theoretical key stored in the Flash memory corresponding to the drive unit through the target interface. The drive unit corresponding to the verification request stores the theoretical key stored in the Flash memory into the FIFO storage area through the target interface. When the write channel control logic determines that there is a theoretical key identical to the security key based on the security key in the verification request and the theoretical key in the FIFO storage area, it sends a verification success message to the register bus through the register unit, and instructs the read channel control logic to perform the data reading operation on the Flash memory corresponding to the drive unit corresponding to the verification request. In some implementable examples, the drive unit in the read state sends the read / write data to the read channel control logic through the target interface.

[0135] In some examples, the drive unit in the read state sends the read / write data to the data reading bus through the target interface, including:

[0136] The drive unit in the read state stores the read / write data read from the target memory into the FIFO storage area through the target interface, such as the FIFO interface. Then, the read channel control logic reads the read / write data from the FIFO storage area and feeds the read / write data back to the data reading bus.

[0137] In some implementable examples, the control unit further includes a prefetch buffer; the drive unit in the read state sends the read / write data to the prefetch buffer through the target interface; the read channel control logic reads the read / write data from the prefetch buffer.

[0138] In some examples, the prefetch buffer can be configured by parameters to determine whether to use this function. For example, when it is necessary to frequently access the stored data in the Flash memory, the prefetch buffer can be enabled, so that each time the stored data is read, x groups of stored data can be read in advance according to the data width of the read bus (such as data widths of 8-bit / 16-bit / 32-bit / 64-bit, etc.), and the read stored data is stored in the prefetch buffer; where x is greater than or equal to 1 (specifically, the user can set the value of x according to needs). In this way, when the write channel control logic of the control unit 13 receives an instruction to read the stored data in the Flash memory, by determining whether the stored data corresponding to the instruction is stored in the prefetch buffer, if it exists, the stored data is directly read from the prefetch buffer, so that there is no need to read the stored data from the Flash memory, shortening the data read time. If it does not exist, the stored data is read from the Flash memory to ensure the user experience.

[0139] In some examples, when the read channel control logic determines to start the read buffer and receives a read operation sent by the data read bus, such as reading 8-bit data in the read operation, at this time, the read channel control logic can read the stored data from the Flash memory according to a pre-specified data read amount (such as 2N). Then, the driving unit in the read state sends the read and write data to the prefetch buffer through the target interface; the read channel control logic reads the read and write data from the prefetch buffer. Since the read channel control logic reads more read and write data than actually needed and stores it in the prefetch buffer, when the data read bus continues to send a read operation for the read and write data at consecutive addresses (the read addresses of the Flash memory for two consecutive reads are consecutive) in the Flash memory next time, the stored data can be directly read from the prefetch buffer, so that there is no need to read the stored data from the Flash memory, shortening the data read time. Where N represents the amount of data to be read in the read operation, such as 8-bit.

[0140] In some implementable examples, the clock management unit is used to determine the division ratio of each Flash memory based on the clock frequency of the register unit and generate a clock signal according to the division ratio.

[0141] In some implementable examples, the clock management unit is also used to obtain the switched clock frequency in response to a system clock switching operation;

[0142] The clock management unit is also used to switch the system clock when the current clock frequency is greater than the switched clock frequency;

[0143] The clock management unit is also used to configure the switched clock frequency as the clock frequency of the register unit after switching the system clock.

[0144] In some implementable examples, the clock management unit is further configured to switch the system clock after configuring the switched clock frequency as the clock frequency of the register unit when the current clock frequency is less than the switched clock frequency. In some examples, the clock management unit is composed of a clock divider. Since most Flash memories operate at a relatively low frequency and cannot operate at the same frequency as the CPU and the controller, the clock signal needs to be divided. The clock management unit realizes the function of automatically calculating the required division ratio according to the clock frequency configured by the register unit and generating the corresponding clock signal.

[0145] In addition, the clock management unit puts forward special requirements for system clock switching. When the system switches the clock, if it switches from a high-frequency clock to a low-frequency clock, the clock can be switched first, and then the switched clock frequency can be configured into the clock frequency register of the register unit; if it switches from a low-frequency clock to a high-frequency clock, the target frequency needs to be configured into the clock frequency register in advance before the clock switching, and then the clock switching can be performed after the configuration is completed.

[0146] In some implementable examples, the register unit is further configured to perform data check on the operation data in the first operation, and send the first operation to the control unit when it is determined that the detection result has no target error; where the operation data includes one or more of an instruction, an address information, a data length, or a written data, and the target error includes one or more of an instruction error, an address misalignment, an address out-of-bounds error, a difference between the data length and the actual data amount of the written data, an address conflict corresponding to the instruction and the address information, and an address corresponding to the address information falling into the write protection area.

[0147] Embodiment 2

[0148] The structural schematic diagram of the generating device of the controller of multiple Flash memories provided in Embodiment 2 of the present application. The generating device of the controller of multiple Flash memories includes: an obtaining unit 201 and a processing unit 202.

[0149] The obtaining unit 201 is configured to obtain control parameters written in the SpinalHDL programming language; where the control parameters include the first configuration parameter of the register bus, the second configuration parameter of the data reading bus, the third configuration parameter of the register unit, the clock management unit, the control unit, and multiple driving units in the controller, and the fourth configuration parameter of at least one Flash memory controlled by the controller.

[0150] A processing unit 202 is configured to generate a control circuit of the controller based on the control parameters obtained by an obtaining unit 201. The control circuit includes a register bus, a data reading bus, and a controller. The controller includes a register unit, a clock management unit, a control unit, and a plurality of driving units, and one driving unit corresponds to one Flash memory.

[0151] In some implementable examples, the first configuration parameter includes a register type, a first decoding logic of the register bus corresponding to the register type, an address bit width, and a data bit width. The register type includes any one of an AXI-Lite bus, an advanced high-performance bus, and a peripheral bus.

[0152] In some implementable examples, the second configuration parameter includes a reading bus type, a second decoding logic of the data reading bus corresponding to the reading bus type, an address bit width of the data reading bus, a data bit width, a second quantity, a data bit width of the memory, a data bit width and a quantity of the first-in-first-out queue. The data bit width of the first-in-first-out queue is the same as the data bit width of the data reading bus, and the quantity of the data reading bus is the same as the quantity of the first-in-first-out queue.

[0153] In some implementable examples, the third configuration parameter includes a register type of the register unit, a second indication information for indicating whether the register unit enables write protection, a base address of the non-volatile memory, a first parameter configuration of the clock management unit, a second parameter configuration of the control unit, and a third parameter configuration of the driving unit.

[0154] In some implementable examples, the fourth configuration parameter includes a data bit width of the non-volatile memory, a third quantity, and a third indication parameter for indicating whether to enable a redundant driving unit.

[0155] In some implementable examples, the second configuration parameter includes a data reading quantity. The control parameter further includes a fifth configuration parameter for generating a prefetch buffer. The fifth configuration parameter includes one or more of a first indication information for indicating whether to generate a prefetch buffer, a first quantity of the smallest storage unit in the prefetch buffer generated when the first indication information indicates to generate a prefetch buffer, and a third quantity of cache blocks in the cache memory. The product of the first quantity and the data quantity of the smallest storage unit is the same as the data reading quantity.

[0156] All relevant contents of each step involved in the above method embodiment can be cited to the function description of the corresponding functional module, and its function will not be elaborated here.

[0157] Of course, the generating device of the controller for multiple Flash memories provided by the embodiments of the present invention includes but is not limited to the above modules. For example, the generating device of the controller for multiple Flash memories may further include a storage unit 203. The storage unit 203 can be used to store the program code of the generating device of the controller for multiple Flash memories, and can also be used to store the data generated during the operation of the generating device of the controller for multiple Flash memories, such as diagnostic data, etc.

[0158] Embodiment 3

[0159] Figure 3 FIG. is a schematic structural diagram of an electronic device provided by Embodiment 3 of the present disclosure. As Figure 3 shown, the electronic device may include: at least one processor 51, a memory 52, a communication interface 53, and a communication bus 54.

[0160] Next, the components of the electronic device will be specifically introduced in conjunction with Figure 3 :

[0161] Among them, the processor 51 is the control center of the electronic device, which can be a single processor or a collective term for multiple processing elements. For example, the processor 51 is a central processing unit (CPU), or can be an application specific integrated circuit (ASIC), or can be one or more integrated circuits configured to implement the embodiments of the present disclosure. For example: one or more DSPs, or one or more field programmable gate arrays (FPGAs).

[0162] In a specific implementation, as an embodiment, the processor 51 may include one or more CPUs. For example, Figure 3 the CPUs shown in Figure 3 . And, as an embodiment, the controller for multiple Flash memories may include multiple processors. For example,

[0163] The memory 52 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or can also be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 52 can exist independently and be connected to the processor 51 through the communication bus 54. The memory 52 can also be integrated with the processor 51.

[0164] In a specific implementation, the memory 52 is used to store the data in the present disclosure and execute the software programs in the present disclosure. The processor 51 can execute various functions of the air conditioner by running or executing the software programs stored in the memory 52 and calling the data stored in the memory 52.

[0165] The communication interface 53 uses any device such as a transceiver to communicate with other devices or communication networks, such as a radio access network (RAN), a wireless local area network (WLAN), a terminal, the cloud, etc.

[0166] The communication bus 54 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 3 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0167] As an example, the function implemented by the acquisition unit 201 of the generating device of the controller of multiple Flash memories is the same as Figure 3The functions of the communication interface 53 in [reference] are the same. The functions implemented by the processing unit 202 in the generating device of the multi-chip Flash memory controller are the same as those of Figure 3 the processor 51 in [reference]. The functions of the storage unit 203 in the generating device of the multi-chip Flash memory controller are the same as those of Figure 3 the memory 52 in [reference].

[0168] Embodiment 4

[0169] Embodiment 4 of the present disclosure provides a computer-readable storage medium storing computer-executable instructions. When the computer-executable instructions are executed by a processor, they are used to implement the method in any one of the embodiments.

[0170] Embodiment 5

[0171] Embodiment 5 of the present disclosure provides a computer program product. When the computer program product runs on a computer, it causes the computer to execute the method in any one of the items in any one of the embodiments.

[0172] The above are only the specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but rather will conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for generating a controller of multiple Flash memories, characterized in that: include: Acquire control parameters written in SpinalHDL programming language; wherein the control parameters include first configuration parameters of a register bus, second configuration parameters of a data read bus, third configuration parameters of a register unit, a clock management unit, a control unit and a plurality of drive units in a controller, and fourth configuration parameters of at least one Flash memory controlled by the controller; Based on the control parameters, a control circuit of the controller is generated; wherein the control circuit includes a register bus, a data reading bus and the controller, and the controller includes a register unit, a clock management unit, a control unit and multiple driving units, and one of the driving units corresponds to one of the Flash memories.

2. The method for generating a controller of multiple Flash memories according to claim 1, characterized in that: The first configuration parameter includes a register type, a first decoding logic of a register bus corresponding to the register type, an address bit width, and a data bit width; wherein the register type includes any one of an AXI-Lite bus, an advanced high performance bus, and a peripheral bus.

3. The method for generating a controller of a multi-chip Flash memory according to claim 1, characterized in that: The second configuration parameters include a read bus type, a second decoding logic of a data read bus corresponding to the read bus type, an address width, a data width, a second quantity of the data read bus, a data width of a memory, and a data width and quantity of first-in-first-out queues; wherein the data width of the first-in-first-out queue is the same as the data width of the data read bus, and the quantity of the data read buses is the same as the quantity of the first-in-first-out queues.

4. The method for generating a controller of multiple Flash memories according to claim 1, characterized in that: The third configuration parameters include the register type of the register unit, the second indication information for indicating whether the register unit is write-protected and the base address of the non-volatile memory, the first parameter configuration of the clock management unit, the second parameter configuration of the control unit and the third parameter configuration of the driving unit.

5. The method for generating a controller of multiple Flash memories according to claim 1, characterized in that: The fourth configuration parameters include a data bit width of the non-volatile memory, a third quantity, and a third indication parameter for indicating whether to enable the redundant driving unit.

6. The method for generating a controller of multiple Flash memories according to claim 1, characterized in that: The second configuration parameter includes the data read amount; The control parameters also include a fifth configuration parameter for generating a prefetch buffer, the fifth configuration parameter including one or more of first indication information of whether to generate a prefetch buffer, a first number of minimum storage units in the prefetch buffer generated when the first indication information indicates to generate a prefetch buffer, and a third number of cache blocks in the cache memory; wherein the product of the first number and the amount of data of the minimum storage unit is the same as the data read amount.

7. A device for generating a controller of a plurality of Flash memories, characterized in that: include: An acquisition unit, used to acquire control parameters written in SpinalHDL programming language; wherein the control parameters include a first configuration parameter of a register bus, a second configuration parameter of a data read bus, a third configuration parameter of a register unit, a clock management unit, a control unit and a plurality of drive units in the controller, and a fourth configuration parameter of at least one Flash memory controlled by the controller; A processing unit, used to generate a control circuit of the controller based on the control parameters acquired by the acquisition unit; wherein the control circuit includes a register bus, a data reading bus and the controller, and the controller includes a register unit, a clock management unit, a control unit and multiple driving units, and one of the driving units corresponds to one of the Flash memories.

8. An electronic device, characterized in that: include: A memory and a processor, wherein the memory is used to store a computer program; and the processor is used to enable the electronic device to implement the method for generating a controller of a multi-chip Flash memory as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the method for generating a controller of multiple Flash memories according to any one of claims 1 to 6.

10. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to implement the method for generating a controller of multiple Flash memories according to any one of claims 1 to 6.

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