Transformer type differential series resonant cavity, differential series resonant oscillator, chip and equipment

Abstract

The invention discloses a transformer type differential series resonant cavity, a differential series resonant oscillator, a chip and equipment, the resonant cavity comprises a two-port transformer and a variable capacitance module, the two-port transformer comprises an inductor LP1, an inductor LP2, an inductor LS1 and an inductor LS2 which are mutually coupled, and the variable capacitance module comprises a variable capacitor CP and a variable capacitor CS; one end of the inductor LP1 is connected with the first port, and the other end is connected with the variable capacitor CP; one end of the inductor LP2 is connected with the second port, and the other end is connected with the variable capacitor CP; one end of the inductor LS1 and one end of the inductor LS2 are connected with the third port and the fourth port respectively, and the other end of the inductor LS1 and the other end of the inductor LS2 are connected with each other; two ends of the variable capacitor CS are respectively connected with the third port and the fourth port; a plurality of pole frequencies of the voltage gain function AV are set to be equal such that AV at the zero phase increases. According to the invention, the problem that a series resonant oscillator cannot realize pure differential output in the current pure CMOS process is solved.

Description

Technical Field

[0001] The present invention relates to a local oscillator generation circuit for mixing in a wireless communication system, and particularly to a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip and a device. Background Art

[0002] In high-speed wireless and wired communications, as well as high-speed digital-to-analog / analog-to-digital converter systems, a voltage-controlled oscillator with ultra-low phase noise is often required. According to Leeson's formula, the phase noise of a voltage-controlled oscillator can be reduced by increasing the resonator voltage or decreasing the resonator inductance. However, the maximum voltage across the resonator is limited by the process, and excessively reducing the inductance value will deteriorate the quality factor of the resonator. Therefore, it is difficult to further reduce the phase noise of traditional voltage-controlled oscillators. A multi-core voltage-controlled oscillator is another solution to reduce phase noise. However, when ultra-low phase noise is required, this solution faces problems such as large on-chip area, serious inter-core mismatch, and complex power supply network.

[0003] In recent years, a series resonant voltage-controlled oscillator has been proven to be able to achieve ultra-low phase noise in a single-core architecture. To achieve series resonance, a first prior art solution uses an inverter to drive a series resonant cavity composed of an inductor and a capacitor in series, and takes out the voltage across the capacitor in the resonant cavity and loads it to the input terminal of the next-stage inverter. Finally, a combination of four inverters and the series resonant cavity is cascaded together to form a series resonant oscillator and achieve quadrature signal output. However, this technical solution requires the use of four discrete inductors, resulting in a large chip area.

[0004] A second prior art solution, based on the first prior art solution, changes the inductor in the series resonant cavity to a transformer, where the primary coil terminal of the transformer is composed of a capacitor in series with the primary inductance of the transformer, and the secondary coil terminal is composed of a capacitor in parallel with the secondary inductance of the transformer. The inverter output drives the primary coil terminal, and the voltage at the secondary coil terminal of the transformer is loaded to the input terminal of the next-stage inverter. Finally, a combination of four inverters and the transformer-type series resonant cavity is cascaded together to form a series resonant oscillator and achieve quadrature signal output. However, this technical solution has a problem of mode ambiguity, that is, there are two different oscillation frequencies. In addition, both the first prior art solution and the second prior art solution can only achieve quadrature output and cannot achieve pure differential output.

[0005] A third prior art solution uses a series resonant cavity composed of an inductor and a capacitor in series, places the series resonant cavity at the source of a cross-coupled transistor, and realizes a differential series resonant oscillator; although this solution can achieve differential output, this differential structure topology has not been able to be realized in a pure CMOS process and requires an additional bias inductor, occupying a large chip area. Summary of the Invention

[0006] To solve at least to some extent one of the technical problems existing in the prior art, an object of the present invention is to provide a transformer-type differential series resonant cavity, a differential series resonant oscillator, a chip and a device based on pole aggregation technology.

[0007] The first technical solution adopted by the present invention is:

[0008] A transformer-type differential series resonant cavity includes a two-port transformer and a variable capacitance module. The two-port transformer includes inductors L P1 , inductor L P2 and inductor L S1 , inductor L S2 . The variable capacitance module includes variable capacitors C P and variable capacitor C S ;

[0009] The same-named end of the inductor L P1 is connected to the first port, and the different-named end is connected to the variable capacitor C P ; The different-named end of the inductor L P2 is connected to the second port, and the same-named end is connected to the variable capacitor C P ;

[0010] The different-named end of the inductor L S1 and the same-named end of the inductor L S2 are respectively connected to the third port and the fourth port. The same-named end of the inductor L S1 and the different-named end of the inductor L S2 are connected to each other; The two ends of the variable capacitor C S are respectively connected to the third port and the fourth port;

[0011] The multiple pole frequencies of the voltage gain function A V of the transformer-type differential series resonant cavity are set to be equal, so that A V at zero phase increases.

[0012] Furthermore, the variable capacitor C P includes a first switched capacitor array and variable capacitor tubes C VP1 and variable capacitor tube C VP2 ; The two ends of the first switched capacitor array are respectively connected to the other ends of the inductor L P1 and the inductor L P2 ; One ends of the variable capacitor tubes C VP1 and the variable capacitor tubes C VP2 are connected to the control voltage V TUNEP ; The other ends of the variable capacitor tubes C VP1 and the variable capacitor tubes C VP2 are connected to the two ends of the first switched capacitor array;

[0013] The variable capacitor C S includes a second switched-capacitor array and variable capacitor tubes C VS1 and variable capacitor tubes C VS2 ; both ends of the second switched-capacitor array are respectively connected to an inductor L S1 and an inductor L S2 at one end; one ends of the variable capacitor tubes C VS1 and variable capacitor tubes C VS2 are connected to a control voltage V TUNES ; the other ends of the variable capacitor tubes C VS1 and variable capacitor tubes C VS2 are connected to both ends of the second switched-capacitor array.

[0014] Furthermore, the variable capacitor C P includes a first switched-capacitor array and variable capacitor tubes C VP1 and variable capacitor tubes C VP2 ; both ends of the first switched-capacitor array are respectively connected to the other end of an inductor L P1 and an inductor L P2 ; one ends of the variable capacitor tubes C VP1 and variable capacitor tubes C VP2 are connected to a control voltage V TUNEP ; the other ends of the variable capacitor tubes C VP1 and variable capacitor tubes C VP2 are connected to both ends of the first switched-capacitor array;

[0015] The variable capacitor C S includes a second switched-capacitor array, and both ends of the second switched-capacitor array are respectively connected to an inductor L S1 and an inductor L S2 at one end.

[0016] Furthermore, both the first switched-capacitor array and the second switched-capacitor array are switched-capacitor arrays based on NMOS switches, and the switched-capacitor array includes a plurality of switched-capacitor units;

[0017] The switched-capacitor unit includes a transistor M N , a resistor R B1 , a resistor R B2 , a switched capacitor C U1 , a switched capacitor C U2 , a third inverter, a fourth inverter, and a fifth inverter;

[0018] One end of the switched capacitor C U1 is connected to the drain of the transistor M N , and the other end of the switched capacitor C U1 is connected to one end of the switched-capacitor array;

[0019] The switch capacitor C U2 has one end connected to the source of transistor M N , and the other end of the switch capacitor C U2 is connected to the other end of the switch capacitor array;

[0020] The resistor R B1 has one end connected to the drain of transistor M N , and one end of the resistor R B2 is connected to the source of transistor M N ; The enable signal EN is loaded onto the gate of transistor M N after passing through the third inverter and the fourth inverter in sequence; After the enable signal EN passes through the fifth inverter, it is loaded onto the other end of the resistor R B1 and the other end of the resistor R B2 .

[0021] Furthermore, both the first switch capacitor array and the second switch capacitor array are switch capacitor arrays based on complementary switches, and the switch capacitor array includes multiple switch capacitor units;

[0022] The switch capacitor unit includes transistor M P , transistor M N , resistor R B1 , resistor R B2 , switch capacitor C U1 , switch capacitor C U2 , the third inverter, the fourth inverter, and the fifth inverter;

[0023] The drain of the transistor M P is connected to the drain of the transistor M N , and the connection point is denoted as point A; The source of the transistor M P is connected to the source of the transistor M N , and the connection point is denoted as point B;

[0024] One end of the switch capacitor C U1 is connected to point A, and the other end of the switch capacitor C U1 is connected to one end of the switch capacitor array;

[0025] One end of the switch capacitor C U2 is connected to point B, and the other end of the switch capacitor C U2 is connected to the other end of the switch capacitor array;

[0026] One end of the resistor R B1 is connected to point A, and one end of the resistor R B2 is connected to point B;

[0027] The enable signal EN is loaded onto the gate of transistor M after passing through the third inverter. P The enable signal EN is loaded onto the gate of transistor M after passing through the third inverter and the fourth inverter in sequence. N After the enable signal EN passes through the fifth inverter, it is loaded onto the other end of resistor R B1 and the other end of resistor R B2 .

[0028] The second technical solution adopted by the present invention is:

[0029] A differential series resonant oscillator, comprising a differential driver and a transformer-type differential series resonant cavity as described above;

[0030] The differential output terminals of the differential driver are connected to the first port and the second port of the transformer-type differential series resonant cavity; the differential input terminals of the differential driver are connected to the third port and the fourth port of the transformer-type differential series resonant cavity.

[0031] Further, the differential driver includes two inverters with the same structure and two capacitors C B1 , C B2 ; the input terminal of the differential driver is connected to one end of capacitors C B1 , C B2 , and the other ends of capacitors C B1 , C B2 are connected to the input terminals of the two inverters; the output terminals of the two inverters serve as the output terminals of the differential driver;

[0032] The inverter is composed of an NMOS transistor, a PMOS transistor, and a resistor R FB . The gates of the two transistors are connected together as the input terminal of the inverter, the drains of the two transistors are connected together as the output terminal of the inverter, and both ends of resistor R FB are respectively connected to the input terminal and the output terminal of the inverter; the source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply.

[0033] Further, the differential driver includes two inverters with the same structure and two capacitors C B1 , C B2 ; the input terminal of the differential driver is connected to one end of capacitors C B1 , C B2 , and the other ends of capacitors C B1 , C B2 are connected to the input terminals of the two inverters; the output terminals of the two inverters serve as the output terminals of the differential driver;

[0034] The inverter is composed of a first NMOS transistor, a second NMOS transistor, and a resistor R BComposed of, the gates of two transistors are connected together as the input terminal of the inverter, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected together as the output terminal of the inverter, and the resistor R B One end is connected to the input terminal of the inverter, and the other end is connected to the power supply; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to the ground.

[0035] Furthermore, the differential driver includes two inverters with the same structure; the input terminals and output terminals of the two inverters are respectively connected to the input terminal and output terminal of the differential driver;

[0036] The inverter is composed of an NMOS transistor and a PMOS transistor. The gates of the two transistors are connected together as the input terminal of the inverter, and the drains of the two transistors are connected together as the output terminal of the inverter; the source of the NMOS transistor is connected to the ground, and the source of the PMOS transistor is connected to the power supply;

[0037] In the transformer-type differential series resonant cavity, the inductor L S1 and the inductor L S2 One end is connected to the external bias voltage V B , and the bias voltage V B Reaches the input terminal of the inverter through the inductor L S1 and the inductor L S2 as the bias voltage of the inverter.

[0038] Furthermore, the differential driver includes two inverters with the same structure; the input terminals and output terminals of the two inverters are respectively connected to the input terminal and output terminal of the differential driver;

[0039] The inverter is composed of a first NMOS transistor and a second NMOS transistor. The gates of the two transistors are connected together as the input terminal of the inverter, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected together as the output terminal of the inverter; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to the ground;

[0040] In the transformer-type differential series resonant cavity, the inductor L S1 and the inductor L S2 One end is connected to the external bias voltage V B , and the bias voltage V B Reaches the input terminal of the inverter through the inductor L S1 and the inductor L S2 as the bias voltage of the inverter.

[0041] The third technical solution adopted by the present invention is:

[0042] A chip, including a differential series resonant oscillator as described above, and for implementing the method as described above.

[0043] The fourth technical solution adopted by the present invention is:

[0044] A communication device, including a chip as described above.

[0045] The beneficial effects of the present invention are: By constructing a transformer-type differential series resonant cavity and through the pole aggregation technology, the series resonant oscillator can achieve differential operation, which is the first oscillator to achieve differential series resonance in a pure CMOS process at present, solving the mode ambiguity problem existing in the transformer-type series resonant oscillator, and at the same time avoiding the large on-chip area problem caused by additional bias inductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following introduces the accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings in the following introduction are only for conveniently and clearly expressing some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0047] Figure 1 It is a schematic diagram of the transformer-type differential series resonant cavity of the present invention;

[0048] Figure 2 It is a schematic diagram of the differential series resonant oscillator of the present invention;

[0049] Figure 3 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 1 of the present invention;

[0050] Figure 4 It is a schematic diagram of the two-port transformer T1 in Embodiment 2 of the present invention;

[0051] Figure 5 It is the structure diagram of an embodiment of a switched capacitor array based on complementary switches provided in the embodiment of the present invention;

[0052] Figure 6 It is the test result of the tuning range of the differential series resonant oscillator provided in Embodiment 1 of the present invention;

[0053] Figure 7 It is the phase noise test curve graph of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 7.762 GHz;

[0054] Figure 8It is the phase noise test curve graph of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 9.122 GHz;

[0055] Figure 9 It is the phase noise test graph of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 1 MHz and 10 MHz frequency offsets at each frequency point;

[0056] Figure 10 It is the FoM value test graph of the differential series resonant oscillator provided in Embodiment 1 of the present invention at 1 MHz and 10 MHz frequency offsets at each frequency point;

[0057] Figure 11 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 2 of the present invention;

[0059] Figure 12 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 3 of the present invention;

[0060] Figure 13 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 4 of the present invention;

[0061] Figure 14 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 5 of the present invention;

[0062] Figure 15 It is the circuit structure diagram of the differential series resonant oscillator provided in Embodiment 6 of the present invention. Detailed implementation manners

[0063] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention. For the step numbers in the following embodiments, they are only set for the convenience of description and illustration, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0064] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc., is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0065] In the description of the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceeding", etc. are understood not to include the base number, and "above", "below", "within", etc. are understood to include the base number. If "first" and "second" are described, it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0066] In the description of the present invention, unless otherwise clearly defined, terms such as "set", "installed", "connected", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0067] Generally speaking, the purpose of the present invention is to solve the following technical problems: 1) Solve the problem that a pure differential output cannot be achieved by a series resonant oscillator in a pure CMOS process currently; 2) Solve the problem of mode ambiguity existing in a traditional transformer-type series resonant oscillator; 3) Solve the problem that a traditional series resonant oscillator occupies a large chip area; 4) Solve the problem that the bias resistance in the switched capacitor array circuit of a traditional oscillator contributes a large phase noise.

[0068] For technical problems 1)-3), the present invention provides a differential series resonant oscillator adopting a transformer aggregation technology, and the series resonant oscillator realizes a pure differential output in a pure CMOS process. In addition, by setting the two pole frequencies of the voltage gain function A of the transformer-type series resonant cavity to be close to each other and using a small transformer magnetic coupling coefficient k, the two peaks of Av are aggregated at the zero phase point, improving the gain at the zero phase point of Av, thereby improving the performance of the transformer-type series resonant oscillator in the differential working state, and thus realizing a high-performance pure differential series resonant oscillator. Since there is only a unique zero phase point in the transformer-type series resonant cavity, the proposed transformer-type differential series resonant oscillator avoids the mode ambiguity problem of the previous transformer-type orthogonal series resonant oscillator. V For technical problem 4), the present invention provides a switched capacitor array circuit adopting complementary switches. By simultaneously using NMOS and PMOS transistors as switches, the phase noise introduced by modulating the parasitic capacitances of the NMOS and PMOS transistors by the bias resistance in the switched capacitor array is mutually cancelled, thereby reducing the total phase noise contributed by the bias resistance.

[0069] The following will be described in detail with reference to the accompanying drawings and specific embodiments.

[0070] Example 1

[0071] Example 1

[0072] As Figure 1 , Figure 2 andFigure 3 As shown in Figure 3 , the circuit structure of the differential series resonant oscillator provided in this embodiment is specifically as follows:

[0073] The NMOS transistor M 1 (M 3 ) has its drain and gate terminals connected to the drain and gate terminals of the PMOS transistor M 2 (M 4 ). The resistor R FB1 (R FB2 ) is connected across the drain and gate of M 1 and M 2 (M 3 and M 4 ). The sources of M1 and M3 are connected to each other and grounded, and the sources of M 2 , M 4 are connected to each other and connected to the power supply V DD . The two ends of the five-bit switched capacitor array composed of C P1 , C P2 and SW P are connected to the two ends of the varactor diodes C V1 , C V2 . The common terminal of the varactor diodes C v1 , C v2 is connected to the voltage control signal V TUNE . The inductor L P1 (L P2 ) is connected across the drain of M 1 , M 2 (M 3 , M 4 ) and C P1 , C V1 (C P2 , C V2 ). The two ends of the five-bit switched capacitor array composed of C S1 , C S2 and SW S are connected to the two ends of the inductors L S1 , L S2 . The inductors L S1 and L S2 are directly connected. The capacitor C B1 (C B2 ) is connected across the gates of M 1 , M 2 (M 3 , M 4 ) and C S1 , L S1 (C S2 , L S2 ). The gate of the transistor M 5 (M 6 ) and M 1, M 2 (M 3 , M 4 ) are connected to the drain. The outputs V out+ and V out- of the oscillator are respectively taken out through the drains of transistors M 5 and M 6 . The sources of M 5 and M 6 are grounded.

[0074] It should be noted that the switched-capacitor array in this embodiment uses a five-bit switched-capacitor array, but it is not limited to five bits. Specifically, a switched-capacitor array with different bit values can be selected according to actual needs.

[0075] As an alternative embodiment, the two-port transformer T1 composed of L P1 , L P2 and L S1 , L S2 , the power supply, and the ground wire are as Figure 4 shown. The interface sequence is ①②③④⑤⑥⑦⑧ in turn. Among them, ①② respectively correspond to the positive electrode of L S2 and the negative electrode of L S1 . ③⑤ respectively correspond to the positive electrode and the negative electrode of L P1 . ④⑥ respectively correspond to the negative electrode and the positive electrode of L P2 . ⑦⑧ respectively correspond to the power supply and the ground wire. The inductors L P1 , L P2 and L S1 , L S2 in the transformer T1 are mutually coupled. Among them, L P1 (L P2 ) and L S1 (L S2 ) have a strong coupling with a turn ratio of 1:2.

[0076] As an alternative embodiment, the switched-capacitor array in this embodiment is a complementary-switch type switched-capacitor array, including a plurality of switched-capacitor units, as Figure 5 shown. The circuit structure of the switched-capacitor unit is specifically as follows: The drains and sources of the NMOS transistor M N and the PMOS transistor M P are connected to each other. The switched-capacitor C U1 and the bias resistor R B1 (the switched-capacitor C U2 and the bias resistor R B2 ) are connected to the drains (sources) of M N and M P . The switched-capacitor C U1 (C U2) The other end is connected to the differential series resonant oscillator circuit. The enable signal EN of the switched capacitor array is loaded onto the gate of transistor M after passing through an inverter, and this signal is loaded onto the gate of transistor M after passing through another inverter. After passing through another inverter, the EN signal is loaded onto the other ends of bias resistors R P and R N and R B1 and R B2 .

[0077] The working principle of the oscillator is described in detail below.

[0078] 1) Working principle of the fully differential, low phase noise series resonant voltage controlled oscillator

[0079] Refer to Figure 3 , the NMOS transistors M 1 (M 3 ), the PMOS transistors M 2 (M 4 ), and the feedback resistor R FB1 (R FB2 ) form a self-biased inverter to provide negative resistance for the oscillator and maintain oscillation. V DD provides the supply voltage required by the circuit. The DC current starts from V DD , flows through M 2 and M 1 (M 4 and M 3 ), and finally converges to ground. The output terminals of the inverter (the drains of M 1 , M 2 , M 3 , M 4 ) drive the transformer-type series resonant cavity composed of L P1 , L P2 , L S1 , L S2 , C P1 , C P2 , C V1 , C V2 , C S1 , C S2 . The voltage at the output terminals of the inverter is close to a square wave. Since the input impedance of the series resonant cavity is small, a large amount of current flows into the series resonant cavity, and a large amount of energy is stored in the inductance and capacitance of the resonant cavity, thus achieving ultra-low phase noise. Since the transformer-type series resonant cavity provides a large voltage gain, there is a large voltage swing at both ends (①②) of C S1 , C S2 , L S1 , L S2 . In order to ensure that this voltage swing enters transistors M 1 , M 2 ​3 , M 4 The voltage after the gate does not exceed the maximum value of the process limit, and a capacitor C is added B1 , C B2 For C S1 , C S2 , L S1 , L S2 The voltage swing at both ends (①②) is divided

[0080] Consisting of C P1 , C P2 and SW P A five-bit switched-capacitor array, and a five-bit switched-capacitor array consisting of C S1 , C S2 and SW S is used for the coarse tuning of the oscillation frequency. By changing the control voltage V V1 of the varactor diodes C V2 , TUNE continuous tuning of the frequency is achieved

[0081] The pole aggregation technique is achieved by adjusting the capacitors C P1 , C P2 , C S1 , C S2 . After adjusting the pole frequencies corresponding to C P1 , C P2 , C V1 , C V2 , L P1 , L P2 and the pole frequencies corresponding to C S1 , C S2 , L S1 , L S2 to be equal, the two voltage gain resonance peaks of the transformer-type series resonant cavity are aggregated together, increasing the voltage gain at the voltage gain zero phase point, increasing the voltage swing at both ends (①②) of C S1 , C S2 , L S1 , L S2 and the energy they store, thus reducing the phase noise of the oscillator

[0082] By adjusting the magnetic coupling coefficient k of the transformer, the input impedance of the transformer-type series resonant cavity can be flexibly adjusted, thereby achieving flexible control of power consumption and phase noise. When the magnetic coupling coefficient k is increased, the input impedance of the transformer-type series resonant cavity becomes larger, the power consumption of the oscillator decreases, and at the same time the phase noise increases; when the magnetic coupling coefficient k is decreased, the input impedance of the transformer-type series resonant cavity becomes larger, the power consumption of the oscillator increases, and at the same time the phase noise decreases

[0083] ​2) Control Principle of Switching Capacitor Array of Complementary Switches

[0084] When the enable signal EN is at a high level, the gate voltage of transistor M N is at a high level, and the gate of transistor M P is at a low level. At the same time, the drains and gates of M P and M N are both at a low level. At this time, the voltage between the gate and source of transistor M N and M P is greater than the threshold voltage, and M N and M P are both turned on. At this time, capacitors C U1 and C U2 are both loaded into the differential series resonant oscillator, increasing the equivalent capacitance of the resonator in the differential series resonant oscillator and reducing the resonant frequency of the resonator; when the enable signal EN is at a low level, the gate voltage of transistor M N is at a low level, and the gate of transistor M P is at a high level. At the same time, the drains and gates of M P and M N are both at a high level. At this time, the voltage between the gate and source of transistor M N and M P is less than the threshold voltage, and M N and M P are both turned off. At this time, capacitors C U1 and C U2 are not loaded into the differential series resonant oscillator, reducing the equivalent capacitance of the resonator in the differential series resonant oscillator and increasing the resonant frequency of the resonator.

[0085] In addition, when the enable signal EN is at a low level, the parasitic capacitances of transistors M N and M P are in series with capacitors C U1 and C U2 and are loaded into the differential series resonant oscillator. Moreover, the parasitic capacitances of transistors M N and M P are related to the voltages of the drains and sources. At this time, the thermal noise of the bias resistors R B1 and R B2 modulates and changes the parasitic capacitances of transistors M N and M P , causing the equivalent capacitance of the resonator in the differential series resonant oscillator to change accordingly, and the oscillation frequency and output signal phase of the differential series resonant oscillator to change. Since the variation relationships of the parasitic capacitances of transistors M N and M P with voltage are opposite, the thermal noise of the bias resistors R B1 and R B2 modulates transistors M Nand M P The introduced phase noises are opposite to each other and cancel each other out. Therefore, the switched capacitor array of the complementary switch of the present invention is insensitive to the noises of the bias resistors R B1 and R B2 .

[0086] Specifically, the tuning range of the embodiment of the present invention is 7.65–9.135 GHz, and the tuning range test curve is as Figure 6 shown. Figure 7 and Figure 8 respectively show the phase noise test result curves at the oscillation frequencies of 7.65 GHz and 9.135 GHz. Figure 9 shows the phase noises at 1 MHz and 10 MHz frequency offsets for each frequency point. Among them, the phase noise at 1 MHz frequency offset is -130.5 to -132 dBc / Hz, and the phase noise at 10 MHz frequency offset is -150.5 to -153 dBc / Hz. The power consumption of the embodiment of the present invention is 159–164.5 mW, and the FoM values at 1 MHz and 10 MHz frequency offsets are 186.4–189 dBc / Hz and 186.5–190 dBc / Hz respectively, as Figure 10 shown. In summary, the embodiment of the present invention realizes a differential series resonant voltage controlled oscillator with ultra-low phase noise and compact area.

[0087] Based on the above, the differential series resonant oscillator of this embodiment has at least the following advantages and

[0088] beneficial effects compared with the prior art:

[0089] (1) The present invention proposes a fully differential type series resonant oscillator, which can achieve a pure differential output under a pure CMOS process, solves the mode ambiguity problem existing in the traditional transformer type series resonant oscillator, occupies a smaller chip area, has a wider tuning range, and the power consumption and phase noise are flexibly controllable.

[0090] (2) The present invention proposes a complementary switch type switched capacitor array, which solves the problem of large noise contribution of bias resistors in the traditional switched capacitor array.

[0091] Embodiment 2

[0092] As Figure 11 shown, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that: the transformer type series resonant cavity consists of inductors L P1 , L P2 , L S1 , L S2 and capacitors C P1 , C P2 , C S1 , CS2 , C VP1 , C VP2 , C VS1 , C VS2 The oscillator is composed of TUNEP and V TUNES Control variable capacitor C VP1 , C VP2 , C VS1 , C VS2 The capacitance value of the differential series resonant cavity is changed to change the resonant frequency of the differential series resonant cavity to achieve a continuous tuning function. For example, in the process of achieving continuous tuning, the control voltage V TUNEP Follow V TUNES , thereby ensuring that the frequencies of the two poles in the proposed differential series resonant cavity change synchronously, thereby reducing the variation of circuit performance during continuous tuning.

[0093] The differential series resonant oscillator of this embodiment can obtain the same functions and beneficial effects as the oscillator of Embodiment 1.

[0094] Example 3

[0095] like Figure 12 As shown, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the inverter is a non-self-biased inverter, and the active drive part is composed of transistors M1, M2, M3, M4 and bias resistor R B1 , R B2 composition, external bias voltage V B Through the bias resistor R B1 , R B2 Applied to the gates of transistors M1, M2, M3, and M4 to achieve DC bias. Similar to Embodiment 1, the transformer-type series resonant cavity is still composed of an inductor L P1 , L P2 , L S1 , L S2 And the capacitor C P1 , C P2 , C S1 , C S2 , C V1 , C V2 composition.

[0096] The differential series resonant oscillator of this embodiment can obtain the same functions and beneficial effects as the oscillator of Embodiment 1.

[0097] Example 4

[0098] like Figure 13As shown, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the active drive part consists of NMOS transistors M1, M2, M3, M4 and bias resistors R B1 , R B2 , R B3 , R B4 . NMOS transistors M1, M2 (M3, M4) form a full NMOS inverter, and the input terminals of M1, M2 (M3, M4) are respectively connected to the V B1 , C B2 (C B3 , C B4 ) of the differential series resonant cavity through voltage dividing capacitors C SN , V SP (V SP , V SN ) terminals. The power supply voltage provides a bias voltage for the gates of transistors M1, M2, M3, M4 through bias resistors R B1 , R B2 , R B3 , R B4 . Similar to Embodiment 1, the transformer-type series resonant cavity still consists of inductors L P1 , L P2 , L S1 , L S2 and capacitors C P1 , C P2 , C S1 , C S2 , C V1 , C V2 .

[0099] The differential series resonant oscillator of this embodiment can achieve the same functions and beneficial effects as the oscillator in Embodiment 1.

[0100] Embodiment 5

[0101] As Figure 14 shown, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator in Embodiment 1 is that the active drive part consists of transistors M1, M2, M3, M4, and the gates are directly connected to the differential series resonant cavity. The gate bias voltage V B is applied to the gates of transistors M1, M2, M3, M4 from the center tap positions of inductors LS1 and LS2. Similar to Embodiment 1, the transformer-type series resonant cavity still consists of inductors L P1 , L P2 , L S1 , L S2 and capacitors C P1 , C P2 , C S1 , CS2 , C V1 , C V2 are composed of

[0102] The differential series resonant oscillator of this embodiment can achieve the same functions and beneficial effects as the oscillator of Embodiment 1.

[0103] Embodiment 6

[0104] As Figure 15 shown, the main difference between the differential series resonant oscillator provided in this embodiment and the oscillator of Embodiment 1 is that the inductors L P1 , L P2 , L S1 , L S2 have magnetic coupling between each other, and the magnetic coupling coefficients are k 21 , k 31 , k 41 , k 32 , k 42 , k 43 . Similar to Embodiment 1, the transformer-type series resonant cavity is still composed of inductors L P1 , L P2 , L S1 , L S2 and capacitors C P1 , C P2 , C S1 , C S2 , C V1 , C V2 ; the active drive part is still composed of transistors M1, M2, M3, and M4.

[0105] The differential series resonant oscillator of this embodiment can achieve the same functions and beneficial effects as the oscillator of Embodiment 1.

[0106] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0107] The above embodiments are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those of ordinary skill in the art to understand the content of the present invention and implement it accordingly, and it should not be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the essence of the content of the present invention should be covered within the protection scope of the present invention.

Claims

1. A transformer type differential series resonant cavity, characterized in that: It includes a two-port transformer and a variable capacitor module. The two-port transformer includes a mutually coupled inductor L P1 、Inductance L P2 and inductor L S1 、Inductance L S2 The variable capacitor module includes a variable capacitor C P and variable capacitor C S ; The inductance L P1 One end is connected to the first port, and the other end is connected to the variable capacitor C P The inductor L P2 One end is connected to the second port, and the other end is connected to the variable capacitor C P ; The inductance L S1 and inductor L S2 One end of the inductor L is connected to the third port and the fourth port respectively. S1 and inductor L S2 The other ends of the variable capacitor C S Two ends of the device are connected to the third port and the fourth port respectively; The voltage gain function A of the transformer-type differential series resonant cavity V The multiple pole frequencies of the V Increase.

2. The transformer-type differential series resonant cavity according to claim 1, characterized in that: The variable capacitor C P It includes a first switch capacitor array and a variable capacitor tube C VP1 And variable capacitance tube C VP2 The two ends of the first switch capacitor array are respectively connected to the inductor L P1 and inductor L P2 The other end of the variable capacitance tube C VP1 And variable capacitance tube C VP2 One end is connected to the control voltage V TUNEP The variable capacitance tube C VP1 And variable capacitance tube C VP2 The other end of the capacitor is connected to two ends of the first switch capacitor array; The variable capacitor C S The second switch capacitor array and the variable capacitor C VS1 And variable capacitance tube C VS2 The two ends of the second switch capacitor array are respectively connected to the inductor L S1 and inductor L S2 One end of the variable capacitance tube C VS1 And variable capacitance tube C VS2 One end is connected to the control voltage V TUNES The variable capacitance tube C VS1 And variable capacitance tube C VS2 The other end is connected to two ends of the second switch capacitor array.

3. The transformer-type differential series resonant cavity according to claim 1, characterized in that: The variable capacitor C P It includes a first switch capacitor array and a variable capacitor tube C VP1 And variable capacitance tube C VP2 The two ends of the first switch capacitor array are respectively connected to the inductor L P1 and inductor L P2 The other end of the variable capacitance tube C VP1 And variable capacitance tube C VP2 One end is connected to the control voltage V TUNEP The variable capacitance tube C VP1 And variable capacitance tube C VP2 The other end of the capacitor is connected to two ends of the first switch capacitor array; The variable capacitor C S The second switch capacitor array includes two ends of which are connected to an inductor L S1 and inductor L S2 one end.

4. A transformer-type differential series resonant cavity according to claim 2 or 3, characterized in that: The first switch capacitor array and the second switch capacitor array are both switch capacitor arrays based on NMOS switches, and the switch capacitor arrays include a plurality of switch capacitor units; The switch capacitor unit includes a transistor M N , resistor R B1 , resistor R B2 , switch capacitor C U1 , switch capacitor C U2 , a third inverter, a fourth inverter and a fifth inverter; The switch capacitor C U1 One end of the transistor M N The drain, switch capacitor C U1 The other end is connected to one end of the switch capacitor array; The switch capacitor C U2 One end of the transistor M N The source of the switch capacitor C U2 The other end of is connected to the other end of the switched capacitor array; The resistor R B1 One end of the transistor M N The drain, the resistor R B2 One end of the transistor M N The source of The enable signal EN is sequentially passed through the third inverter and the fourth inverter and then loaded to the transistor M. N The gate of the enable signal EN passes through the fifth inverter and is loaded to the resistor R B1 The other end and resistor R B2 the other end.

5. A transformer-type differential series resonant cavity according to claim 2 or 3, characterized in that: The first switched capacitor array and the second switched capacitor array are both switched capacitor arrays based on complementary switches, and the switched capacitor arrays include a plurality of switched capacitor units; The switch capacitor unit includes a transistor M P , transistor M N , resistor R B1 , resistor R B2 , switch capacitor C U1 , switch capacitor C U2 , a third inverter, a fourth inverter and a fifth inverter; The transistor M P The drain of transistor M N The drain of transistor M is connected, and the connection point is marked as point A; P The source of transistor M N The source of is connected, and the connecting point is marked as point B; The switch capacitor C U1 One end of the switch capacitor C is connected to point A. U1 The other end is connected to one end of the switched capacitor array; The switch capacitor C U2 One end of the switch capacitor C is connected to point B. U2 The other end of is connected to the other end of the switched capacitor array; The resistor R B1 One end of the resistor R is connected to point A. B2 Connect one end of the The enable signal EN is loaded to the transistor M after passing through the third inverter. P The enable signal EN is sequentially passed through the third inverter and the fourth inverter and then loaded to the transistor M. N The gate of the enable signal EN passes through the fifth inverter and is loaded to the resistor R B1 The other end and resistor R B2 the other end.

6. A differential series resonant oscillator, characterized in that: A differential driver and a transformer-type differential series resonant cavity as claimed in any one of claims 1 to 5; The differential output end of the differential driver is connected to the first port and the second port of the transformer type differential series resonant cavity; The differential input terminal of the differential driver is connected to the third port and the fourth port of the transformer-type differential series resonant cavity.

7. The differential series resonant oscillator according to claim 6, characterized in that: The differential driver includes two inverters with the same structure and two capacitors C B1 , C B2 The input terminal of the differential driver is connected to the capacitor C B1 , C B2 One end of the capacitor C B1 , C B2 The other end of is connected to the input ends of two inverters; the output ends of the two inverters serve as the output ends of the differential driver; The inverter is composed of an NMOS transistor, a PMOS transistor and a resistor R FB The gates of the two transistors are connected as the input of the inverter, the drains of the two transistors are connected as the output of the inverter, and the resistor R FB The two ends are respectively connected to the input end and the output end of the inverter; the source of the NMOS transistor is connected to the ground, and the source of the PMOS transistor is connected to the power supply.

8. The differential series resonant oscillator according to claim 6, characterized in that: The differential driver includes two inverters with the same structure and two capacitors C B1 , C B2 The input terminal of the differential driver is connected to the capacitor C B1 , C B2 One end of the capacitor C B1 , C B2 The other end of is connected to the input ends of two inverters; the output ends of the two inverters serve as the output ends of the differential driver; The inverter is composed of a first NMOS transistor, a second NMOS transistor and a resistor R B The gates of the two transistors are connected as the input of the inverter, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected as the output of the inverter, and the resistor R B One end is connected to the input end of the inverter, and the other end is connected to the power supply; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to the ground.

9. The differential series resonant oscillator according to claim 6, characterized in that: The differential driver comprises two inverters of the same structure; the input end and the output end of the two inverters are respectively connected to the input end and the output end of the differential driver; The inverter is composed of an NMOS transistor and a PMOS transistor, the gates of the two transistors are connected as the input end of the inverter, and the drains of the two transistors are connected as the output end of the inverter; the source of the NMOS transistor is connected to the ground, and the source of the PMOS transistor is connected to the power supply; In the transformer type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B connected, bias voltage V B Through the inductor L S1 and inductor L S2 Arrives at the input terminal of the inverter and serves as the bias voltage of the inverter.

10. The differential series resonant oscillator according to claim 6, characterized in that: The differential driver comprises two inverters of the same structure; the input end and the output end of the two inverters are respectively connected to the input end and the output end of the differential driver; The inverter is composed of a first NMOS transistor and a second NMOS transistor, the gates of the two transistors are connected as the input end of the inverter, the source of the first NMOS transistor and the drain of the second NMOS transistor are connected as the output end of the inverter; the drain of the first NMOS transistor is connected to the power supply, and the source of the second NMOS transistor is connected to the ground; In the transformer type differential series resonant cavity, the inductor L S1 and inductor L S2 One end is connected to the external bias voltage V B connected, bias voltage V B Through the inductor L S1 and inductor L S2 Arrives at the input terminal of the inverter and serves as the bias voltage of the inverter.

11. A chip, characterized in that: Comprising a differential series resonant oscillator as described in any one of claims 7-10.

12. A communication device, characterized in that: The communication device comprises the chip as claimed in claim 11.

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