Double-gate structure for high-performance MOSFET and optimization method

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a dual-gate structure and an optimization method for high-performance MOSFETs. Background Art

[0002] With the rapid development of semiconductor devices towards high performance and high integration, traditional single-gate MOSFETs gradually expose significant technical bottlenecks at the nanoscale. First, the short-channel effect weakens the gate's control ability over the channel, leading to an increase in leakage current and threshold voltage drift, severely restricting the miniaturization process of the device. Second, the electric field concentration phenomenon at the gate edge is significant in the single-gate structure, easily causing local breakdown, which limits the breakdown voltage and reliability of the device. In the prior art, although there are attempts at multi-gate structures or doping optimization, they are often accompanied by problems such as high process complexity, increased manufacturing cost, and insufficient thermal stability. For example, complex multi-gate designs are difficult to be compatible with existing lithography processes, and the improvement effect of doping layer optimization on the electric field distribution is limited. Therefore, there is an urgent need for a new MOSFET structure with high performance, high reliability, and process friendliness to break through the existing technical bottlenecks.

[0003] A prior patent discloses a trench-gate SiC MOSFET device with high performance (publication number CN117766587A), including: a semiconductor substrate, a buffer layer, a breakdown voltage layer, and a current spreading layer are sequentially arranged on the drain ohmic contact electrode; two trenches are arranged in the breakdown voltage layer, the trenches are filled with polysilicon gates, electric field shielding regions are respectively arranged at the bottoms of the two trenches, P-type connection regions connected to the electric field shielding regions are alternately arranged between the two trenches, and channels are arranged in the P-type connection regions. In the technology disclosed in this patent, due to the narrow conduction path, the on-resistance is relatively high, and the current driving ability is insufficient, making it difficult to meet the requirements of high-frequency and high-power applications. Summary of the Invention

[0004] The present invention provides a dual-gate structure and an optimization method for high-performance MOSFETs to solve the existing technical problems and address the issues in the above background art.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a dual-gate structure for high-performance MOSFETs is provided, which is composed of a plurality of MOS cells. Each MOS cell includes a drain, a source, a gate, a gate oxide layer, and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes an N substrate layer, an N diffusion layer, a P- layer, a P-well layer, and an N-well layer. There are two gates in each MOS cell, and they are respectively located on the left and right sides within the gate oxide layer.

[0006] Further, the cross-sectional profile of the gate oxide layer is semicircular; polysilicon is provided inside the gate oxide layer and between two gates, and the polysilicon is in ohmic contact with the source electrode. The cross-sectional depth of the polysilicon is times that of the two gates.

[0007] Further, the polysilicon further includes side silicon layers, and the cross-sectional profile of the side silicon layers is thick at the bottom and narrow at the top.

[0008] Further, a high-resistance doped layer is filled in the middle of the side silicon layers, and the high-resistance doped layer divides the side silicon layers into left and right parts.

[0009] Further, the cross-sectional profile of the gate oxide layer is rectangular; the two gates further include rectangular gates. Rectangular silicon is provided inside the gate oxide layer and between two rectangular gates, and the cross-sectional depth of the rectangular silicon is the same as that of the rectangular gates.

[0010] Further, the N diffusion layer further includes a low-doped N- layer, and the low-doped N- layer is located between the N substrate layer and the gate oxide layer.

[0011] An optimization method for a high-performance MOSFET double-gate structure specifically includes: S1. Using an N-type substrate layer as a substrate, an N diffusion layer and a low-doped N- layer are formed by epitaxial growth. S2. A P- layer, a P well layer, and an N well layer are sequentially deposited on the N diffusion layer to form a multi-layer doped structure. S3. A gate oxide layer is formed on the surface of the semiconductor epitaxial layer by chemical vapor deposition. S4. Polysilicon is deposited on both sides of the gate oxide layer to form left and right gates, polysilicon is filled between the double gates, and its doping concentration is adjusted by ion implantation to ensure that the depth of the polysilicon is times that of the gate depth; S5. Side silicon layers are formed on both sides of the polysilicon, and an inclined ion implantation is used to achieve the profile shape of the side silicon layers that is thick at the bottom and narrow at the top. S6. A high-resistance doped layer is implanted in the middle region of the side silicon layers to divide the side silicon layers into left and right parts. S7. Source and drain electrode contacts are formed through a metallization process.

[0012] Further, in step S5, by optimizing the inclined ion implantation angle at , the ratio of the bottom width to the top narrow region of the side silicon layers is controlled.

[0013] Further, in step S6, a low-doped N-layer can be introduced between the N diffusion layer and the gate oxide layer, where the doping concentration of the low-doped N-layer is lower than that of the N diffusion layer by an order of magnitude.

[0014] A dual-gate structure and optimization method for high-performance MOSFET provided by the present invention, compared with the prior art, the effects achieved by this method are as follows: 1. Through the dual-gate structure, geometric shape optimization, doping layer design and process innovation, the present invention significantly improves the switching speed, breakdown voltage, thermal stability and integration of MOSFET, while reducing the leakage current and on-resistance, and is applicable to high-performance power devices and high-frequency application scenarios.

[0015] 2. By jointly regulating the channel by the gates on both the left and right sides, the present invention enhances the control ability of carriers, so that the channel turn-on / turn-off time can be shortened through the dual-gate synergy, and the dual-gate electric fields are superimposed to suppress subthreshold leakage, and this more uniform electric field distribution reduces the influence of the short-channel effect.

[0016] 3. By using this semi-circular structure to disperse the electric field to increase the breakdown voltage, reduce the electric field concentration at the gate edge, and improve the current driving ability, and the polysilicon-ohmic contact with the source can reduce the contact resistance heating.

[0017] 4. Since the rectangular structure of the present invention matches the existing lithography process, the manufacturing process of the rectangular gate and silicon filling can be simplified, and the rectangular silicon has the same depth as the gate, ensuring the electric field uniformity and threshold voltage stability.

[0018] 5. By introducing a low-doped N-layer between the N substrate and the gate oxide layer, the present invention forms a buffer with the low-doped N-layer to reduce the leakage between the N substrate layer and the gate oxide layer, and this structure also optimizes the electric field gradient, enhances the breakdown voltage of the device, and reduces the parasitic capacitance to improve the high-frequency response speed. Description of the Drawings

[0019] Figure 1 is a schematic structural diagram of Embodiment 1 in the present invention; Figure 2 is a schematic structural diagram of Embodiment 2 in the present invention; Figure 3 is a schematic structural diagram of Embodiment 3 in the present invention; Figure 4 is a schematic structural diagram of Embodiment 4 in the present invention; Figure 5 is a schematic structural diagram of Embodiment 5 in the present invention; Figure 6 is a comparison diagram of current density between the dual-gate structure and the traditional single-gate structure in the present invention.

[0020] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Gate oxide layer; 5. N-type substrate layer; 6. N-diffusion layer; 7. P-layer; 8. P-well layer; 9. N-well layer; 10. Polysilicon; 11. High-resistance doping layer; 101. Side silicon layer; 102. Rectangular silicon; 31. Rectangular gate; 61. Low-doped N-layer. Detailed implementation manners

[0021] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] As Figures 1-5 shown, an optimization method for a high-performance MOSFET double-gate structure specifically includes: Step 1: Use the N-type substrate layer 5 as the substrate, and form the N-diffusion layer 6 and the low-doped N-layer 61 through epitaxial growth; this step precisely controls the doping concentration gradient through epitaxial growth, thereby forming a semiconductor layer with low defects and providing an electrical performance basis for the subsequent structure.

[0023] Step 2: Deposit the P-layer 7, the P-well layer 8, and the N-well layer 9 in sequence on the N-diffusion layer to form a multi-layer doping structure.

[0024] Step 3: Form the gate oxide layer 4 on the surface of the semiconductor epitaxial layer through chemical vapor deposition.

[0025] Step 4: Deposit polysilicon on both sides of the gate oxide layer 4 to form two left and right gates 3, fill polysilicon 10 between the double gates 3, and adjust its doping concentration through ion implantation to ensure that the depth of the polysilicon 10 is 1.2 - 1.7 times the gate depth; this adjustment of the polysilicon doping concentration through ion implantation to ensure a depth of 1.2 - 1.7 times that of the gate 3 can optimize the conduction path, reduce the on-resistance, and avoid short circuits between the gates 3.

[0026] Step 5: Form side silicon layers 101 on both sides of the polysilicon 10, and use inclined ion implantation to achieve a bottom-thick and top-narrow profile shape of the side silicon layer 101; and in this step, by optimizing the inclined ion implantation angle at 30° - 60°, the ratio of the bottom width to the top narrow region of the side silicon layer 101 is further controlled; the inclination angle controls the implantation depth and distribution, forming a bottom-thick and top-narrow profile, enhancing the uniformity of current distribution, and reducing the risk of local overheating.

[0027] Step 6: Inject a high-resistance doping layer 11 into the middle region of the side silicon layer 101 to divide the side silicon layer 101 into left and right parts; in this step, a lightly doped N- layer 61 can also be introduced between the N diffusion layer 6 and the gate oxide layer 4, where the doping concentration of the lightly doped N- layer 61 is 1-2 orders of magnitude lower than that of the N diffusion layer 6. A high-resistance region is formed by selective ion implantation to isolate the left and right current paths, suppress crosstalk and parasitic capacitance, and improve high-frequency performance.

[0028] Step 7: Form electrode contacts for the source electrode 2 and the drain electrode 1 through a metallization process. The metallization process forms a low-resistance metal electrode by evaporation to reduce the contact resistance and improve the overall efficiency and power handling capacity of the device.

[0029] Example 1 As Figure 1 shown, according to one aspect of the present invention, a double-gate structure for a high-performance MOSFET is provided, which is composed of a plurality of MOS cells. A single MOS cell includes a drain electrode 1, a source electrode 2, a gate electrode 3, a gate oxide layer 4, and a semiconductor epitaxial layer; the semiconductor epitaxial layer includes an N substrate layer 5, an N diffusion layer 6, a P- layer 7, a P well layer 8, and an N well layer 9. There are two gate electrodes 3 in a single MOS cell, and they are respectively located on the left and right sides within the gate oxide layer 4. The channels are jointly regulated by the gate electrodes 3 on the left and right sides to enhance the control ability of carriers, so that the channel turn-on / turn-off time can be shortened through the double-gate cooperative effect, and the subthreshold leakage current is suppressed by the superposition of the double-gate electric fields, and this more uniform electric field distribution reduces the influence of the short-channel effect.

[0030] Example 2 As Figure 2 、 6 shown, the cross-sectional profile of the gate oxide layer 4 is semicircular; polysilicon 10 is provided inside the gate oxide layer 4 and between the two gate electrodes 3, and the polysilicon 10 is in ohmic contact with the source electrode 2; the cross-sectional depth of the polysilicon 10 is 1.2-1.7 times the cross-sectional depth of the two gate electrodes 3. In this embodiment, the electric field distribution is optimized through the semicircular gate oxide layer 4, and the conductivity is enhanced by controlling the depth of the polysilicon 10. This semicircular structure disperses the electric field, increases the breakdown voltage, and reduces the electric field concentration at the gate edge; and the depth of the polysilicon 10 (1.2-1.7 times the depth of the gate electrode 3) expands the conduction path (as Figure 6 shown), improves the current driving ability, and the ohmic contact between the polysilicon 10 and the source electrode 2 can reduce the contact resistance heating.

[0031] Example 3 As Figure 3As shown, the polysilicon 10 further includes a side silicon layer 101, and the cross-sectional profile of the side silicon layer 101 is in the shape of being thick at the bottom and narrow at the top. A high-resistance doping layer 11 is filled in the middle of the side silicon layer 101, and the high-resistance doping layer 11 divides the side silicon layer 101 into two parts, left and right. The profile of the side silicon layer 101 being thick at the bottom and narrow at the top and combined with the high-resistance doping layer 11 is used to adjust the current path, and the shape of the side silicon layer 101 can reduce the local current density and reduce the hot spot effect; the side silicon layer 101 is divided by the high-resistance doping layer 11 to suppress the parasitic capacitance and leakage phenomenon.

[0032] Embodiment 4 As Figure 4 shown, the cross-sectional profile of the gate oxide layer 4 is rectangular; the two gate electrodes 3 further include rectangular gates 31; a rectangular silicon 102 is provided inside the gate oxide layer 4 and between the two rectangular gates 31, and the cross-sectional depth of the rectangular silicon 102 is the same as the cross-sectional depth of the rectangular gate 31. The rectangular gate 31 and the silicon filling simplify the manufacturing process because the rectangular structure matches the existing lithography process and reduces the manufacturing cost. And the rectangular silicon 102 has the same depth as the gate electrode 3 to ensure the electric field uniformity and the threshold voltage stability. And this regular structure is convenient for the arrangement of the cell array and improves the device density.

[0033] Embodiment 5 As Figure 5 shown, the N diffusion layer 6 further includes a low-doped N- layer 61, and the low-doped N- layer 61 is located between the N substrate layer 5 and the gate oxide layer 4. Introducing the low-doped N- layer 61 between the N substrate 5 and the gate oxide layer 4 allows the low-doped N- layer 61 to form a buffer to reduce the leakage between the N substrate layer 5 and the gate oxide layer 4. And this structure also optimizes the electric field gradient, enhances the breakdown voltage of the device, reduces the parasitic capacitance, and improves the high-frequency response speed.

[0034] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the present invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent should be subject to the appended claims.

Claims

1. A dual-gate structure for high-performance MOSFET, comprising a plurality of MOS cells, wherein each of the MOS cells comprises a drain (1), a source (2), a gate (3), a gate oxide layer (4) and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer (5), an N diffusion layer (6), a P-layer (7), a P well layer (8) and an N well layer (9), characterized in that: There are two gates (3) in a single MOS cell, and they are located on the left and right sides of the gate oxide layer (4) respectively.

2. The dual-gate structure for high-performance MOSFET according to claim 1, characterized in that: The cross-sectional profile of the gate oxide layer (4) is in a semicircular shape; polysilicon (10) is provided inside the gate oxide layer (4) and between the two gate electrodes (3), and the polysilicon (10) is in ohmic contact with the source electrode (2); The cross-sectional depth of the polysilicon (10) is 1.2-1.7 times the cross-sectional depth of the two gates (3).

3. The dual-gate structure for high-performance MOSFET according to claim 2, characterized in that: The polysilicon (10) further comprises a side silicon layer (101), and the cross-sectional profile of the side silicon layer (101) is in a shape of being thick at the bottom and narrow at the top.

4. The dual-gate structure for high-performance MOSFET according to claim 3, characterized in that: The middle of the side silicon layer (101) is filled with a high-resistance doping layer (11), wherein the high-resistance doping layer (11) divides the side silicon layer (101) into two left and right parts.

5. The dual-gate structure for high-performance MOSFET according to claim 1, characterized in that: The cross-sectional profile of the gate oxide layer (4) is in a rectangular shape; the two gate electrodes (3) further include a rectangular gate (31); A rectangular silicon (102) is provided inside the gate oxide layer (4) and between the two rectangular gates (31); the cross-sectional depth of the rectangular silicon (102) is the same as the cross-sectional depth of the rectangular gates (31).

6. The dual-gate structure for high-performance MOSFET according to claim 5, characterized in that: The N diffusion layer (6) further comprises a low-doped N-layer (61), wherein the low-doped N-layer (61) is located between the N substrate layer (5) and the gate oxide layer (4).

7. An optimization method for a high-performance MOSFET dual-gate structure, characterized in that: Applied to the dual-gate structure according to any one of claims 1 to 6, the optimization method specifically comprises: S1, using an N-type substrate layer (5) as a substrate, forming an N diffusion layer (6) and a low-doped N-layer (61) by epitaxial growth; S2, depositing a P-layer (7), a P well layer (8) and an N well layer (9) in sequence on the N diffusion layer to form a multi-layer doping structure; S3, forming a gate oxide layer (4) on the surface of the semiconductor epitaxial layer by chemical vapor deposition; S4, depositing polysilicon on both sides of the gate oxide layer (4) to form two left and right gates (3), filling polysilicon (10) between the two gates (3), and adjusting its doping concentration by ion implantation to ensure that the depth of the polysilicon (10) is 1.2-1.7 times the depth of the gate; S5, forming side silicon layers (101) on both sides of the polysilicon (10), and using inclined ion implantation to achieve a profile shape in which the side silicon layer (101) is thick at the bottom and narrow at the top; S6, implanting a high-resistance doped layer (11) into the middle region of the side silicon layer (101) to divide the side silicon layer (101) into two left and right parts; S7. Forming electrode contacts of the source (2) and the drain (1) through a metallization process.

8. The optimization method for high performance MOSFET dual gate structure according to claim 7, characterized in that: In the step S5, the ratio of the bottom width to the top narrow area of ​​the side silicon layer (101) is controlled by optimizing the inclined ion implantation angle to be between 30° and 60°.

9. The optimization method for high performance MOSFET dual-gate structure according to claim 7, characterized in that: In step S6, a low-doped N-layer (61) may also be introduced between the N diffusion layer (6) and the gate oxide layer (4), wherein the doping concentration of the low-doped N-layer (61) is 1-2 orders of magnitude lower than that of the N diffusion layer (6).

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