A phase-controlled synchronization method for shortwave array signals based on pulse programming

Through the pulse programming method, FPGA is used to generate synchronous main clock and sub-clock signal groups, eliminating the impact of layout and routing delay and clock jitter, achieving high-precision synchronization of short-wave array systems, and solving the problem of low synchronization accuracy of multi-channel array signals.

CN120111646BActive Publication Date: 2025-08-19CHINESE PEOPLES LIBERATION ARMY UNIT 32802
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Patent Information

Application Number
CN202510284497.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-03-11
Publication Date
2025-08-19
Estimated Expiration
2045-03-11

AI Technical Summary

Technical Problem

In existing short-wave array systems, the synchronization accuracy of multi-channel array signals is affected by factors such as layout and routing delay, clock offset and clock jitter, making it difficult to achieve accurate array signal synchronization.

Method used

Using a pulse programming method, the synchronization signal FPGA and the array signal FPGA are used to generate the N+1 main clock signal, phase fine-tuning and frequency division processing are performed, and the synchronous main clock signal and sub-clock signal group are generated, and the array signal trigger operation is used to eliminate the influence of layout and wiring delay and clock jitter, and finally a digital radio frequency signal is generated.

Benefits of technology

It realizes stable and reliable synchronization of multi-channel array signals, eliminates the influence of factors such as wiring delay and clock jitter, improves synchronization accuracy, and ensures the effect of array phased synthesis.

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Abstract

The present invention discloses a pulse programming-based shortwave array signal phase-controlled synchronization method. This method can eliminate errors caused by layout and routing delays, clock offsets, and clock jitter through pulse programming, achieving precise array signal synchronization. The method's main implementation process includes: 1) Synchronous clock generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving, and buffering, N+1 stable and synchronized master clocks are generated. Then, N+1 sub-clocks with different frequency synchronization are generated through clock derivation. 2) Programmable pulse generation: Upon receiving an external signal generation instruction, one pulse is generated based on the synchronized master clock. Then, pulse programming is used to generate pulses for other master and sub-clocks for synchronous triggering of array signal generation. 3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition and baseband signal generation. Under the triggering of the master clock pulse, the low-rate baseband signal is processed through baseband signal processing to obtain a high-rate baseband signal. A carrier signal corresponding to the initial phase is generated according to the array output phase requirement. Orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain the array signal for transmission.
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