Planar gate MOSFET device structure capable of improving irradiation capability and manufacturing method thereof

Abstract

The invention discloses a planar gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure capable of improving irradiation capability and a manufacturing method thereof. A substrate gradient buffer region is added between a substrate and an N-drift region of a conventional planar structure MOSFET; a P-type isolation layer and a P-type isolation layer gradient buffer region are added between the P-Well region and the N-drift region; a P-Plus region gradient buffer region is additionally arranged between the P-Plus region and the P-Well region; an N-Plus region gradient buffer region is additionally arranged between the N-Plus region and the P-Well region; a grid electrode is set as a separation grid electrode, and a P-type high-energy particle injection layer is integrated in the middle of the separation grid electrode. The arranged substrate gradient buffer region can reduce a peak electric field caused by high-energy particles injected from any region of the device in the irradiation period, and the probability that the device is out of control in the irradiation period of the high-energy particles is reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor devices and relates to a planar gate MOSFET device structure with improved radiation capability and a manufacturing method thereof. Background Art

[0002] With the continuous development of power electronics technology towards high energy efficiency, high power density and miniaturization, power switching devices are applied in more and more fields. Planar gate MOSFET, as a representative device of power switching devices, is widely used in new energy vehicles, photovoltaic power generation, rail transportation, smart grid, aerospace and other fields. In the fields of photovoltaic power generation and aerospace, there are high requirements for the radiation resistance of devices, but the radiation resistance of commercial MOSFET is far from expected. The reason is that when MOSFET devices are irradiated by high-energy particles, a large number of electrons and holes will be generated inside the device, resulting in the conduction of parasitic npn transistors, high local energy dissipation at the junction of different doping concentrations, resulting in the inability to turn off the MOSFET device, or a large number of holes accumulate under the gate to break down the gate, resulting in the inability to control the MOSFET device. At present, how to improve the radiation resistance of MOSFET devices has become a hot research point.

[0003] In the latest technology, there are ways to improve the gate oxide electric field, such as patent CN 114388621 A, which integrates a diode under the gate, extracts the holes under the gate, reduces the hole concentration under the gate, and reduces the probability of gate damage. However, due to the integration of the diode, the strong electric field generated at the beginning of the high-energy particle irradiation injection above the diode cannot be avoided, which will lead to avalanche breakdown caused by excessive local electric field, and cannot improve the irradiation capacity of the device well; patent CN 115117053 A reduces the electric field strength at the junction area of ​​the device N-drift region and the substrate during high-energy particle irradiation through the design of the device, but cannot reduce the electric field strength at the junction area of ​​the N-Plus region and the P-Well region, the junction area of ​​the P-Plus region and the P-Well region, and the junction area of ​​the P-Well region and the N-drift region. In addition, the improvement of this patent does not reduce the hole concentration under the gate, and the risk of gate breakdown remains unchanged.

[0004] The present invention adds a buffer layer with a gradient doping concentration to the N-drift region and substrate interface region, the N-Plus region and P-Well region interface region, the P-Plus region and P-Well region interface region, and the P-Well region and N-drift region interface region of the traditional planar MOSFET, thereby reducing the peak electric field of the four regions and reducing the probability of avalanche breakdown of the device at the interface when the device is irradiated with high-energy particles; the present invention changes the gate of the traditional planar MOSFET into a separated gate, and adds a P-type high-energy particle injection layer gradient buffer region and a P-type high-energy particle injection layer under the gate, and the additional region is connected to the source, so that the holes under the gate can be quickly extracted during the high-energy particle irradiation. In addition, due to the existence of the P-type high-energy particle injection layer gradient buffer region, the high-energy particle irradiation occurs at the P-type high-energy particle The sub-injection layer will not have an excessively high peak electric field, which reduces the probability of avalanche breakdown of the device; compared with the traditional MOSFET device, the present invention also provides a current guiding layer, which can guide the extra electrons and holes generated in the high-energy particle irradiation device to flow to the P-type high-energy particle injection layer, guide the current generated during the high-energy particle irradiation to flow out from the source, avoid the device failure caused by the parasitic triode of the MOSFET being turned on, and the current guiding layer can reduce the on-resistance of the device when it is turned on; the width of the first P-type isolation layer gradient buffer layer, the second P-type isolation layer gradient buffer layer, etc. included in the P-type isolation layer gradient buffer region of the present invention gradually decreases to form a trapezoidal shape, and combined with the effect of the current guiding layer, the current can flow along the junction of the P-type isolation layer gradient buffer region and the current guiding layer during the device conduction, thereby improving the utilization rate of the area below the P-Well. The setting of the P-type isolation layer can guide the current to flow to the P-type high-energy particle injection layer in the high-energy particle irradiation device, allowing the holes to be quickly extracted from the device to prevent the accumulation of holes under the gate. Summary of the invention

[0005] The purpose of the present invention is to provide a planar gate MOSFET device structure with improved irradiation capability and a method for manufacturing the same, wherein the provided substrate gradient buffer region can reduce the peak electric field caused by high-energy particles injected from any region of the device during irradiation, thereby reducing the probability of the device losing control during irradiation by high-energy particles.

[0006] The technical solution adopted by the present invention is as follows: A planar gate MOSFET device structure with improved radiation capability comprises a metal drain, a substrate, a substrate gradient buffer region, an N-epitaxial layer and a current guiding layer stacked in sequence from bottom to top; a P-type isolation layer gradient buffer region, a P-type isolation layer and a P-Well region are stacked in sequence from bottom to top on both sides of the current guiding layer; a P-Plus region gradient buffer region and a P-Plus region are stacked in sequence from bottom to top in the P-Well regions on both sides; and an N-Plus region gradient buffer region and an N-Plus region are stacked in sequence from bottom to top in parallel; a P-type high-energy particle injection layer gradient buffer region and a P-type high-energy particle injection layer are stacked in sequence from bottom to top in the middle of the current guiding layer; a metal source electrode covers the top layer and contacts the P-Plus region, the N-Plus region and the P-type high-energy particle injection layer; and a polysilicon gate electrode is coated with a gate oxide layer and arranged in the metal source electrode and connected to the N-Plus region and the P-type high-energy particle injection layer.

[0007] Furthermore, the number of layers of the substrate, the P-type isolation layer gradient buffer region, and the P-Plus region gradient buffer region are all arbitrary natural numbers and at least one of the three is not 0; the number of layers of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region are equal.

[0008] Furthermore, when there are multiple layers: The N-type doping concentration of the first substrate gradient buffer layer, the second substrate gradient buffer layer, ... the nth substrate gradient buffer layer arranged sequentially from top to bottom in the substrate gradient buffer region increases sequentially; The P-type doping concentration of the first P-type isolation layer gradient buffer layer, the second P-type isolation layer gradient buffer layer, ... the nth P-type isolation layer gradient buffer layer arranged sequentially from top to bottom in the P-type isolation layer gradient buffer region decreases sequentially; The P-Plus region gradient buffer region includes a first P-Plus region gradient buffer layer, a second P-Plus region gradient buffer layer, ... an nth P-Plus region gradient buffer layer which are sequentially arranged from top to bottom, and the P-type doping concentration of the layer decreases sequentially; The N-Plus region gradient buffer region includes a first N-Plus region gradient buffer layer, a second N-Plus region gradient buffer layer, ... an nth N-Plus region gradient buffer layer which are sequentially arranged from top to bottom, and the N-type doping concentration of the layer decreases sequentially; The P-type high energy particle injection layer gradient buffer area includes a first P-type high energy particle injection layer gradient buffer layer, a second P-type high energy particle injection layer gradient buffer layer...an nth P-type high energy particle injection layer gradient buffer layer which are arranged from top to bottom in sequence, and the P-type doping concentration decreases in sequence.

[0009] Furthermore, the widths of the first P-type isolation layer gradient buffer layer, the second P-type isolation layer gradient buffer layer ... the nth P-type isolation layer gradient buffer layer) included in the P-type isolation layer gradient buffer region gradually decrease from top to bottom.

[0010] Furthermore, the doping concentration of the current guiding layer is N-type doping higher than the doping concentration of the N-epitaxial layer, and the current guiding layer wraps the P-type isolation layer gradient buffer region, the P-type isolation layer, the P-Well region, the P-type high-energy particle injection layer and the P-type high-energy particle injection layer gradient buffer region.

[0011] Furthermore, the P-Plus region, the N-Plus region, and the P-type high-energy particle injection layer are all arranged corresponding to the top position of the current guiding layer, and the outer edges of the P-Plus region and the P-Well region are aligned.

[0012] Furthermore, the P-Plus region, N-Plus region, and P-type high-energy particle injection layer have equal thickness and corresponding positions; the thickness of each layer of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region is equal and corresponding positions.

[0013] Furthermore, the P-type isolation layer guides the current to flow to the P-type high-energy particle injection layer when the high-energy particle irradiation device is in operation, so that holes are quickly extracted from the device, thereby preventing holes from accumulating under the gate.

[0014] A method for manufacturing a planar gate MOSFET device structure with improved radiation capability, which is applicable to the above-mentioned planar gate MOSFET device structure, comprises the following steps: Step 1: preparing a substrate region of a power semiconductor device; Step 2: performing the first epitaxy on the prepared substrate, and performing multiple ion implantations to form a substrate gradient buffer region; Step 3: Perform a second epitaxy on the basis of the first epitaxy to form an N-epitaxial layer, and perform multiple injections in parallel to form a current guiding layer, a P-type isolation layer gradient buffer region, a P-type isolation layer, a P-Well region, a P-Plus region gradient buffer region, an N-Plus region gradient buffer region, a P-type high-energy particle injection layer gradient buffer region, a P-Plus region, an N-Plus region, and a P-type high-energy particle injection layer; Step 4: forming a gate oxide layer by thermal oxidation technology, and forming a polysilicon gate by depositing polysilicon; Step 5: Form a metal drain and a metal source through a metal process to form a planar gate MOSFET device with improved radiation capability.

[0015] Furthermore, in step 3, if the depth of the ions actually to be implanted is too deep, multiple epitaxy and implantation steps are performed to form the target region.

[0016] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. The substrate gradient buffer region can reduce the peak electric field caused by high-energy particles injected from any region of the device during irradiation, thereby reducing the probability of device runaway during irradiation by high-energy particles.

[0017] 2. The set P-type isolation layer gradient buffer area can reduce the peak electric field caused by high-energy particles injected from the device above the P-Plus area, above the N-Plus area and above part of the gate area during irradiation, thereby reducing the probability of device loss of control during irradiation by high-energy particles.

[0018] 3. The P-Plus region gradient buffer area can reduce the peak electric field caused by high-energy particles injected into the P-Plus region of the device during irradiation, thereby reducing the probability of device loss of control during irradiation of high-energy particles.

[0019] 4. The N-Plus region gradient buffer region can reduce the peak electric field caused by high-energy particles injected into the N-Plus region of the device during irradiation, thereby reducing the probability of device loss of control during irradiation of high-energy particles.

[0020] 5. The gradient buffer area of ​​the P-type high-energy particle injection layer can reduce the peak electric field caused by high-energy particles injected into the P-type high-energy particle injection layer during irradiation of the device, thereby reducing the probability of device loss of control during irradiation of high-energy particles.

[0021] 6. Setting a P-type high-energy particle injection layer can extract the holes existing under the gate during high-energy particle irradiation, prevent gate damage, and reduce the probability of device loss of control during high-energy particle irradiation.

[0022] 7. The setting of the P-type isolation layer can guide the current to flow to the P-type high-energy particle injection layer in the high-energy particle irradiation device, so that the holes can be quickly extracted from the device and prevent the accumulation of holes under the gate.

[0023] 8. The gradient buffer region of the P-type isolation layer is set to a trapezoidal shape, which can guide the current to flow along the junction of the gradient buffer region of the P-type isolation layer and the current buffer layer, thereby improving the utilization rate of the area below the P-Well. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative work, among which: Figure 1 The invention relates to a planar gate MOSFET device structure with improved radiation capability.

[0025] Figure 2 A planar gate MOSFET device structure with improved radiation capability having a buffer layer for each buffer region.

[0026] Figure 3 A planar gate MOSFET device structure with improved radiation capability having three buffer layers in each buffer region.

[0027] Figure 4 Schematic diagram of step 1 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0028] Figure 5 Schematic diagram of step 2 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0029] Figure 6 The present invention is a schematic diagram of forming an N-epitaxial layer in step 3 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0030] Figure 7 Schematic diagram of step 3 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0031] Figure 8 Schematic diagram of step 4 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0032] Fig. 9 Schematic diagram of step 5 of a method for preparing a planar gate MOSFET device structure with improved radiation capability.

[0033] Fig.10 It is a traditional planar gate MOSFET structure.

[0034] Fig.11 It is a comparison chart of simulation results of the traditional structural device and the structural device proposed in the present invention.

[0035] The marks in the figure are: metal drain 1, substrate 2; A first substrate gradient buffer layer 2-1, a second substrate gradient buffer layer 2-2, a third substrate gradient buffer layer 2-3, and an nth substrate gradient buffer layer 2-n; N-epitaxial layer 3, current guiding layer 4; A first P-type isolation layer gradient buffer layer 5-1, a second P-type isolation layer gradient buffer layer 5-2, a third P-type isolation layer gradient buffer layer 5-3, and an nth P-type isolation layer gradient buffer layer 5-n; P-type isolation layer 5, P-Well region 6; A first P-Plus region gradient buffer layer 7-1, a second P-Plus region gradient buffer layer 7-2, a third P-Plus region gradient buffer layer 7-3, and an nth P-Plus region gradient buffer layer 7-n; A first N-Plus region gradient buffer layer 8-1, a second N-Plus region gradient buffer layer 8-2, a third N-Plus region gradient buffer layer 8-3, and an nth N-Plus region gradient buffer layer 8-n; The first P-type high energy particle injection layer gradient buffer layer 9-1, the second P-type high energy particle injection layer gradient buffer layer 9-2, the third P-type high energy particle injection layer gradient buffer layer 9-3, and the nth P-type high energy particle injection layer gradient buffer layer 9-n; P-Plus region 7 , N-Plus region 8 , P-type high-energy particle injection layer 9 , metal source 10 , gate oxide layer 11 , and polysilicon gate 12 . DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0038] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0039] The features and performance of the present invention are further described in detail below in conjunction with the embodiments.

[0040] Embodiment 1: A preferred embodiment of the present invention provides a conventional device structure such as Fig.10 As shown, in the simulation, a single high-energy particle is injected into the traditional structure device and the structure device proposed in this patent. The simulation results are as follows Fig.11 As mentioned above, the traditional device structure fails to shut down due to the opening of the parasitic transistor, while the structure device proposed in this patent successfully shuts down after a short current appears, injecting a single high-energy particle to induce the extra electrons and holes generated to exclude the device. This verifies that the structure proposed in this patent has a higher irradiation capacity. Figure 1 , Figure 2 Embodiment 1 proposes a planar gate MOSFET device structure with improved radiation capability, which is a cellular structure including a basic structure. The cellular structure of the MOSFET device is a metal drain 1, a substrate 2, a substrate gradient buffer region, an N-epitaxial layer 3, and a current guiding layer 4 stacked in sequence from bottom to top. On both sides of the current guiding layer 4, a P-type isolation layer gradient buffer region, a P-type isolation layer 5, and a P-Well region 6 are stacked in sequence from bottom to top. In the P-Well regions 6 on both sides, a P-Plus region gradient buffer region, A P-Plus region 7 and a parallel N-Plus region gradient buffer region and an N-Plus region 8 are stacked in sequence from bottom to top; a P-type high-energy particle injection layer gradient buffer region and a P-type high-energy particle injection layer 9 are stacked in sequence from bottom to top in the middle of the current guiding layer 4; a metal source 10 covers the top layer and contacts the P-Plus region 7, the N-Plus region 8, and the P-type high-energy particle injection layer 9; a polysilicon gate 12 is coated with a gate oxide layer 11 and then disposed in the metal source 10 and connected to the N-Plus region 8 and the P-type high-energy particle injection layer 9.

[0041] For the substrate gradient buffer region, the P-type isolation layer gradient buffer region, the P-Plus region gradient buffer region, the N-Plus region gradient buffer region and the P-type high energy particle injection layer gradient buffer region, Figure 2 as shown in .

[0042] Furthermore, the substrate gradient buffer region, the P-type isolation layer gradient buffer region, the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region can have any number of buffer layers according to actual needs. In this embodiment, the number of buffer layers is set to 1. The number of layers of the substrate 2, the P-type isolation layer gradient buffer region, and the P-Plus region gradient buffer region are all any natural numbers and at least one of the three is not 0; the number of layers of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region are equal. Different buffer regions of the same device can have different numbers of buffer layers.

[0043] Embodiment 2:

[0044] A planar gate MOSFET device structure with improved radiation capability comprises a metal drain 1, a substrate 2, a substrate gradient buffer region, an N-epitaxial layer 3, and a current guiding layer 4 which are stacked in sequence from bottom to top; a P-type isolation layer gradient buffer region, a P-type isolation layer 5, and a P-Well region 6 are stacked in sequence from bottom to top on both sides of the current guiding layer 4; a P-Plus region gradient buffer region and a P-Plus region 7 are stacked in sequence from bottom to top in the P-Well regions 6 on both sides; and an N-Plus region gradient buffer region and an N-Plus region 8 are stacked in sequence from bottom to top in parallel; a P-type high-energy particle injection layer gradient buffer region and a P-type high-energy particle injection layer 9 are stacked in sequence from bottom to top in the middle of the current guiding layer 4; a metal source 10 covers the top layer and contacts the P-Plus region 7, the N-Plus region 8, and the P-type high-energy particle injection layer 9; and a polysilicon gate 12 is disposed in the metal source 10 after covering a gate oxide layer 11 and connected to the N-Plus region 8 and the P-type high-energy particle injection layer 9.

[0045] like Figure 3As shown, in this example, a three-layer buffer structure is set, the substrate gradient buffer area includes a first substrate gradient buffer layer 2-1, a second substrate gradient buffer layer 2-2, a third substrate gradient buffer layer 2-3, etc.; the P-type isolation layer gradient buffer area includes a first P-type isolation layer gradient buffer layer 5-1, a second P-type isolation layer gradient buffer layer 5-2, a third P-type isolation layer gradient buffer layer 5-3, etc.; the P-Plus region gradient buffer area includes a first P-Plus region gradient buffer layer 7-1, a second P-Plus region gradient The substrate gradient buffer region, the P-type isolation layer gradient buffer region, the P-Plus region gradient buffer region, the N-Plus region gradient buffer region and the P-type high energy particle injection layer gradient buffer region are provided to allow the regions to share the peak electric field generated in the respective regions, thereby reducing the maximum peak electric field occurring during high energy particle irradiation and reducing the probability of avalanche breakdown.

[0046] In some examples of the present application, the N-type doping concentrations of the first substrate gradient buffer layer 2-1, the second substrate gradient buffer layer 2-2, the third substrate gradient buffer layer 2-3, etc. included in the substrate gradient buffer region increase in sequence; the P-type doping concentrations of the first P-type isolation layer gradient buffer layer 5-1, the second P-type isolation layer gradient buffer layer 5-2, the third P-type isolation layer gradient buffer layer 5-3, etc. included in the P-type isolation layer gradient buffer region decrease in sequence; the first P-Plus region gradient buffer layer 7-1, the second P-Plus region gradient buffer layer 7-2, The P-type doping concentration of the third P-Plus region gradient buffer layer 7-3 and the like decreases in sequence; the N-type doping concentration of the first N-Plus region gradient buffer layer 8-1, the second N-Plus region gradient buffer layer 8-2, the third N-Plus region gradient buffer layer 8-3 and the like included in the N-Plus region gradient buffer region decreases in sequence; the P-type high-energy particle injection layer gradient buffer layer 9-1, the second P-type high-energy particle injection layer gradient buffer layer 9-2, the third P-type high-energy particle injection layer gradient buffer layer 9-3 and the like decrease in sequence. The doping concentration of the substrate gradient buffer region, the P-type isolation layer gradient buffer region, the P-Plus region gradient buffer region, the N-Plus region gradient buffer region and the P-type high-energy particle injection layer gradient buffer region is set to change in a gradient in order to reduce the change in doping concentration between different regions and reduce the strong electric field caused by the electron and hole aggregation due to the base widening effect.

[0047] In some examples of the present application, the current guiding layer 4 can guide the extra current generated during high-energy particle irradiation to flow into the P-type high-energy particle injection layer and out from the source. The current guiding layer 4 can also reduce the on-resistance of the device.

[0048] In some examples of the present application, the gradient buffer region of the P-type isolation layer is set to a body shape, and combined with the current guiding layer 4, the current can be guided to flow along the junction of the gradient buffer region of the P-type isolation layer and the current guiding layer 4 when the device is turned on, thereby improving the utilization rate of the area below the P-Well area.

[0049] Embodiment 3:

[0050] Based on Example 2, the number of layers of the substrate 2, the P-type isolation layer gradient buffer region, and the P-Plus region gradient buffer region are all arbitrary natural numbers and at least one of the three is not 0; the number of layers of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region are equal.

[0051] When there are multiple layers: The N-type doping concentrations of the first substrate gradient buffer layer 2-1, the second substrate gradient buffer layer 2-2, ... the nth substrate gradient buffer layer 2-n arranged sequentially from top to bottom in the substrate gradient buffer region are increased sequentially; The P-type doping concentrations of the first P-type isolation layer gradient buffer layer 5-1, the second P-type isolation layer gradient buffer layer 5-2, and the nth P-type isolation layer gradient buffer layer 5-n arranged sequentially from top to bottom in the P-type isolation layer gradient buffer region are decreased sequentially; The P-type doping concentrations of the first P-Plus region gradient buffer layer 7-1, the second P-Plus region gradient buffer layer 7-2, ... the nth P-Plus region gradient buffer layer 7-n arranged sequentially from top to bottom in the P-Plus region gradient buffer region are decreased sequentially; The N-type doping concentrations of the first N-Plus region gradient buffer layer 8-1, the second N-Plus region gradient buffer layer 8-2, ... the nth N-Plus region gradient buffer layer 8-n arranged sequentially from top to bottom in the N-Plus region gradient buffer region are decreased sequentially; The P-type doping concentrations of the first P-type high energy particle injection layer gradient buffer layer 9-1, the second P-type high energy particle injection layer gradient buffer layer 9-2, ... the nth P-type high energy particle injection layer gradient buffer layer 9-n, which are arranged from top to bottom in the P-type high energy particle injection layer gradient buffer area, decrease in sequence.

[0052] Furthermore, the widths of the first P-type isolation layer gradient buffer layer 5-1, the second P-type isolation layer gradient buffer layer 5-2, ... the nth P-type isolation layer gradient buffer layer 5-n included in the P-type isolation layer gradient buffer region gradually decrease from top to bottom.

[0053] The doping concentration of the current guiding layer 4 is N-type doping higher than the doping concentration of the N-epitaxial layer 3, and the current guiding layer 4 wraps the P-type isolation layer gradient buffer area, the P-type isolation layer 5, the P-Well area 6, the P-type high-energy particle injection layer 9 and the P-type high-energy particle injection layer gradient buffer area.

[0054] The P-Plus region 7 , the N-Plus region 8 , and the P-type high-energy particle injection layer 9 are all arranged corresponding to the top position of the current guiding layer 4 , and the P-Plus region 7 is aligned with the outer edge of the P-Well region 6 .

[0055] The P-Plus region 7, the N-Plus region 8, and the P-type high-energy particle injection layer 9 have equal thickness and corresponding positions; the thickness of each layer of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region is equal and the positions remain corresponding.

[0056] The P-type isolation layer 5 guides the current to flow to the P-type high-energy particle injection layer 9 when the device is irradiated by high-energy particles, so that holes are quickly extracted from the device, thereby preventing holes from accumulating under the gate.

[0057] Embodiment 4: A specific method and steps for preparing a planar gate MOSFET device with improved radiation capability include: Step 1: Figure 4 As shown, a substrate region of a power semiconductor device is prepared; Step 2: If Figure 5 As shown, the first epitaxy is performed on the prepared substrate, and multiple ion implantations are performed to form a substrate gradient buffer region.

[0058] Step 3: If Figure 6 Figure 7 As shown, a second epitaxy is performed on the basis of the first epitaxy to form an N-epitaxial layer 3, and multiple injections are performed in parallel to form a current guiding layer 4, a P-type isolation layer gradient buffer region, a P-type isolation layer 5, a P-Well region 6, a P-Plus region gradient buffer region, an N-Plus region gradient buffer region, a P-type high-energy particle injection layer gradient buffer region, a P-Plus region 7, an N-Plus region 8, and a P-type high-energy particle injection layer 9. If the actual depth of the ions to be injected is too deep, multiple epitaxies and injections may be performed to form the regions; Step 4: Figure 8 As shown, a gate oxide layer is formed by using a thermal oxidation technique, and a polysilicon gate is formed by depositing polysilicon.

[0059] Step 5: Fig. 9 As shown, a metal drain 1 and a metal source 10 are formed by a metal process to form a planar gate MOSFET device with improved radiation capability.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions and improvements made by any technician familiar with the field within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A planar gate MOSFET device structure with improved radiation capability, characterized in that: The metal drain, substrate, substrate gradient buffer region, N-epitaxial layer and current guiding layer are stacked in sequence from bottom to top; the P-type isolation layer gradient buffer region, P-type isolation layer and P-Well region are stacked in sequence from bottom to top on both sides of the current guiding layer; the P-Plus region gradient buffer region and P-Plus region are stacked in sequence from bottom to top in the P-Well regions on both sides; the N-Plus region gradient buffer region and N-Plus region are stacked in sequence from bottom to top in parallel; the P-type high-energy particle injection layer gradient buffer region and P-type high-energy particle injection layer are stacked in sequence from bottom to top in the middle of the current guiding layer; the metal source covers the top layer and contacts with the P-Plus region, N-Plus region and P-type high-energy particle injection layer; the polysilicon gate is coated with a gate oxide layer and is arranged in the metal source and connected to the N-Plus region and the P-type high-energy particle injection layer.

2. A planar gate MOSFET device structure with improved radiation capability according to claim 1, characterized in that: The number of layers of the substrate, the P-type isolation layer gradient buffer region, and the P-Plus region gradient buffer region are all arbitrary natural numbers and at least one of the three is not 0; the number of layers of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region are equal.

3. A planar gate MOSFET device structure with improved radiation capability according to claim 2, characterized in that: When there are multiple layers: The N-type doping concentration of the first substrate gradient buffer layer, the second substrate gradient buffer layer, ... the nth substrate gradient buffer layer arranged sequentially from top to bottom in the substrate gradient buffer region increases sequentially; The P-type doping concentration of the first P-type isolation layer gradient buffer layer, the second P-type isolation layer gradient buffer layer, ... the nth P-type isolation layer gradient buffer layer arranged sequentially from top to bottom in the P-type isolation layer gradient buffer region decreases sequentially; The P-Plus region gradient buffer region includes a first P-Plus region gradient buffer layer, a second P-Plus region gradient buffer layer, ... an nth P-Plus region gradient buffer layer which are sequentially arranged from top to bottom, and the P-type doping concentration of the layer decreases sequentially; The N-Plus region gradient buffer region includes a first N-Plus region gradient buffer layer, a second N-Plus region gradient buffer layer, ... an nth N-Plus region gradient buffer layer which are sequentially arranged from top to bottom, and the N-type doping concentration of the layer decreases sequentially; The P-type high energy particle injection layer gradient buffer area includes a first P-type high energy particle injection layer gradient buffer layer, a second P-type high energy particle injection layer gradient buffer layer...an nth P-type high energy particle injection layer gradient buffer layer which are arranged from top to bottom in sequence, and the P-type doping concentration decreases in sequence.

4. A planar gate MOSFET device structure with improved radiation capability according to claim 3, characterized in that: The widths of the first P-type isolation layer gradient buffer layer, the second P-type isolation layer gradient buffer layer, ... the nth P-type isolation layer gradient buffer layer in the P-type isolation layer gradient buffer region gradually decrease from top to bottom.

5. A planar gate MOSFET device structure with improved radiation capability according to claim 1, characterized in that: The doping concentration of the current guiding layer is N-type doping higher than the doping concentration of the N-epitaxial layer, and the current guiding layer wraps the P-type isolation layer gradient buffer area, the P-type isolation layer, the P-Well area, the P-type high-energy particle injection layer and the P-type high-energy particle injection layer gradient buffer area.

6. A planar gate MOSFET device structure with improved radiation capability according to claim 1, characterized in that: The P-Plus region, the N-Plus region, and the P-type high-energy particle injection layer are all arranged corresponding to the top position of the current guiding layer, and the outer edge of the P-Plus region is aligned with the P-Well region.

7. A planar gate MOSFET device structure with improved radiation capability according to claim 6, characterized in that: The P-Plus region, N-Plus region, and P-type high-energy particle injection layer have equal thickness and corresponding positions; the thickness of each layer of the P-Plus region gradient buffer region, the N-Plus region gradient buffer region, and the P-type high-energy particle injection layer gradient buffer region is equal and corresponding positions.

8. A planar gate MOSFET device structure with improved radiation capability according to claim 1, characterized in that: The P-type isolation layer guides the current to flow to the P-type high-energy particle injection layer when the high-energy particle irradiation device is in operation, so that holes are quickly extracted from the device, thereby preventing holes from accumulating under the gate.

9. A method for manufacturing a planar gate MOSFET device structure with improved radiation capability, characterized in that: It is applicable to the planar gate MOSFET device structure according to any one of claims 1 to 8, and the steps include: Step 1: preparing a substrate region of a power semiconductor device; Step 2: performing the first epitaxy on the prepared substrate, and performing multiple ion implantations to form a substrate gradient buffer region; Step 3: Perform a second epitaxy on the basis of the first epitaxy to form an N-epitaxial layer 3, and perform multiple injections in parallel to form a current guiding layer, a P-type isolation layer gradient buffer region, a P-type isolation layer, a P-Well region, a P-Plus region gradient buffer region, an N-Plus region gradient buffer region, a P-type high-energy particle injection layer gradient buffer region, a P-Plus region, an N-Plus region, and a P-type high-energy particle injection layer; Step 4: forming a gate oxide layer by thermal oxidation technology, and forming a polysilicon gate by depositing polysilicon; Step 5: Form a metal drain and a metal source through a metal process to form a planar gate MOSFET device with improved radiation capability.

10. The method for manufacturing a planar gate MOSFET device structure with improved radiation capability according to claim 9, characterized in that: In step 3, if the depth of the ions actually to be implanted is too deep, multiple epitaxy and implantation steps are performed to form the target region.

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