Control method of filter modulator module, integrated circuit chip and motor control system

Abstract

The embodiment of the invention provides a control method of a filter modulator module, an integrated circuit chip and a motor control system. Relates to the technical field of integrated circuits. The method comprises the following steps: for each path of pulse width modulation module in multiple paths of pulse width modulation modules, if it is determined that a current count value of the pulse width modulation module meets a preset synchronization triggering condition in a counting process, triggering a synchronization event, and generating a synchronization signal corresponding to the synchronization event. And after the synchronous signal is generated, if it is determined that the current count value meets a preset interruption triggering condition at the current moment in the counting process, interruption is executed at the current moment, and the current value of the motor is collected at the current moment. The method is used for achieving the effect of improving the accuracy and the responsivity of the filtering modulator.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to a control method for a filter modulator module, an integrated circuit chip, and a motor control system. Background Art

[0002] Currently, the SDFM module, namely the Sigma-Delta filter modulator, is an advanced digital filtering device designed for motor control systems and has four independent input channels. In motor control applications, these input channels are usually used for current measurement and resolver position decoding. Each input channel can independently receive the bit stream from the Sigma Delta modulator, which can be regarded as digital quantity sampling. SDFM is generally used for three-phase current sampling. Due to the particularity of the scenario, the three-phase current sampling has requirements for synchronization, and at the same time, the real-time requirement for current sampling is very high. However, due to the Sigma-Delta sampling principle, it is determined that there are errors in the first two sampling data obtained by the SDFM after the synchronization signal is triggered. Therefore, in order to collect correct data, T1 (i.e., the time between the trigger synchronization event and the interruption time) must be greater than three sampling periods of the SDFM.

[0003] In the prior art, usually one PWM module is designed to count up, and two events are designed at the same time. For the first event, an interrupt handler is triggered. After entering the interrupt, the current sampling data is obtained immediately after the interrupt starts. For the second event, it is used to trigger the synchronization event and generate a synchronization start signal for current sampling.

[0004] However, in the prior art, the sampling period of each SDFM is generally very long. With the further improvement of future chip function requirements, the oversampling rate will be higher in the future, and there will be more bit positions for each conversion. However, the T1 time must be limited by the PWM period, which makes the T1 time longer, resulting in too long processing time of the SDFM, and thus it is impossible to obtain correct data in time and ensure the accuracy and responsiveness of the calculation. Summary of the Invention

[0005] Embodiments of this application provide a control method for a filter modulator module, an integrated circuit chip, and a motor control system, so as to achieve the effect of improving the accuracy and responsiveness of the filter modulator.

[0006] In a first aspect, embodiments of this application provide a control method for a filter modulator module. The filter modulator module is provided with multiple pulse width modulation modules. The method includes:

[0007] For each pulse width modulation module in the multi-channel pulse width modulation module, if it is determined during the counting process that the current count value of the pulse width modulation module meets a preset synchronization trigger condition, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated;

[0008] After generating the synchronization signal, if it is determined during the counting process that the current count value meets a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value of the motor is collected at the current moment.

[0009] In a possible implementation manner, for the synchronization event and the interrupt event corresponding to each pulse width modulation module, the time difference between the moment when the synchronization event occurs and the moment when the interrupt event occurs is greater than a preset duration; wherein, the preset duration is 3 times the preset period.

[0010] In a possible implementation manner, the filter modulator module is provided with a first pulse width modulation module and a second pulse width modulation module; the moments at which the two pulse width modulation modules execute interrupts are adjustable;

[0011] The interrupt frequency of executing the interrupt is determined according to the time difference between the moment when the interrupt event of the first pulse width modulation module occurs and the moment when the interrupt event of the second pulse width modulation module occurs.

[0012] In a possible implementation manner, each pulse width modulation module is provided with a first comparison register and a second comparison register.

[0013] In a possible implementation manner, for each pulse width modulation module in the multi-channel pulse width modulation module, if it is determined during the counting process that the current synchronization event of the pulse width modulation module meets a preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated, including:

[0014] For each pulse width modulation module in the multi-channel pulse width modulation module, if it is determined during the counting process that the current synchronization event of the pulse width modulation module meets a preset synchronization trigger condition based on the first comparison register, a synchronization signal corresponding to the synchronization event is generated.

[0015] In a possible implementation manner, after generating the synchronization signal, if it is determined during the counting process that the current interrupt event meets a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value is collected at the current moment, including:

[0016] After generating the synchronization signal, if during the counting process, it is determined based on the second comparison register that the current interruption event satisfies a preset interruption triggering condition at the current moment, then an interruption is executed at the current moment, and a current value is collected at the current moment.

[0017] In a possible implementation manner, the preset synchronization triggering condition is a preset synchronization count value; the preset interruption triggering condition is a preset interruption count value.

[0018] In a possible implementation manner, each pulse width modulation module corresponds to a timer; the counting method and frequency of the pulse width modulation modules are the same.

[0019] In a second aspect, an integrated circuit chip provided by an embodiment of the present application includes a filter modulator chip, the filter modulator chip is provided with a filter modulator module, and the filter modulator module is provided with multiple pulse width modulation modules; wherein, the filter modulator module is the filter modulator module as described in the first aspect.

[0020] In a third aspect, an embodiment of the present application provides a motor control system, the motor control system includes an integrated circuit chip and a motor, and the integrated circuit chip is the integrated circuit chip as described in the second aspect.

[0021] In a fourth aspect, an embodiment of the present application provides a control device for a filter modulator module, the filter modulator module is provided with multiple pulse width modulation modules; including:

[0022] A first triggering module, configured to, for each pulse width modulation module in the multiple pulse width modulation modules, if during the counting process, it is determined that the current count value of the pulse width modulation module satisfies a preset synchronization triggering condition, then trigger a synchronization event and generate a synchronization signal corresponding to the synchronization event;

[0023] A second triggering module, configured to, after generating the synchronization signal, if during the counting process, it is determined that the current count value satisfies a preset interruption triggering condition at the current moment, then execute an interruption at the current moment, and collect the current value of the motor at the current moment.

[0024] In a possible implementation manner, for the synchronization event and the interruption event corresponding to each pulse width modulation module, the time difference between the moment when the synchronization event occurs and the moment when the interruption event occurs is greater than a preset duration; wherein, the preset duration is 3 times the preset period.

[0025] In a possible implementation, the filter modulator module is provided with a first pulse width modulation module and a second pulse width modulation module; the moments at which the two pulse width modulation modules execute interrupts are adjustable;

[0026] The interrupt frequency of the executed interrupt is determined according to the time difference between the moment when the interrupt event of the first pulse width modulation module occurs and the moment when the interrupt event of the second pulse width modulation module occurs.

[0027] In a possible implementation, each of the pulse width modulation modules is provided with a first comparison register and a second comparison register.

[0028] In a possible implementation, the first trigger module is specifically configured to:

[0029] For each pulse width modulation module among the multiple pulse width modulation modules, if during the counting process, it is determined based on the first comparison register that the current synchronization event of the pulse width modulation module meets a preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated.

[0030] In a possible implementation, the second trigger module is specifically configured to:

[0031] After the synchronization signal is generated, if during the counting process, it is determined based on the second comparison register that the current interrupt event meets a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and a current value is collected at the current moment.

[0032] In a possible implementation, the preset synchronization trigger condition is a preset synchronization count value; the preset interrupt trigger condition is a preset interrupt count value.

[0033] In a possible implementation, each of the pulse width modulation modules corresponds to a timer; the counting method and frequency of the pulse width modulation modules are the same.

[0034] In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor;

[0035] The memory stores computer execution instructions;

[0036] The processor executes the computer execution instructions stored in the memory, so that the processor executes the above first aspect and / or various possible implementations of the first aspect.

[0037] Sixth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the first aspect and / or various possible implementation manners of the first aspect as described above.

[0038] Seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the first aspect and / or various possible implementation manners of the first aspect as described above.

[0039] For the control method of the filter modulator module, the integrated circuit chip and the motor control system provided by the embodiments of the present application, for each pulse width modulation module in the multi-channel pulse width modulation module, if it is determined during the counting process that the current count value of the pulse width modulation module satisfies a preset synchronization trigger condition, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated. After the synchronization signal is generated, if it is determined during the counting process that the current count value satisfies a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value of the motor is collected at the current moment. In this solution, the synchronous trigger of the multi-channel PWM module participating in the SDFM sampling is used to improve the time difference between the synchronous start time and the current acquisition time, ensure that on the basis of accurate signal sampling, the range of the T1 value is expanded, and incorrect data is better avoided, so as to achieve the effect of improving the accuracy and responsiveness of the filter modulator. Description of the Drawings

[0040] The drawings here are incorporated into the description and form a part of this description, showing embodiments consistent with the present application, and are used together with the description to explain the principles of the present application.

[0041] Figure 1 Schematic flowchart of a control method for a filter modulator module provided by an embodiment of the present application Figure 1 ;

[0042] Figure 2 Schematic scenario of a control method for a filter modulator module provided by an embodiment of the present application Figure 1 ;

[0043] Figure 3 Schematic flowchart of another control method for a filter modulator module provided by an embodiment of the present application Figure 2 ;

[0044] Figure 4 Schematic scenario of a control method for a filter modulator module provided by an embodiment of the present application Figure 2 ;

[0045] Figure 5Schematic diagram of a control device for a filter modulator module provided by an embodiment of the present application;

[0046] Figure 6 Schematic diagram of an electronic device provided by an embodiment of the present application.

[0047] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and more detailed descriptions will be provided hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0048] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0049] Technical term explanation:

[0050] SDFM: Σ-Δ Filter Modulator, abbreviated as SDFM, is a filter that converts analog signals into digital signals through modulation technology and is commonly used for high-precision analog-to-digital conversion.

[0051] OSR: Oversampling Ratio, abbreviated as OSR, refers to the multiple of the sampling frequency relative to the signal bandwidth in digital signal processing and is usually used to improve the accuracy of the signal and reduce noise.

[0052] PWM: Pulse Width Modulation, is a technology that controls power output by changing the width of pulse signals and is widely used in fields such as motor control, dimming, and audio modulation.

[0053] Currently, the SDFM module, namely the Sigma-Delta filter modulator, is an advanced digital filtering device designed for motor control systems and has four independent input channels. In motor control applications, these input channels are typically used for current measurement and resolver position decoding. Each input channel can independently receive the bit stream from the Sigma Delta modulator, which can be regarded as digital quantity sampling. SDFM is generally used for three-phase current sampling. Due to the particularity of the scenario, there are synchronization requirements for each phase current sampling, and at the same time, there are very high real-time requirements for current sampling. However, due to the Sigma-Delta sampling principle, it is determined that there are errors in the first two sampling data obtained by the SDFM after the synchronization signal is triggered. Therefore, in order to collect correct data, T1 (i.e., the time between triggering the synchronization event and the interruption time) must be greater than three sampling periods of the SDFM.

[0054] In an example, usually one PWM module is designed to count up, and at the same time two events are designed. The first event triggers the interrupt handler. After entering the interrupt, the current sampling data is obtained immediately after the interrupt starts. The second event is used to trigger the synchronization event and generate a synchronization start signal for current sampling. However, in the prior art, the sampling period of each SDFM is generally very long. With the further improvement of future chip function requirements, the oversampling rate will be higher in the future, and there will be more bit positions for each conversion. However, the T1 time must be limited by the PWM period, which makes the T1 time longer, resulting in too long processing time of the SDFM, and then it is impossible to obtain correct data in time, and the accuracy and responsiveness of the calculation cannot be guaranteed.

[0055] Specifically, the three key parameters of the SDFM are: the module clock CLK, the oversampling rate OSR, and the offset address SH. CLK determines the calculation speed of the module. The oversampling rate OSR determines how many bit positions are required for one current calculation. The higher the OSR, the higher the data accuracy (the resolution is improved). For example, at a 20M clock, OSR = 250, then the time required for a complete Sigma-Delta sampling is 12.5 us. However, at the same time, the increase in OSR will extend the filter response time and affect the processing rate.

[0056] First possibility: If the future OSR is larger, it is very likely that the condition that T1 is greater than 3 sampling periods will not be met. (Assuming an interrupt of 16K, that is, a period of 62.5 us, only 3 - 4 sampling period lengths can be limited (the single sampling period calculated by OSR = 250 and CLK = 20M is 12.5 us). If OSR further increases, the single sampling period also increases), which will further cause the T1 time to become longer. Second possibility: When the PWM frequency is increased, the direct impact is that the overall PWM period becomes smaller, which directly causes T1 not to meet the condition of being greater than 3 sampling periods, resulting in the inavailability of SDFM sampling. Due to the limitations of these two future trends, the current SDFM configuration is very restricted and cannot exert its true performance.

[0057] Combining the above scenarios, it can be seen that in the prior art, there are technical problems of low accuracy and responsiveness of the filter modulator.

[0058] The control method of the filter modulator module provided by this application solves the technical problems of low accuracy and responsiveness of the filter modulator by setting multiple PWM modules to participate in the synchronous trigger of SDFM sampling and improving the time difference from the synchronous start time to the current acquisition time.

[0059] The technical solution of this application and how this technical solution solves the above technical problems will be described in detail below with specific embodiments. These specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this application will be described below in conjunction with the drawings.

[0060] Figure 1 Flow schematic of a control method for a filter modulator module provided by this application Figure 1 , the filter modulator module is provided with multiple pulse width modulation modules; as Figure 1 shown, the method includes:

[0061] S101. For each pulse width modulation module in the multiple pulse width modulation modules, if it is determined during the counting process that the current count value of the pulse width modulation module meets the preset synchronous trigger condition, then trigger a synchronous event and generate a synchronous signal corresponding to the synchronous event.

[0062] Exemplarily, the execution subject of this embodiment can be an electronic device, or a terminal device, or a control device or equipment of the filter modulator module, or other devices or equipment that can execute this embodiment, and this is not limited. In this embodiment, the execution subject is introduced as an electronic device.

[0063] First, for the motor, a three-phase motor is preferably selected, and current sampling is performed on the motor control. Taking a three-phase motor as an example, the three-phase motor includes a filter modulation module (SDFM module), and the filter modulation module is provided with multiple pulse width modulation modules (i.e., PWM modules). The connection relationship between the multiple PWM modules can be parallel. Among them, each PWM module is provided with a timer for counting up (or down), and the count value is used to trigger an interrupt / synchronization event; each PWM module corresponds to two comparison registers, namely the first timer CMPA and the second timer CMPB. The second timer CMPB is used to trigger the synchronization event of SOCA or SOCB of the PWM module and can be used as the synchronization start signal for current sampling; the first timer CMPA is used to trigger an interrupt response, and current sampling starts immediately when the interrupt starts. Moreover, the counting method and frequency of each PWM module are the same.

[0064] In this step, the preset synchronization trigger condition is the preset synchronization count value. For each PWM module in the multiple pulse width modulation modules, counting starts simultaneously during application, and the count value is compared with the preset synchronization count value in real time. If it is determined that the current count value of the pulse width modulation module satisfies the preset synchronization count value, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated.

[0065] For example, the filter modulation module is provided with 2 PWM modules or 3 PWM modules, and there is no limitation on this. Taking 3 PWM modules as an example, Figure 2 is a schematic scenario of a control method for a filter modulation module provided by an embodiment of the present application Figure 1 , such as Figure 2 shown, including: 3 PWM modules. The SDFM module (SINCx) only receives one PWM at a time. Press Figure 2 shown for parallel design to implement multiple PWMs. Therefore, by setting 3 PWM modules, higher-frequency interrupt applications can be achieved, and SDFM can also be used for sampling.

[0066] S102. After generating the synchronization signal, if during the counting process, it is determined that the current count value satisfies the preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value of the motor is collected at the current moment.

[0067] Exemplarily, the preset interrupt trigger condition is the preset interrupt count value. After generating the synchronization signal, continue counting, and compare the count value with the preset interrupt count value in real time. If it is determined that the current count value satisfies the preset interrupt count value at the current moment, an interrupt event is triggered at the current moment, an interrupt is executed, and the current value of the motor is collected at the current moment.

[0068] The control method for the filter modulator module provided by the embodiments of the present application is as follows. For each pulse width modulation module in the multi-channel pulse width modulation module, if during the counting process, it is determined that the current count value of the pulse width modulation module meets the preset synchronization trigger condition, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated. After generating the synchronization signal, if during the counting process, it is determined that the current count value meets the preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value of the motor is collected at the current moment. In this solution, the synchronization trigger of the multi-channel PWM module participating in SDFM sampling is utilized to increase the time difference between the synchronization start time and the current acquisition time, ensuring that on the basis of accurate signal sampling, the range of T1 values is expanded, and incorrect data is better avoided, so as to achieve the effect of improving the accuracy and responsiveness of the filter modulator.

[0069] Figure 3 Schematic flow of a control method for a filter modulator module provided by the present application Figure 2 , as Figure 3 shown, based on the Figure 1 embodiment, the control method for the filter modulator module is described in detail. The method includes:

[0070] S201. For each pulse width modulation module in the multi-channel pulse width modulation module, if during the counting process, it is determined based on the first comparison register that the current synchronization event of the pulse width modulation module meets the preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated.

[0071] In one example, for the synchronization event and interrupt event corresponding to each pulse width modulation module, the time difference between the moment when the synchronization event occurs and the moment when the interrupt event occurs is greater than the preset duration; where the preset duration is 3 times the preset period.

[0072] In one example, the filter modulator module is provided with a first pulse width modulation module and a second pulse width modulation module; the moments when the two pulse width modulation modules execute interrupts are adjustable; the interrupt frequency of the execution of the interrupt is determined according to the time difference between the moment when the interrupt event of the first pulse width modulation module occurs and the moment when the interrupt event of the second pulse width modulation module occurs.

[0073] In one example, each pulse width modulation module is provided with a first comparison register and a second comparison register.

[0074] In one example, the preset synchronization trigger condition is a preset synchronization count value.

[0075] In one example, each pulse width modulation module corresponds to a timer; the counting method and frequency of the pulse width modulation modules are the same.

[0076] Exemplarily, each PWM module is provided with a timer for counting up (or down), and the count value is used to trigger an interrupt / synchronization event; each PWM module corresponds to two comparison registers, namely the first timer CMPA and the second timer CMPB. The second timer CMPB is used to trigger the synchronization event of SOCA or SOCB of the PWM module and can be used as the synchronization start signal for current sampling; the first timer CMPA is used to trigger an interrupt response, and current sampling starts immediately when the interrupt starts. Moreover, the counting method and frequency of each PWM module are the same.

[0077] In this step, the preset synchronization trigger condition is the preset synchronization count value. For each PWM module in the multiple pulse width modulation modules, counting starts simultaneously during application, and the count value is compared with the preset synchronization count value in real time through the first comparison register. If it is determined that the current count value of the pulse width modulation module meets the preset synchronization count value, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated.

[0078] For example, Figure 4 is a schematic scenario of a control method for a filter modulator module provided by an embodiment of the present application Figure 2 , as Figure 4 shown, including: the filter modulator module is provided with 2 PWM modules, namely the first pulse width modulation module PWM1 and the second pulse width modulation module PWM2. The timer of PWM1 counts up, with a frequency of x. The preset interrupt event (CMPA1 event) is used to trigger an interrupt, and the preset synchronization event (CMPB1 event) is used to trigger the SOC synchronization signal. The timer of PWM2 counts up, with a frequency of x. The preset interrupt event (CMPA2 event) is used to trigger an interrupt, and the preset synchronization event (CMPB2 event) is used to trigger the SOC synchronization signal. Prd refers to the count value, and T1 refers to the time period from triggering the synchronization event to triggering the interrupt; the interrupt start time point when the interrupt is triggered is the current acquisition time point.

[0079] Further, taking two pulse width modulation modules as an example, the filter modulator module is respectively the first pulse width modulation module and the second pulse width modulation module. The time when the interruption occurs in each pulse width modulation module can be manually adjusted. Furthermore, the interruption frequency is determined according to the time difference between the time when the interruption event of the first pulse width modulation module occurs and the time when the interruption event of the second pulse width modulation module occurs. Preferably, by moving the values of the CMPA1 event and the CMPA2 event, the time difference between the time when the CMPA1 event occurs and the time when the CMPA2 event occurs can be made half of the preset counting period, that is, the interruption frequency can reach 2x. By analogy, if there are 3 PWM modules, the interruption frequency can reach 3x. Therefore, according to actual needs, multiple interruption trigger points can be set on different PWM lines respectively. By adjusting the time node distance between the CMPA1 event and the CMPA2 event, the overall interruption frequency can be flexibly designed.

[0080] Further, for the synchronization event and the interruption event corresponding to each pulse width modulation module, the time difference between the time when the synchronization event occurs and the time when the interruption event occurs is greater than a preset duration, and the preset duration is 3 times the preset period.

[0081] Therefore, the interruptions triggered by the CMPB1 event and the CMPA1 event correspond to current sampling; the interruptions triggered by the CMPB2 event and the CMPA2 event correspond to current sampling and do not interfere with each other. At this time, the T1 time is the duration from when the CMPB1 event is triggered until the interruption is triggered by the CMPA1 event, which ensures a substantial increase in the upper limit of the T1 time. Considering the development of future technologies, this application can be compatible with SDFM applications with higher OSR sampling rates (currently with an upper limit of 256 bits) in the future, and the OSR sampling rate is not limited.

[0082] S202. After generating the synchronization signal, if during the counting process, it is determined based on the second comparison register that the current interruption event meets the preset interruption trigger condition at the current moment, then an interruption is executed at the current moment, and the current value is collected at the current moment.

[0083] In one example, the preset interruption trigger condition is a preset interruption count value.

[0084] Exemplarily, the preset interruption trigger condition is a preset interruption count value. The electronic device can continue counting after generating the synchronization signal, and compare the count value with the preset interruption count value in real time through the second comparison register. If it is determined that the current count value meets the preset interruption count value at the current moment, then an interruption event is triggered and an interruption is executed at the current moment, and the current value of the motor is collected at the current moment.

[0085] The control method of the filter modulator module provided by the embodiment of the present application, for each pulse width modulation module in the multi-channel pulse width modulation module, if during the counting process, it is determined based on the first comparison register that the current synchronization event of the pulse width modulation module meets the preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated. After generating the synchronization signal, if during the counting process, it is determined based on the second comparison register that the current interruption event meets the preset interruption trigger condition at the current moment, an interruption is executed at the current moment, and the current value is collected at the current moment. In this solution, the synchronization trigger of the multi-channel PWM module participating in SDFM sampling is utilized to increase the time difference between the synchronization start time and the current acquisition time, ensure that on the basis of accurate signal sampling, the range of T1 values is expanded, and incorrect data is better avoided, so as to achieve the effect of improving the accuracy and responsiveness of the filter modulator.

[0086] Figure 5 The following is a schematic structural diagram of a control device for a filter modulator module provided by the present application. The filter modulator module is provided with a multi-channel pulse width modulation module; as Figure 5 shown, the control device 30 for the filter modulator module provided in this embodiment includes:

[0087] A first trigger module 31, configured to, for each pulse width modulation module in the multi-channel pulse width modulation module, if during the counting process, it is determined that the current count value of the pulse width modulation module meets the preset synchronization trigger condition, trigger a synchronization event and generate a synchronization signal corresponding to the synchronization event;

[0088] A second trigger module 32, configured to, after generating the synchronization signal, if during the counting process, it is determined that the current count value meets the preset interruption trigger condition at the current moment, execute an interruption at the current moment and collect the current value of the motor at the current moment.

[0089] In Figure 5 On the basis of the embodiment shown, the embodiment of the present application provides another control device for a filter modulator module, including: for the synchronization event and interruption event corresponding to each pulse width modulation module, the time difference between the moment when the synchronization event occurs and the moment when the interruption event occurs is greater than a preset duration; wherein, the preset duration is 3 times the preset period.

[0090] In a possible implementation manner, the filter modulator module is provided with a first pulse width modulation module and a second pulse width modulation module; the moments when the two pulse width modulation modules execute interruptions are adjustable; the interruption frequency of the execution of the interruption is determined according to the time difference between the moment when the interruption event of the first pulse width modulation module occurs and the moment when the interruption event of the second pulse width modulation module occurs.

[0091] In a possible implementation, each of the pulse width modulation modules is provided with a first comparison register and a second comparison register.

[0092] In a possible implementation, the first trigger module 31 is specifically configured to:

[0093] For each of the multiple pulse width modulation modules, if during the counting process, it is determined based on the first comparison register that the current synchronization event of the pulse width modulation module meets a preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated.

[0094] In a possible implementation, the second trigger module 32 is specifically configured to:

[0095] After the synchronization signal is generated, if during the counting process, it is determined based on the second comparison register that the current interrupt event meets a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and a current value is collected at the current moment.

[0096] In a possible implementation, the preset synchronization trigger condition is a preset synchronization count value; the preset interrupt trigger condition is a preset interrupt count value.

[0097] In a possible implementation, each of the pulse width modulation modules corresponds to a timer; the counting method and frequency of the pulse width modulation modules are the same.

[0098] The device provided in this embodiment can execute the method provided in the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0099] Exemplarily, the present application provides an integrated circuit chip, including a filter modulator chip. The filter modulator chip is provided with a filter modulator module, and the filter modulator module is provided with multiple pulse width modulation modules; wherein, the filter modulator module is the filter modulator module as pointed out in the above embodiments.

[0100] Exemplarily, the present application provides a motor control system. The motor control system includes an integrated circuit chip and a motor. The integrated circuit chip is the integrated circuit chip as pointed out in the above embodiments, and the integrated circuit chip is used to control the operation of the motor.

[0101] Figure 6 It is a schematic structural diagram of the electronic device provided by the present application. As Figure 6As shown in the figure, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. Among them, the processor 501, the memory 502, and the communication component 503 are connected through a bus 504.

[0102] In the specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above method.

[0103] For the specific implementation process of the processor 501, reference can be made to the above method embodiment. The implementation principle and technical effect are similar, and will not be elaborated here in this embodiment.

[0104] In the above embodiment, it should be understood that the processor may be a central processing unit (English: Central Processing Unit, abbreviated: CPU), or other general-purpose processors, digital signal processors (English: Digital Signal Processor, abbreviated: DSP), application-specific integrated circuits (English: Application Specific Integrated Circuit, abbreviated: ASIC), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the invention can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0105] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0106] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0107] This application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0108] The present application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0109] The above-readable storage medium may be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk. The readable storage medium may be any available medium accessible by a general-purpose or special-purpose computer.

[0110] An exemplary readable storage medium is coupled to the processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium may also be a component of the processor. The processor and the readable storage medium may be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium may also exist as discrete components in a device.

[0111] The division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other may be indirect couplings or communication connections through some interfaces, devices, or units, and may be in electrical, mechanical, or other forms.

[0112] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0113] In addition, in each embodiment of the present invention, the functional units may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0114] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, and other various media that can store program codes.

[0115] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When this program is executed, it executes the steps including the above method embodiments; and the aforementioned storage medium includes: ROMs, RAMs, magnetic disks, or optical discs, and other various media that can store program codes.

[0116] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other implementation manners of the present invention. The present invention is intended to cover any variations, uses, or adaptations of the present invention. These variations, uses, or adaptations follow the general principles of the present invention and include common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A control method for a filter modulator module, characterized in that: The filter modulator module is provided with a plurality of pulse width modulation modules; the method comprises: For each pulse width modulation module in the multiple pulse width modulation modules, if it is determined during the counting process that the current count value of the pulse width modulation module meets the preset synchronization trigger condition, a synchronization event is triggered, and a synchronization signal corresponding to the synchronization event is generated; After the synchronization signal is generated, if it is determined during the counting process that the current count value satisfies a preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value of the motor is collected at the current moment.

2. The method according to claim 1, characterized in that For the synchronization event and interruption event corresponding to each pulse width modulation module, the time difference between the time when the synchronization event occurs and the time when the interruption event occurs is greater than a preset duration; wherein the preset duration is 3 times of the preset period.

3. The method according to claim 1, characterized in that The filter modulator module is provided with a first pulse width modulation module and a second pulse width modulation module; the time when the two pulse width modulation modules execute interruption is adjustable; The interruption frequency of the execution interruption is determined according to the time difference between the time when the interruption event of the first pulse width modulation module occurs and the time when the interruption event of the second pulse width modulation module occurs.

4. The method according to claim 1, characterized in that: Each of the pulse width modulation modules is provided with a first comparison register and a second comparison register.

5. The method according to claim 4, characterized in that For each pulse width modulation module in the multiple pulse width modulation modules, if it is determined during the counting process that the current synchronization event of the pulse width modulation module meets the preset synchronization trigger condition, then a synchronization signal corresponding to the synchronization event is generated, including: For each pulse width modulation module in the multiple pulse width modulation modules, if during the counting process, it is determined based on the first comparison register that the current synchronization event of the pulse width modulation module meets the preset synchronization trigger condition, a synchronization signal corresponding to the synchronization event is generated.

6. The method according to claim 4, characterized in that After the synchronization signal is generated, if it is determined during the counting process that the current interrupt event satisfies the preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and a current value is collected at the current moment, including: After the synchronization signal is generated, if during the counting process, it is determined based on the second comparison register that the current interrupt event satisfies the preset interrupt trigger condition at the current moment, an interrupt is executed at the current moment, and the current value is collected at the current moment.

7. The method according to claim 1, characterized in that The preset synchronization trigger condition is a preset synchronization count value; the preset interruption trigger condition is a preset interruption count value.

8. The method according to any one of claims 1 to 7, characterized in that: Each pulse width modulation module corresponds to a timer; the counting method and frequency of the pulse width modulation modules are the same.

9. An integrated circuit chip, characterized in that: It includes a filter modulator chip, the filter modulator chip is provided with a filter modulator module, and the filter modulator module is provided with a multi-channel pulse width modulation module; Wherein, the filter modulator module is the filter modulator module as described in any one of claims 1-8.

10. A motor control system, characterized in that: The motor control system comprises an integrated circuit chip and a motor, and the integrated circuit chip is the integrated circuit chip as claimed in claim 9.

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