Method for identifying whether digital gate circuit can oscillate
By modeling the digital gate circuit as a directed graph and analyzing the strongly connected component SCC and a single loop, the problem of difficult to automatically detect the oscillation combination logic ring in the digital gate circuit is solved, and the ability to automatically identify and analyze the oscillation conditions is realized.
Patent Information
- Application Number
- CN202510204489.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-24
- Publication Date
- 2025-06-13
AI Technical Summary
The prior art is difficult to automatically detect and analyze the possible oscillating combination logic rings in digital gate circuits, resulting in increased circuit power consumption and functional errors.
By modeling the digital gate circuit as a directed graph, the strongly connected component SCC is analyzed, and a single loop is extracted and graded, and the combined relationship of the loop is analyzed to determine the oscillation situation.
It realizes the ability to automatically detect the oscillation combination logic ring in the digital gate circuit, finds the trigger conditions during oscillation, and provides the smallest path to disconnect the loop, helping designers identify and solve design problems.
Smart Images
Figure CN120145957A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic design automation technology, and in particular, to a method for identifying whether a digital gate circuit can oscillate. Background Art
[0002] A logic gate circuit is a unit circuit used to implement basic logical operations. Usually, logic gate circuits can be classified into several types according to logical functions, such as NOT gate, AND gate, OR gate, NOR gate, NAND gate, XOR gate, etc. According to the basic functions of these gate circuits, multiple gate circuits can be combined together according to certain rules to form a combinational logic circuit that can implement specific functions.
[0003] In a combinational logic circuit, if there is a logic combination unit that returns to the starting logic combination unit after passing through multiple logic gates, forming a closed-loop path, then we call this loop a combinational logic loop. Combinational logic loops are divided into two types: positive feedback and negative feedback. A positive feedback loop is a feedback that can maintain the current state of the combinational logic output signal unchanged, and is commonly found in circuits such as latches, registers, and SRAM memory cells. A negative feedback loop is a feedback that flips the current combinational logic output signal. A negative feedback loop will cause the output signal value to keep flipping, and is commonly found in circuits such as oscillators and pseudo-random number generators.
[0004] Combinational logic loops are common in basic gate circuit modules, but unexpected combinational logic loops may cause multiple driving or signal oscillation, resulting in increased circuit power consumption and functional errors. Currently, combinational logic loops are difficult to be analyzed and calculated by static timing analysis tools, and may even cause the simulator to enter an infinite loop. Therefore, an EDA tool is needed to automatically detect combinational logic loops that may oscillate in digital gate circuits, find the triggering conditions during oscillation, and provide the minimum path to break the loop, so as to help designers discover and solve design problems. Summary of the Invention
[0005] To solve the technical problems existing in the background art, the present invention proposes a method for identifying whether a digital gate circuit can oscillate.
[0006] The method for identifying whether a digital gate circuit can oscillate proposed by the present invention includes:
[0007] Obtain the digital gate circuit to be identified, and model the digital gate circuit as a directed graph;
[0008] Analyze all strongly connected components SCCs in the directed graph, and extract single loops one by one for all strongly connected components SCCs to obtain multiple single loops;
[0009] Classify multiple single loops and analyze the combination relationship of the multiple single loops in the corresponding strongly connected component (SCC) after classification, so as to obtain the oscillation condition corresponding to the strongly connected component.
[0010] Preferably, a directed graph corresponds to one or more strongly connected components (SCCs); the analysis of all the strongly connected components (SCCs) in the directed graph specifically includes:
[0011] Use the Tarjan algorithm to analyze one or more strongly connected components (SCCs) in the directed graph.
[0012] Preferably, one strongly connected component (SCC) corresponds to one or more single loops; and the extraction of single loops is performed one by one for all the strongly connected components (SCCs) to obtain multiple single loops, which specifically includes:
[0013] Use the depth-first search algorithm (DFS) to extract single loops from one or more strongly connected components to obtain multiple single loops.
[0014] Preferably, the oscillation conditions required for the single loop specifically include:
[0015] The output of the single loop is not a fixed logic gate, and the single loop has an odd number of NOT gates.
[0016] Preferably, the oscillation types corresponding to the single loop specifically include impossible oscillation, possible oscillation, and infinite oscillation;
[0017] The impossible oscillation is specifically that the number of NOT gates in the single loop after equivalence is even and no negative feedback is generated;
[0018] The possible oscillation is specifically that the single loop is affected by other single loops in the same strongly connected component (SCC), but the number of NOT gates in the single loop after equivalence is odd;
[0019] The infinite oscillation is specifically that the single loop satisfies the oscillation condition.
[0020] Preferably, the oscillation conditions corresponding to the strongly connected component specifically include: complete oscillation, first-type local oscillation, second-type local oscillation, and no oscillation.
[0021] Preferably, the complete oscillation is specifically that the oscillation type corresponding to one or more single loops corresponding to the strongly connected component has infinite oscillation or the oscillation types corresponding to one or more single loops are all possible oscillations;
[0022] The specific local oscillation of the first type is that the oscillation types corresponding to one or more single loops of the strongly connected component are such that the logic gates where possible oscillations may occur can all oscillate, and there are both single loops with possible oscillations and impossible oscillations in the strongly connected component, and by backtracking in the single loops with impossible oscillations, the requirement that the logic gates of all single loops with possible oscillations are not locked can be satisfied;
[0023] The specific local oscillation of the second type is that there is a single loop whose corresponding oscillation type is such that the logic gate where possible oscillation may occur can oscillate, and there are both single loops with possible oscillations and impossible oscillations in the strongly connected component, and by backtracking in the single loops with impossible oscillations, the requirement that the logic gates of all single loops with possible oscillations are not locked can be satisfied, and at the same time, by backtracking in the single loops with possible oscillations, the requirement that the logic gates of all single loops with impossible oscillations are not locked can be satisfied;
[0024] The non-oscillation specifically means that the oscillation types corresponding to one or more single loops of the strongly connected component are all impossible oscillations.
[0025] Preferably, it further includes:
[0026] Backtrack the strongly connected components that do not conform to the oscillation situation to determine the final oscillation situation of the strongly connected components.
[0027] Preferably, the non-oscillation further includes that the requirements still cannot be met after backtracking.
[0028] In the present invention, the proposed method for identifying whether a digital gate circuit can oscillate is to obtain the digital gate circuit to be identified and model the digital gate circuit as a directed graph; analyze all strongly connected components SCCs in the directed graph, and extract single loops one by one for all strongly connected components SCCs to obtain multiple single loops; classify the multiple single loops and analyze the combination relationship of the classified multiple single loops in the corresponding strongly connected components SCCs to obtain the oscillation situation corresponding to the strongly connected components. It provides a set of solutions for automatically detecting whether a cross-combination logic loop can oscillate, simply and efficiently finds the oscillation conditions when a digital logic gate oscillates, classifies the oscillation situations of the strongly connected components and the logic combination loops therein, gradually narrows the analysis scope, more systematically identifies and analyzes the possibility of logic gate oscillation, helps designers lock the oscillation area, and is helpful for solving design problems. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 It is a schematic diagram of the overall structure of the method for identifying whether a digital gate circuit can oscillate according to the present invention;
[0030] Figure 2Schematic diagram of a directed graph for the method of the present invention for identifying whether a digital gate circuit can oscillate;
[0031] Figure 3 Analysis process diagram of strongly connected components for the method of the present invention for identifying whether a digital gate circuit can oscillate;
[0032] Figure 4 Schematic diagram of the logic gate backtracking process for the method of the present invention for identifying whether a digital gate circuit can oscillate;
[0033] Figure 5 Schematic diagram of the digital gate circuit structure for the method of the present invention for identifying whether a digital gate circuit can oscillate based on BJT Figure 1 ;
[0034] Figure 6 Schematic diagram of the digital gate circuit structure for the method of the present invention for identifying whether a digital gate circuit can oscillate; Figure 2 ;
[0035] Figure 7 Schematic diagram of the digital gate circuit structure for the method of the present invention for identifying whether a digital gate circuit can oscillate; Figure 3 ;
[0036] Figure 8 Schematic diagram of the digital gate circuit structure for the method of the present invention for identifying whether a digital gate circuit can oscillate; Figure 4 ;
[0037] Figure 9 Schematic diagram of the digital gate circuit structure for the method of the present invention for identifying whether a digital gate circuit can oscillate; Figure 5 。 Detailed implementation manners
[0038] Refer to Figures 1-9 , a method for identifying whether a digital gate circuit can oscillate proposed by the present invention includes the following steps:
[0039] S1. Obtain the digital gate circuit to be identified and model the digital gate circuit as a directed graph.
[0040] Specifically, a digital gate circuit can be considered as a directed graph, and a single logic gate is a node. Oscillation occurs in a logic combination loop with negative feedback because negative feedback can cause the current output signal to continuously flip, thereby forming an oscillation. In a directed graph, the strongly connected component SCC is where there is a loop. A strongly connected component refers to a part of a directed graph where every node has a loop that can return from the starting point to the starting point, and there may be many single loops in the strongly connected component. For example Figure 2As shown, nodes 8 and 9, and nodes 1, 2, 3, 4, 5, and 6 respectively form strongly connected components, and each strongly connected component contains many single loops, such as loops 1, 2, 3; loops 2, 3, 4, 5; and loops 2, 3, etc. Therefore, the condition for judging the oscillation of a digital gate circuit is to first find all the strongly connected components.
[0041] S2. Analyze all the strongly connected components SCC in the directed graph, and extract single loops one by one from all the strongly connected components SCC to obtain multiple single loops.
[0042] In this embodiment, a directed graph corresponds to one or more strongly connected components SCC; analyzing all the strongly connected components SCC in the directed graph specifically includes: using the Tarjan algorithm to analyze one or more strongly connected components SCC in the directed graph.
[0043] Specifically, in this method, the search for strongly connected components is based on the tarjan algorithm. During this search process, the nodes passed through are marked. When it is found that the points connected to a certain node have already been marked, it means that a loop has been found, and all the points on this loop form a strongly connected component. In the specific implementation process, we can use the stack data structure to record the searched points. When a loop is encountered, then the elements in the stack are popped out one by one until the starting point is popped, and then continue to search for the next strongly connected component.
[0044] In this embodiment, one strongly connected component SCC corresponds to one or more single loops; and single loops are extracted one by one from all the strongly connected components SCC to obtain multiple single loops, specifically including:
[0045] Use the depth-first search algorithm DFS to extract single loops from one or more strongly connected components to obtain multiple single loops.
[0046] Specifically, based on the depth-first search algorithm DFS, find all the single loops in these strongly connected components. It recursively explores the adjacent points of each vertex and uses a stack to track the current path to detect the existence of a loop. When a loop is found, it stops exploring the current path and backtracks to explore other possible paths. Its highlight is that it records all the vertices that have been visited and all their adjacent points have been visited, preventing unnecessary repeated exploration. As Figure 2 As shown, perform a DFS operation on node 1. When exploring node 3, there are 3 adjacent points, namely 1, 4, and 6 at this time. When exploring node 4, it will be found that there is no loop that can return to node 1, so node 4 will be recorded. When encountering node 4 during the exploration of node 6, it will be directly considered that no loop has been found. This greatly reduces the number of searches and shortens the time to find a loop.
[0047] S3. Classify multiple single loops, and analyze the combination relationship of the multiple single loops in the corresponding strongly connected component (SCC) after classification to obtain the oscillation condition corresponding to the strongly connected component.
[0048] In this embodiment, the oscillation conditions required for a single loop specifically include: the output of the single loop is not a fixed logic gate, and the single loop has an odd number of NOT gates.
[0049] In this embodiment, the oscillation types corresponding to a single loop specifically include impossible oscillation, possible oscillation, and infinite oscillation. Impossible oscillation specifically means that the number of logic gate NOTs after the single loop is equivalent is even and no negative feedback is generated; possible oscillation specifically means that the single loop is affected by other single loops in the same strongly connected component (SCC), but the number of logic gate NOTs after the single loop is equivalent is odd; infinite oscillation specifically means that the single loop satisfies the oscillation condition.
[0050] Specifically, after finding these single loops, by classifying these single loops and analyzing their combination relationship in the strongly connected component, it is possible to determine whether the loop can oscillate.
[0051] The present invention defines the input port of the logic gate in the strongly connected component that is not connected to the strongly connected component as an external connection port. For the logic gate to be able to oscillate continuously, the premise is to perform a logic setting on the logic gate with an external connection port so that its output cannot be locked, that is, the output signal changes with the change of the input signal in the strongly connected component. The logic setting determines the signal value of the external connection port according to the type of the logic gate. For example, for an AND gate, if its external connection port is 1, then the output of the logic gate is equal to the input in the strongly connected component.
[0052] After performing a logic setting on the external connection port to satisfy the non-fixed output, the external connection port will not affect the output signal of the logic gate. Therefore, in this case, the external connection port can be ignored and is equivalent to a logic gate with only one input terminal. For example, logic gates such as NAND and NOR whose input and output are inverted can be equivalent to a single-input logic gate NOT with the same input and output inversion. To ensure that the loop can oscillate, its feedback must be negative feedback, that is, the number of NOTs is odd. And the single loops in the strongly connected component affect each other. The present invention divides the single loops in the strongly connected component into three types: impossible oscillation (type 0), possible oscillation (type 1), and infinite oscillation (type 2).
[0053] In this embodiment, the oscillation conditions corresponding to the strongly connected component specifically include: complete oscillation, local oscillation of the first type, local oscillation of the second type, and no oscillation.
[0054] Specifically, the full oscillation specifically refers to that the oscillation types corresponding to one or more single loops in the strongly connected component are infinite oscillations, or the oscillation types corresponding to one or more single loops are all possible oscillations;
[0055] The first type of local oscillation specifically means that the logic gates where the oscillation types corresponding to one or more single loops in the strongly connected component are possible oscillations can all oscillate, and there are single loops with possible oscillations and impossible oscillations in the strongly connected component at the same time, and by backtracking in the single loops with impossible oscillations, the requirement that the logic gates of all single loops with possible oscillations are not locked can be satisfied;
[0056] The second type of local oscillation specifically means that there is any single loop where the oscillation type is possible oscillation, and the logic gate where it is located can oscillate, and there are single loops with possible oscillations and impossible oscillations in the strongly connected component at the same time, and by backtracking in the single loops with impossible oscillations, the requirement that the logic gates of all single loops with possible oscillations are not locked can be satisfied, and at the same time, by backtracking in the single loops with possible oscillations, the requirement that the logic gates of all single loops with impossible oscillations are not locked can be satisfied;
[0057] No oscillation specifically means that the oscillation types corresponding to one or more single loops in the strongly connected component are all impossible oscillations, or the requirements still cannot be met after backtracking.
[0058] In these cases, the situation where all single loops are of type 0 in full oscillation and no oscillation can be judged when grading the single loops, and the remaining situations focus on specific logic gates. The specific analysis process is as Figure 3 shown. First, set the initial result to ensure that the outputs of all logic gates in the strongly connected component are not locked; find the single loops in the strongly connected component and grade the single loops; judge whether all can oscillate; judge whether it is impossible to oscillate; perform preprocessing on the remaining situations and then further analyze.
[0059] S4. Backtrack the strongly connected components that do not meet the oscillation conditions to determine the final oscillation conditions of the strongly connected components.
[0060] Specifically, the remaining situation is that there are both type 0 and type 1 single loops in the strongly connected component. In this case, the oscillating signal may be fed back to the external ports of the type 1 single loops through the type 0 loops, which may cause the output value to be locked and interrupt the oscillation. To maintain this oscillation, backtracking is required to fix the output of a certain gate circuit in type 0 so that the fixed signal fed back to the external ports of type 1 can meet the requirement of not being locked. As Figure 6As shown, to prevent the port of gate circuit 2 from being locked, it is only necessary to assign a value of 0 to port a of gate circuit 1, which will also cause oscillations. However, in a few cases, even after traversing all 0-type loops, the requirements cannot be met. For example Figure 7 In the loop shown, logic gates 6, 7, and 8 cannot provide a stable input of 1 to the external port of logic gate 4, resulting in the loop composed of logic gates 1, 2, 3, 4, and 5 being unable to oscillate. This oscillation will also be included in the scope of investigation for backtracking in another 1-type loop, such as Figure 7 In the loop composed of logic gates 1, 2, and 9. By setting port a of logic gate 5 to 1, oscillation can be achieved, and the oscillation conditions can be obtained. Therefore, to avoid this situation, we need to perform two types of backtracking on the loop. One is for the logic gates in the 0-type loop only, and the other is for all logic gates except the self-logic gate. The former is performed first, and only when the first backtracking cannot achieve oscillation, the second backtracking is carried out.
[0061] Before performing backtracking, preprocessing needs to be carried out. Similar to the logical equivalence of dual-input ports in a single loop, loops between strongly connected components also need to preprocess special logical combinations, namely the embedding between 0-type and 1-type. As Figure 8 shown, in the logical combination loop composed of logic gates 1, 2, 3, 4, and 5, there is a 0-type logical combination loop composed of logic gates 2, 3, and 6. For the ports of the head and tail logic gates of this 0-type logical combination loop, the logic gates they are connected to, except for the feedback, are all on the 1-type loop. Similar to this form of embedding, it can be considered that this 0-type loop has also been made oscillatable. The preprocessing is to eliminate this possibility. First, find the situation where a 0-type loop and a 1-type loop have more than one identical logic gate. If for all ports of the head and tail logic gates among these identical logic gates, the source logic gates except for the feedback are all in this 1-type loop, then it indicates that this 0-type loop is embedded in this 1-type loop, and record all the identical logic gates. When backtracking the logic gates, skip these identical logic gates.
[0062] After the preprocessing is completed, backtracking can be performed on each logic gate in the 1-type loop, and its main process is as Figure 4 shown.
[0063] The purpose of backtracking is exactly the opposite of that of single-loop oscillation. The latter is to ensure the transmission of oscillation, while the former is to find the logic gates that meet the conditions and lock them. First, the objects of backtracking are the logic gates in the single loop of type 1 whose external ports are connected in the entire strongly connected component. Trace back along the external ports in the reverse direction to find the logic gates that meet the requirements and lock them. The requirement here is that the fixed output of the logic gate can satisfy the change of the output of the backtracking object with the input, rather than being fixed. It should be noted that the logic gates found must be on the strongly connected component or the loop of type 0, rather than on the corresponding loop of type 1. If the requirements cannot be met after traversing all the logic gates, it proves that the loop of type 1 cannot oscillate. During the backtracking process, two variables, requireType and nextrequireType, are designed to represent the logic gates required by the current loop and all the logic gates required for the next iterative backtracking, respectively. Take Figure 9 as an example. Logic gates 1, 2, 3, and 4 form a logic loop of type 1. For logic gate 2, its external port is connected to a loop of type 0, and backtracking is required for logic gate 2. Logic gate 2 is AND. At this time, requireType should satisfy that it can stably output 1 in the locked state, that is, NAND, or OR. And its next logic gate is NOT, so its nextrequireType should be 1 - requireType, that is, the logic gate corresponding to 0. At the same time, logic gate 8 does not meet the requirements, so backtracking continues for logic gate 8, and its requireType is the nextrequireType of the previous backtracking. And so on. When iterating to logic gate 5, the requirements are met, and logic gate 5 is locked. Then the external port of the original backtracking object, logic gate 2, can obtain a stable input of 1, so that the output changes with the input.
[0064] There must be logic gates in the SCC that do not have external ports. In such cases, even if requireType does not have an external port to lock the logic gate, backtracking is still required in this situation. Only after all the logic gates that need to be backtracked in a loop of type 1 meet the requirements can it be ensured that the loop can oscillate. Since the input values of all external ports are preset to ensure the smooth flow of oscillation, only by modifying the corresponding external ports on the basis of the preset values during backtracking can all the conditions for loop oscillation be obtained.
[0065] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.
Claims
1. A method for identifying whether a digital gate circuit can oscillate, characterized in that: include: Acquire a digital gate circuit to be identified, and model the digital gate circuit as a directed graph; Analyze all strongly connected components SCC in the directed graph, and extract single loops from all the strongly connected components SCC one by one to obtain multiple single loops; The plurality of single loops are classified, and the combination relationship of the plurality of single loops in the corresponding strongly connected components SCC after classification is analyzed to obtain the oscillation conditions corresponding to the strongly connected components.
2. The method for identifying whether a digital gate circuit can oscillate according to claim 1, characterized in that: A directed graph corresponds to one or more strongly connected components SCC; analyzing all strongly connected components SCC in the directed graph specifically includes: The Tarjan algorithm is used to analyze one or more strongly connected components SCC in the directed graph.
3. The method for identifying whether a digital gate circuit can oscillate according to claim 3, characterized in that: One strongly connected component SCC corresponds to one or more single loops; and extracting single loops from all strongly connected components SCC one by one to obtain multiple single loops specifically includes: A single loop is extracted from one or more strongly connected components by using a depth-first search algorithm DFS to obtain multiple single loops.
4. The method for identifying whether a digital gate circuit can oscillate according to claim 1, characterized in that: The oscillation conditions required for the single loop specifically include: The single loop has a non-fixed logic gate output and has an odd number of NOT gates.
5. The method for identifying whether a digital gate circuit can oscillate according to claim 4, characterized in that: The oscillation types corresponding to the single loop specifically include impossible oscillation, possible oscillation and infinite oscillation; The impossible oscillation specifically means that the number of logic gates NOT after the single loop is equivalent is an even number, and no negative feedback is generated; The possible oscillation is specifically that the single loop is affected by other single loops in the same strongly connected component SCC, but the number of logic gates NOT after the single loop is equivalent is an odd number; The infinite oscillation specifically means that the single loop satisfies the oscillation condition.
6. The method for identifying whether a digital gate circuit can oscillate according to claim 5, characterized in that: The oscillation conditions corresponding to the strongly connected components specifically include: complete oscillation, first type local oscillation, second type local oscillation and no oscillation.
7. The method for identifying whether a digital gate circuit can oscillate according to claim 6, characterized in that: The complete oscillation specifically means that the oscillation type corresponding to one or more single loops corresponding to the strongly connected component has infinite oscillation or the oscillation type corresponding to one or more single loops is possible oscillation; The first type of local oscillation is specifically that the oscillation type corresponding to one or more single loops corresponding to the strongly connected component is that the logic gates where the possible oscillation is located can all oscillate, and there are both single loops that may oscillate and single loops that cannot oscillate in the strongly connected component, and the requirement that the logic gates of all possible oscillating single loops are not locked can be met by backtracking in the single loop that cannot oscillate; The second type of local oscillation specifically refers to the existence of any single loop corresponding to an oscillation type where the logic gate where the possible oscillation is located can oscillate, and there are both single loops that may oscillate and single loops that cannot oscillate in the strongly connected component, and the requirement that all logic gates of the single loop that may oscillate are not locked can be met by backtracking in the single loop that cannot oscillate, and the requirement that all logic gates of the single loop that cannot oscillate are not locked can be met by backtracking in the single loop that may oscillate; Specifically, the non-oscillation means that the oscillation types corresponding to one or more single loops corresponding to the strongly connected component are all impossible oscillations.
8. The method for identifying whether a digital gate circuit can oscillate according to claim 7, characterized in that: Also includes: The strongly connected components that do not meet the oscillation condition are backtracked to determine the final oscillation condition of the strongly connected components.
9. The method for identifying whether a digital gate circuit can oscillate according to claim 8, characterized in that: The no shock also includes that the requirements cannot be met after backtracking.