Method of configuring memory, memory package and system on chip

Abstract

A method of configuring a memory, a memory package, and a system on chip are provided. In one or more examples, the method includes disposing a first memory physical layer (PHY) interface on a surface of a computing die and connecting a first memory to the first memory PHY interface of the computing die via a first through silicon via (TSV) connection. The method includes connecting the second memory to a base die connected to the computing die via a silicon intermediate, disposing the computing die on the silicon intermediate, and disposing the base die on the silicon intermediate.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 608,822, filed on Dec. 11, 2023, which is incorporated herein by reference for all purposes. Technical Field

[0002] The disclosure generally relates to memory systems, and more particularly, to methods of configuring memories, memory packages, and systems-on-chip. Background Art

[0003] This background art section is only intended to provide context, and the disclosure of any concepts in this section does not constitute an admission that such concepts are prior art.

[0004] As technology advances, the size of electronic devices is decreasing, while the amount of data is increasing rapidly as data is collected by devices such as mobile devices, Internet of Things (IoT) devices, airborne (remote sensing) devices, software logs, cameras, microphones, radio frequency identification (RFID) readers, wireless sensor networks, etc. As the size of electronic devices decreases, the heat generated by components of such electronic devices (e.g., memories, processors, etc.) can increase. There is still a need to improve systems and methods for efficient power usage in electronic devices.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background of the disclosure, and thus it may contain information that does not constitute prior art. Summary of the Invention

[0006] In various embodiments, the systems and methods described herein include systems, methods, and devices for high-bandwidth memory configuration. In some aspects, the techniques described herein relate to a method of configuring a memory, the method including: setting a first memory physical layer (PHY) interface on a surface of a compute die; connecting a first memory to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection; connecting a second memory to a substrate die, the substrate die being connected to the compute die via a silicon interposer; and setting the compute die and the substrate die on the silicon interposer.

[0007] In some aspects, the techniques described herein relate to a method, wherein the first memory includes a first memory die stacked on the first memory PHY interface and a second memory die stacked on the first memory die.

[0008] In some aspects, the techniques described herein relate to a method, wherein the first memory die is connected to the first memory PHY interface via a first TSV connection, and the second memory die is connected to the first memory die via a first TSV connection.

[0009] In some aspects, the techniques described herein relate to a method in which a second memory includes a third memory die stacked on a substrate die and a fourth memory die stacked on the third memory die.

[0010] In some aspects, the techniques described herein relate to a method in which the third memory die is connected to the substrate die via a second TSV connection and the fourth memory die is connected to the third memory die via a second TSV connection.

[0011] In some aspects, the techniques described herein relate to a method in which a compute die includes a second memory PHY interface of the compute die, a first memory PHY interface is disposed on an inner surface of the compute die, and the second memory PHY interface is disposed on one side of the compute die.

[0012] In some aspects, the techniques described herein relate to a method in which a compute die includes a first die-to-die (D2D) interface disposed on one side of the compute die.

[0013] In some aspects, the techniques described herein relate to a method in which a compute die is connected to a second compute die via a second D2D interface of the compute die and a silicon intermediate.

[0014] In some aspects, the techniques described herein relate to a method in which a substrate die includes a memory PHY interface of the substrate die or a D2D interface of the substrate die.

[0015] In some aspects, the techniques described herein relate to a method in which the second memory or the first memory includes at least one of a high bandwidth memory, a static random access memory, a dynamic random access memory, or a flash memory.

[0016] In some aspects, the techniques described herein relate to a method in which a compute die includes a graphics processor die.

[0017] In some aspects, the techniques described herein relate to a memory package that includes: a first memory physical layer (PHY) interface disposed on a surface of a compute die; a first memory connected to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection; a substrate die coupled with the compute die and disposed on a silicon intermediate, wherein the compute die is disposed on the silicon intermediate and connected to the substrate die via the silicon intermediate; and a second memory connected to the substrate die.

[0018] In some aspects, the techniques described herein relate to a memory package in which the first memory includes a first memory die stacked on the first memory PHY interface and a second memory die stacked on the first memory die.

[0019] In some aspects, the techniques described herein relate to a memory package in which a first memory die is connected to a first memory PHY interface via a first TSV connection, and a second memory die is connected to the first memory die via a first TSV connection.

[0020] In some aspects, the techniques described herein relate to a memory package in which a second memory includes a third memory die stacked on a substrate die and a fourth memory die stacked on the third memory die.

[0021] In some aspects, the techniques described herein relate to a memory package in which the third memory die is connected to the substrate die via a second TSV connection, and the fourth memory die is connected to the third memory die via a second TSV connection.

[0022] In some aspects, the techniques described herein relate to a memory package in which a computing die includes a second memory PHY interface of the computing die, the first memory PHY interface is disposed on an inner surface of the computing die, and the second memory PHY interface is disposed on one side of the computing die.

[0023] In some aspects, the techniques described herein relate to a system-on-chip (SoC) that includes: a computing die disposed on a silicon intermediate; a substrate die bonded to the computing die and disposed on the silicon intermediate; and a memory bonded to the computing die and the substrate die, the memory including: a first memory physical layer (PHY) interface disposed on a surface of the computing die; a first memory connected to the first memory PHY interface of the computing die via a first through-silicon via (TSV) connection; and a second memory connected to the substrate die via a second TSV connection.

[0024] In some aspects, the techniques described herein relate to an SoC in which a first memory includes a first memory die stacked on the first memory PHY interface and a second memory die stacked on the first memory die.

[0025] In some aspects, the techniques described herein relate to an SoC in which the first memory die is connected to the first memory PHY interface via a first TSV connection, and the second memory die is connected to the first memory die via a first TSV connection.

[0026] A computer-readable medium is disclosed. The computer-readable medium can store instructions that, when executed by a computer, cause the computer to perform operations that are substantially the same as or similar to the operations further disclosed herein. Similarly, a non-transitory computer-readable medium, apparatus, and system for performing operations that are substantially the same as or similar to the operations described herein are further disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects of the systems and methods will be better understood when the present application is read in view of the following drawings, in which like numerals indicate like or identical elements. Additionally, the drawings provided herein are for the purpose of illustrating specific embodiments only; other embodiments that may not be explicitly illustrated are not excluded from the scope of the disclosure.

[0028] These and other features and advantages of the present disclosure will be appreciated and understood with reference to the specification, claims, and drawings.

[0029] Figure 1 Shows an example system according to one or more embodiments described herein.

[0030] Figure 2 Shows details of a system according to one or more embodiments described herein Figure 1 of.

[0031] Figure 3 Shows an example system according to one or more embodiments described herein.

[0032] Figure 4 Shows an example system according to one or more embodiments described herein.

[0033] Figure 5 Shows an example system according to one or more embodiments described herein.

[0034] Figure 6 Shows an example system according to one or more embodiments described herein.

[0035] Figure 7 Shows an example system according to one or more embodiments described herein.

[0036] Figure 8 Shows an example system according to one or more embodiments described herein.

[0037] Figure 9 Depicts a flowchart showing an example method associated with the disclosed system according to an example embodiment described herein.

[0038] Figure 10A flowchart depicting an example method associated with the disclosed system in accordance with example embodiments described herein.

[0039] Although the systems and methods herein admit of various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described. The drawings may not be to scale. However, it is to be understood that the drawings and the detailed description thereof are not intended to limit the systems and methods to the particular forms disclosed, but on the contrary, are intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the systems and methods as defined by the appended claims. Detailed Description

[0040] Details of one or more embodiments of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0041] Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments are shown. In fact, the disclosures may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Unless otherwise indicated, the term "or" is used herein in its alternative and conjunctive senses. The terms "exemplary" and "example" are used for examples that do not indicate a quality level. The same numbers always refer to the same elements. The arrows in each figure depict bidirectional data flow and / or bidirectional data flow capabilities. The terms "path", "route", and "way" may be used interchangeably herein.

[0042] Embodiments of the present disclosure may be implemented in various ways, including as a computer program product including a manufactured article. The computer program product may include a non-transitory computer-readable storage medium that stores applications, programs, program components, scripts, source code, program code, object code, byte code, compiled code, interpreted code, machine code, executable instructions, etc. (also referred to herein as executable instructions, instructions for execution, computer program product, program code, and / or similar terms that may be used interchangeably herein). Such non-transitory computer-readable storage media include all computer-readable media (including volatile and non-volatile media).

[0043] In one embodiment, the non-volatile computer-readable storage medium may include a floppy disk, flexible disk, hard disk, solid-state storage device (SSD) (e.g., solid-state drive (SSD), solid-state card (SSC), solid-state module (SSM)), enterprise flash drive, magnetic tape, or any other non-transitory magnetic medium, etc. The non-volatile computer-readable storage medium may include punched cards, paper tape, optical mark sheets (or any other physical medium with a hole pattern or other optically recognizable marks), compact disc read-only memory (CD-ROM), rewritable compact disc (CD-RW), digital versatile disc (DVD), Blu-ray disc (BD), any other non-transitory optical medium, etc. Such non-volatile computer-readable storage medium may include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory (e.g., serial, NAND, NOR, etc.), multimedia memory card (MMC), secure digital (SD) memory card, smart media card, compact flash (CF) card, memory stick, etc. In addition, the non-volatile computer-readable storage medium may include conductive-bridging random-access memory (CBRAM), phase-change random-access memory (PRAM), ferroelectric random-access memory (FeRAM), non-volatile random-access memory (NVRAM), magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), silicon-oxide-nitride-oxide-silicon memory (SONOS), floating junction gate random-access memory (FJG RAM), Millipede memory, racetrack memory, etc.

[0044] In one embodiment, a volatile computer-readable storage medium may include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), fast page mode dynamic random access memory (FPM DRAM), extended data output dynamic random access memory (EDO DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), double data rate type two synchronous dynamic random access memory (DDR2 SDRAM), double data rate type three synchronous dynamic random access memory (DDR3 SDRAM), graphics DDR (GDDR), Rambus dynamic random access memory (RDRAM), two-transistor RAM (TTRAM), thyristor RAM (T-RAM), zero-capacitor (Z-RAM), Rambus in-line memory module (RIMM), dual in-line memory module (DIMM), single in-line memory module (SIMM), video random access memory (VRAM), cache memory (including various levels), flash memory, register memory, and the like. It will be understood that where an embodiment is described as using a computer-readable storage medium, other types of computer-readable storage media may be substituted for or used in addition to the above computer-readable storage media.

[0045] It should be understood that various embodiments of the present disclosure may be implemented as a method, apparatus, system, computing device, computing entity, etc. Thus, embodiments of the present disclosure may take the form of an apparatus, system, computing device, computing entity, etc. that executes instructions stored on a computer-readable storage medium to perform specific steps or operations. Accordingly, embodiments of the present disclosure may take the form of a full hardware embodiment, a full computer program product embodiment, and / or an embodiment that includes a combination of a computer program product and hardware that executes specific steps or operations.

[0046] Embodiments of the present disclosure will be described below with reference to the block diagrams and flowcharts. Therefore, it should be understood that each block of the block diagrams and flowcharts can be implemented in the form of a computer program product, a fully hardware embodiment, a combination of hardware and a computer program product, and / or a device, system, computing device, computing entity, etc. that executes instructions, operations, steps, and similar terms that can be used interchangeably (e.g., executable instructions, instructions for execution, program code, etc.) on a computer-readable storage medium. For example, the retrieval, loading, and execution of code can be performed sequentially such that one instruction is retrieved, loaded, and executed at a time. In some example embodiments, the retrieval, loading, and / or execution can be performed in parallel such that multiple instructions are retrieved, loaded, and / or executed together. Thus, such embodiments can produce a machine that executes a specific configuration of steps or operations specified in the block diagrams and flowcharts. Therefore, the block diagrams and flowcharts support various combinations of embodiments for executing the specified instructions, operations, or steps.

[0047] References to "one embodiment" or "an embodiment" in the present specification mean that the particular features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases with similar meanings) that appear throughout the present specification may not necessarily all refer to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" will not necessarily be construed as being preferred or advantageous over other embodiments. Further, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Moreover, depending on the context discussed herein, singular terms may include the corresponding plural forms, and plural terms may include the corresponding singular forms. Similarly, hyphenated terms (e.g., "two-dimensional", "pre-determined", "pixel-specific", etc.) may occasionally be used interchangeably with their corresponding non-hyphenated versions (e.g., "two dimensional", "predetermined", "pixelspecific", etc.), and capitalized entries (e.g., "Counter Clock", "Row Select", "PIXOUT", etc.) may be used interchangeably with their corresponding non-capitalized versions (e.g., "counter clock", "row select", "pixout", etc.). Such occasional interchangeability should not be regarded as inconsistent with each other.

[0048] Moreover, depending on the context discussed herein, singular terms may include the corresponding plural forms, and plural terms may include the corresponding singular forms. It should also be noted that the various figures (including component diagrams) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Similarly, the various waveforms and timing diagrams are shown for illustrative purposes only. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. Additionally, if deemed appropriate, reference numerals are repeated among the figures to indicate corresponding and / or similar elements.

[0049] The terms used herein are for the purpose of describing some example embodiments only and are not intended to limit the claimed subject matter. As used herein, unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well. It will also be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The terms "first", "second", etc. as used herein are used as labels for the nouns following them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly so defined. In addition, the same reference numerals may be used across two or more figures to refer to components, elements, blocks, circuits, units, or modules having the same or similar functionality. However, such use is for simplicity of illustration and ease of discussion only; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced components / modules are the only way to implement some example embodiments disclosed herein.

[0050] It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being "directly on", "directly connected to" or "directly coupled to" another element or layer, no intervening elements or layers are present. The same reference numerals always refer to the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0051] The terms "first", "second", etc. as used herein are used as labels for the nouns following them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly so defined. In addition, the same reference numerals may be used across two or more figures to refer to components, elements, blocks, circuits, units, or modules having the same or similar functionality. However, such use is for simplicity of illustration and ease of discussion only; it does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced components / modules are the only way to implement some example embodiments disclosed herein.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0053] As used herein, the term "module" refers to any combination of software, firmware, and / or hardware configured to provide the functionality described in connection with the module herein. For example, software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any of the embodiments described herein may include, for example, alone or in any combination, an assembly, hardwired circuitry, programmable circuitry, state machine circuitry, and / or firmware that stores instructions executed by the programmable circuitry. A module may be implemented jointly or individually as circuitry that forms part of a larger system (such as, but not limited to, an integrated circuit (IC), a system-on-chip (SoC), an assembly, etc.).

[0054] Increasing the number of memory channels can be a design consideration for increasing data processing, reducing latency, and reducing power usage in a computing system (such as, for example, an artificial intelligence (AI) system-on-chip (SoC)). Stacking memory directly on one or more computing dies can increase the number of memory channels. In some cases, memory can be stacked based on through-silicon via (TSV, or through-silicon via) bonding. A TSV can include a packaging technology that uses vertical electrical connections between silicon wafers or dies instead of conventional wiring for connecting chips. TSVs can be used to create 2.5D packages and / or 3D packages that contain multiple semiconductor dies.

[0055] The systems and methods described herein combine 3D stacking and 2.5D packaging to maximize the number of memory channels in a given system. The systems and methods implement the edges and the tops (such as, for example, the front surfaces) of the dies to increase the memory bandwidth of the computing dies. 2.5D stacking can include a technique (such as, for example, an interposer technique) for arranging two or more semiconductor chips on a silicon interposer (such as, side by side). The devices are typically manufactured separately and delivered as dies to an assembly room. A substrate or interposer can provide connectivity between the devices. 2.5D packaging can be used for applications with low power and / or high performance constraints. The front surface of a semiconductor chip can include the surface of a silicon wafer on which circuitry is formed. The wafer can be a thin slice of a cylindrical silicon ingot having a diameter ranging from 50 mm to 300 mm. On the surface of the wafer, hundreds of semiconductors having the same circuitry can be formed in a lattice arrangement.

[0056] Three-dimensional (3D) or 3D integrated circuit (3D IC) technology can be based on a process of vertically packaging two or more chips (e.g., within the same package). Through-silicon vias (TSVs), copper-copper (Cu-Cu) connections, TSV bond pad metal (TSV-BPM) bonding, hybrid bonding, wafer-on-wafer bonding, and / or integrated system-on-chip (SoIC) bonding can be used to interconnect devices. The first chip in a 3D stacked package can have a different function from the second chip in the 3D stacked package. 3D stacking can improve performance, power, and cost while also addressing challenges surrounding power delivery and thermal management. 3D ICs can be configured to act as a single device to achieve performance improvements at lower power and a smaller footprint than conventional two-dimensional packages.

[0057] In some cases, systems and methods can implement an interposer to achieve a combination of 3D stacking and 2.5D packaging. An interposer (e.g., a silicon interposer) can be an electrical interface that is in a slot or the wiring between connections to additional slots or connections. The purpose of the interposer can be to extend connections to wider pitches or to rewire connections to different connections. A silicon interposer can be a passive silicon component that is disposed on a package substrate and supports active dies. The interposer can allow signals to be remapped from one active chip to another active chip. The interposer can be used in multi-die chips or boards. The interposer can act as a bridge that connects individual dies and provides a high-speed communication interface. The interposer can provide high connectivity between dies and connected components. The interposer can be used in ball grid array (BGA) packages, multi-chip modules, and / or high-bandwidth memories.

[0058] In some cases, systems and methods can implement microbump technology to achieve a combination of 3D stacking and 2.5D packaging. In some configurations, microbump technology can be used to connect chips to an interposer. Microbump technology can be referred to as microbump bonding (MBB) and can allow 3D integration of semiconductor devices. MBB can include an integrated circuit (IC) chip with bumps, a circuit substrate, and a bonding adhesive. The bonding force of the bonding adhesive can create an electrical connection between the bumps on the IC. In some cases, a silicon substrate used as an interposer can be connected to the substrate through bump connections. The surface of the silicon substrate can be interconnected using a redistribution layer (RDL) wiring, while TSVs can be used as conduits for electrical connections between the upper and lower surfaces of the silicon substrate.

[0059] In some cases, systems and methods can implement a base die to achieve a combination of 3D stacking and 2.5D packaging. The base die can refer to the bottommost layer in a stacked memory. In some examples, a buffer die can be used in addition to or in place of the base die. In some cases, the base die can include and / or be referred to as a buffer die. In some cases, the base die can be configured to control a stacked memory (e.g., high bandwidth memory (HBM)). Adding the base die to a stack of memory dies can improve signal quality and signal strength, thereby increasing memory bandwidth.

[0060] In some cases, systems and methods can implement a memory physical layer (PHY) interface to achieve a combination of 3D stacking and 2.5D packaging. HBM can be incorporated into the physical layer IP interface. In some cases, the HBM PHY can receive data, parity, and HBM DRAM row-column commands from a memory controller via a DDR PHY interface (DFI), and then transfer the data, parity, and HBM DRAM row-column commands to the HBM memory using the HBM DRAM interface. The DFI can include an interface protocol that defines the signals, timing, and programmable parameters for transferring control information and data to and from a DRAM device and / or for transferring control information and data between a microcontroller and a PHY (e.g., HBM PHY, HBM 3D PHY (or, 3D HBM PHY)). It should be noted that the terms "high bandwidth memory" and "HBM" can be descriptions in the art that are understood to describe a form of memory. However, the terms "high bandwidth memory" and "HBM" can represent any suitable memory that includes one or more characteristics, including a relatively wide communication channel (e.g., a 4096-bit interface connected to a CPU or GPU), relatively low power consumption (e.g., lower power consumption than GDDR), relatively high capacity (e.g., higher capacity than GDDR), relatively high bandwidth (e.g., a bandwidth of up to 1 TB / s), residing on a silicon interposer (e.g., residing on the same silicon interposer as a processing unit), and / or at least one of 3D stacking.

[0061] In some cases, systems and methods can implement a die-to-die (D2D) interface to achieve a combination of 3D stacking and 2.5D packaging. The D2D interface can include functional blocks that allow for a data link between two silicon dies assembled in the same package. The D2D interface can be used in applications such as networking, high performance computing (HPC), hyperscale data centers, and AI systems. The D2D interface can provide high-speed, low-latency communication between two dies.

[0062] A compute die based on the described systems and methods can be fabricated with a first memory interface (e.g., HBM PHY) on one side or edge of the compute die and a second memory interface (e.g., 3D HBM PHY) on the front surface of the compute die. In some examples, multiple compute dies (e.g., four compute dies) can be connected to each other via respective D2D interfaces. Based on the multiple compute dies and the systems and methods described herein, 32 memory packages (e.g., 32 HBM packages) can be integrated within a single package. Based on the multiple compute dies, the systems and methods can provide a relatively high level of memory bandwidth (e.g., a single multi-die package can support 64 TB / s of HBM bandwidth based on HBM4 with 2 TB / s of memory bandwidth per HBM package).

[0063] High-performance applications such as AI have growing demands for speed and efficiency. According to some embodiments described herein, one or more hybrid arrangements and layouts of 2.5D stacked HBM and 3D stacked HBM provide a faster and more efficient memory system. In some embodiments, the number of HBM channels can be significantly increased to accommodate such growing demands.

[0064] The systems and methods described herein include multiple advantages and benefits. For example, the described hybrid memory stack systems and methods maximize the number of memory channels (e.g., HBM channels) of a given system (e.g., an AI compute SoC). The hybrid memory stack systems and methods increase memory bandwidth and capacity by leveraging both edge input / output (I / O) and front surface I / O (e.g., based on TSV connections). The hybrid memory stack systems and methods described herein reduce memory access latency and increase power efficiency based on a combination of 3D stacking and 2.5D packaging.

[0065] According to some embodiments described herein, an apparatus or method can include a first circuit having a first three-dimensional (3D) stacked HBM. The apparatus can also include a second circuit having a 2.5D stacked HBM connected to the first circuit.

[0066] In some embodiments, a first circuit may be connected to a second circuit via a silicon intermediary. According to some embodiments, the second circuit may include an HBM substrate die (e.g., an HBM buffer die). In some embodiments, the HBM substrate die may communicate with the silicon intermediary via a first HBM PHY connection on the HBM substrate die. In some embodiments, the HBM substrate die may also communicate with the first circuit via a second HBM PHY connection on the first circuit. In some embodiments, the first circuit may be connected to a third circuit including a second 3D stacked HBM. The first circuit may be connected to the third circuit via a die-to-die (D2D) interface. According to some embodiments, the first circuit may also include, for example, four 3D stacked HBMs. Implementations of the described techniques may include hardware, methods or processes, or computer software on a computer-accessible medium.

[0067] In some embodiments, a device may include a first compute die having a first 3D stacked HBM and a host. According to some embodiments, the device may also include a first circuit having a 2.5D stacked HBM connected to the first compute die.

[0068] According to some embodiments, the host may distribute data to the 3D stacked HBM and the 2.5D stacked HBM. According to some embodiments, the first compute die may be connected to the first circuit via an intermediary. The first circuit may also include an HBM substrate die. The HBM substrate die may communicate via the intermediary via a first HBM PHY connection on the HBM substrate die. The HBM substrate die may also communicate with the first compute die via a second HBM PHY connection on the first compute die. The first compute die may be connected to a second compute die including a second 3D stacked HBM. In some embodiments, the first compute die may be connected to the second compute die via a die-to-die interface. In some embodiments, each of the first compute die and the second compute die may have, for example, eight 3D stacked HBMs. Each of the first compute die and the second compute die may have at least two circuits having 2.5D stacked HBMs connected to the respective first compute die and second compute die. In some embodiments, each of the first compute die and the second compute die may have, for example, sixteen 3D stacked HBMs.

[0069] Figure 1 An example system 100 is shown in accordance with one or more embodiments described herein. In Figure 1 is shown a machine 105, which may be referred to as a host, system, or server. Although Figure 1 the machine 105 is depicted as a tower computer, the disclosed embodiments may extend to any form factor or type of machine. For example, the machine 105 may be a rack server, blade server, desktop computer, tower computer, mini-tower computer, desktop server, laptop computer, notebook computer, tablet computer, etc.

[0070] Machine 105 may include a processor 110, a memory 115, and a storage device 120. The processor 110 can be any kind of processor. Note that, for ease of illustration, the processor 110 along with other components discussed below are shown outside the machine: the disclosed embodiments may include these components within the machine. Although Figure 1 a single processor 110 is shown, the machine 105 may include any number of processors, each of which can be a single-core processor or a multi-core processor, each of which can implement a reduced instruction set computer (RISC) architecture or a complex instruction set computer (CISC) architecture, etc., and can be mixed in any desired combination.

[0071] The processor 110 may be coupled to the memory 115. The memory 115 can be any kind of memory (such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), persistent random access memory, ferroelectric random access memory (FRAM), or non-volatile random access memory (NVRAM) (such as magnetoresistive random access memory (MRAM), phase change memory (PCM), or resistive random access memory (ReRAM))). The memory 115 may include volatile memory and / or non-volatile memory. The memory 115 may use any desired form factor: for example, single in-line memory module (SIMM), dual in-line memory module (DIMM), non-volatile DIMM (NVDIMM), etc. The memory 115 can be any desired combination of different types of memory and can be managed by a memory controller 125. The memory 115 can be used to store data that can be referred to as "short-term": that is, data that is not expected to be stored for an extended period of time. Examples of short-term data may include temporary files, data used locally by an application (which may have been copied from other storage locations), etc. The memory 115 may include 3D stacked memory (e.g., 3D HBM) and / or 2.5D stacked memory (e.g., 2.5D HBM). In some cases, at least a portion of the memory 115 may be stacked on the processor 110. For example, at least a portion of the memory 115 may be stacked on the front surface of the compute die of the processor 110 (e.g., 3D HBM). Additionally or alternatively, at least a portion of the memory 115 may be stacked on one side or edge of the compute die of the processor 110 (e.g., 2.5D HBM).

[0072] Processor 110 and memory 115 may support an operating system under which various applications may run. These applications may issue requests (which may be referred to as commands) to read data from or write data to memory 115 or storage device 120. When storage device 120 is used to support an application that reads or writes data via a certain file system, device driver 130 may be used to access storage device 120. Although Figure 1 one storage device 120 is shown, any number (one or more) of storage devices may be present in machine 105. Storage device 120 may support any desired one or more protocols, and any desired one or more protocols include, for example, the Non-Volatile Memory Express (NVMe) protocol, the Serial Attached SCSI (SAS) protocol, or the Serial ATA (SATA) protocol. Storage device 120 may include any desired interface, and any desired interface includes, for example, a Peripheral Component Interconnect Express (PCIe) interface or a Compute Express Link (CXL) interface. Storage device 120 may adopt any desired form factor, and any desired form factor includes, for example, the U.2 form factor, the U.3 form factor, the M.2 form factor, the Enterprise and Data Center Standard Form Factor (EDSFF) (including all its series (such as the short E1, the long E1, and the E3 series)), or an Add-in Card (AIC).

[0073] Although Figure 1 the term "storage device" is used, the disclosed embodiments may include any storage device format that may benefit from the use of a compute storage unit, and examples of a compute storage unit may include a hard disk drive, a solid state drive (SSD), or a persistent memory device (such as PCM, ReRAM, or MRAM). Any reference to "storage device" or "SSD" hereinafter should be understood to include such other disclosed embodiments and other types of storage devices. In some cases, the term "storage unit" may encompass storage device 120 and memory 115.

[0074] Machine 105 may include a power supply 135. Power supply 135 may supply power to machine 105 and its components. Machine 105 may include a transmitter 145 and a receiver 150. Transmitter 145 or receiver 150 may be used to transmit or receive data, respectively. In some cases, transmitter 145 and / or receiver 150 may be used to communicate with memory 115 and / or storage device 120. Transmitter 145 may include a write circuit 160, and write circuit 160 may be used to write data to a storage device (such as a register) in memory 115 and / or storage device 120. In a similar manner, receiver 150 may include a read circuit 165, and read circuit 165 may be used to read data from a storage device (such as a register) in memory 115 and / or storage device 120.

[0075] In one or more examples, machine 105 may be implemented with any type of device. Machine 105 may be configured as one or more (e.g., as its host) of servers (such as compute servers, storage servers, storage nodes, network servers, supercomputers, data center systems, etc. or any combination thereof). Additionally or optionally, machine 105 may be configured as one or more (e.g., as its host) of computers (such as workstations, personal computers, tablets, smart phones, etc. or any combination thereof). Machine 105 may be implemented with any type of device that may be configured to "include, for example, accelerator devices, storage devices, network devices, memory expansion and / or buffer devices, central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), tensor processing unit (TPU), etc. or any combination thereof".

[0076] Any communication between devices including machine 105 (e.g., host, compute storage device, and / or any intermediate device) may occur through an interface that may be implemented with any type of wired and / or wireless communication medium, interface, protocol, etc. "including PCIe, NVMe, Ethernet, Non-Volatile Memory Express over Fabrics (NVMe-oF), Compute Express Link (CXL), and / or coherence protocols (such as CXL.mem, CXL.cache, CXL.IO, etc.), Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), Advanced eXtensible Interface (AXI), etc. or any combination thereof, Transmission Control Protocol / Internet Protocol (TCP / IP), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, any generation of wireless network including 2G, 3G, 4G, 5G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc. or any combination thereof". In some embodiments, the communication interface may include a communication fabric that includes one or more links, buses, switches, hubs, nodes, routers, translators, repeaters, etc. In some embodiments, system 100 may include one or more additional devices having one or more additional communication interfaces.

[0077] The functionality of the systems and methods described herein (including any functionality in host functionality (e.g., machine 105), device functionality, component functionality, etc.) can be implemented using hardware, software, firmware, or any combination thereof, including, for example, hardware and / or software combination logic, timing logic, timers, counters, registers, state machines, volatile memory (such as dynamic random access memory (DRAM) and / or static random access memory (SRAM)), non-volatile memory including flash memory, persistent memory (such as cross-grid non-volatile memory), memory with bulk resistance change, phase change memory (PCM), etc., and / or any combination thereof, complex programmable logic devices (CPLDs) that execute instructions stored in any type of memory, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), CPUs (including complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as RISC-V and / or ARM processors)), graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), etc. In some embodiments, one or more components of the systems and methods can be implemented as a system on a chip (SoC). In some cases, machine 105 can be an example of an SoC (e.g., an AI computing SoC) based on the systems and methods described herein.

[0078] In some examples, the hybrid memory stack systems and methods described herein enhance the operation of logic (e.g., logic circuits), hardware (e.g., processing units, memories, storage devices), software, firmware, etc. The hybrid memory stack systems and methods can improve the operation of any one or combination of multiplexers, registers, logic gates, arithmetic logic units (ALUs), caches, computer memories, microprocessors, processing units (CPUs, GPUs, NPUs, and / or TPUs), FPGAs, ASICs, etc.

[0079] The systems and methods described herein include multiple advantages and benefits. For example, the described hybrid memory stack systems and methods maximize the number of memory channels (e.g., HBM channels) on a given system (e.g., an AI computing SoC). The hybrid memory stack systems and methods increase memory bandwidth and capacity by leveraging both edge I / O and front surface I / O (e.g., based on TSV connections). The hybrid memory stack systems and methods described herein reduce memory access latency and increase power efficiency based on a combination of 3D stacking and 2.5D packaging.

[0080] Figure 2 Shown in accordance with examples described herein Figure 1Details of machine 105. In the illustrated example, machine 105 may include one or more processors 110. One or more processors 110 may include a memory controller 125 and a clock 205 that may be used to coordinate the operation of the components of the machine. Processor 110 may be coupled to memory 115. As an example, memory 115 may include random access memory (RAM), read-only memory (ROM), or other state-saving media. Processor 110 may be coupled to storage device 120 and network connector 210. Network connector 210 may be, for example, an Ethernet connector or a wireless connector. Processor 110 may be connected to bus 215. A user interface 220 and an input / output (I / O) interface port may be attached to bus 215. The input / output (I / O) interface port may be managed using an I / O engine 225, etc.

[0081] Figure 3 Illustrates an example system 300 in accordance with one or more embodiments described herein. In the illustrated example, system 300 includes a data center 305. In some embodiments, one or more data center racks 315 may be used. One or more data center racks 315 include any number or configuration of 2.5D stacked memory and 3D stacked memory. At least one data center rack 315 may have, for example, a top-of-rack router 310. The top-of-rack router 310 may include routing means configured to receive signaling, route processing and / or data requests to at least one data center rack 315, etc.

[0082] At least one data center rack 315 may include any number of combinations of 2.5D stacked memory (e.g., 2.5D HBM) and / or 3D stacked memory (e.g., 3D HBM), where the 2.5D stacked memory and / or 3D stacked memory may be stacked relative to a compute die. In some cases, the 2.5D stacked memory may be disposed adjacent to the compute die, and the 3D stacked memory may be stacked on the surface of the compute die. The compute die may include at least one of a graphics processing unit (GPU), a central processing unit (CPU), a tensor processing unit (TPU), a neural processing unit (NPU), a vision processing unit (VPU), a field programmable gate array (FPGA), a quantum processor, a microprocessor, a physics processing unit, and a host / controller device, etc. The arrangement of the 2.5D stacked memory and 3D stacked memory may be in any manner including a grid, in series, an organized arrangement, etc. In some embodiments, the number of 2.5D HBM stacks and 3D HBM stacks may be a power of two (e.g., 8, 16, 32, or 64), or any combination allowed by each die size and available space and technology.

[0083] Any functionality disclosed herein may be implemented in hardware, software, or a combination thereof, including combinational logic, sequential logic, one or more timers, counters, registers, and / or state machines, one or more complex programmable logic devices (CPLDs), FPGAs, application-specific integrated circuits (ASICs), CPUs (such as complex instruction set computers (CISC) processors (such as x86 processors) and / or reduced instruction set computers (RISC) processors (such as ARM processors)), GPUs, NPUs, TPUs, etc., or any combination thereof, that execute instructions stored in any type of memory. In some embodiments, one or more components may be implemented as an SoC (e.g., an AI computing SoC).

[0084] In some embodiments, storage devices may be individually arranged on respective data center racks 315. Any variations in the amount, location, and configuration of the storage devices may be considered. Any storage device disclosed herein may communicate via any interface and / or protocol, including PCIe, NVMe, NVMe-oF, Ethernet, TCP / IP, User Datagram Protocol (UDP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (RoCE), Fibre Channel, InfiniBand, SATA, SCSI, SAS, iWARP, Hypertext Transfer Protocol (HTTP), HBM PHY, HBM 3D PHY, D2D, etc., or any combination thereof.

[0085] In some embodiments, one or more storage devices may be implemented with, for example, multiple storage devices arranged in one or more servers. They may be configured in, for example, one or more server chassis, server racks, server rack groups, data rooms, data centers, edge data centers, mobile edge data centers, etc., and / or any combination thereof. In some embodiments, data center 305 may be implemented with one or more storage server clusters.

[0086] In some examples, data center 305 may be implemented with any type and / or configuration of network resources. For example, data center 305 may include any type of network fabric (such as Ethernet, Fibre Channel, InfiniBand, etc.) using any type of network protocol (such as Transmission Control Protocol / Internet Protocol (TCP / IP), RoCE, etc.). In some cases, data center 305 may include any type of storage interface and / or protocol (such as SATA, SCSI, SAS, NVMe, NVMe-oF, etc.). In some embodiments, data center 305 and / or at least one data center rack 315 may be implemented with one or more networks and / or network segments interconnected with one or more switches, routers, bridges, hubs, etc.

[0087] A variety of packaging techniques can be used to package the semiconductor devices described herein. For example, semiconductor devices constructed in accordance with the principles of the disclosed subject matter can be packaged using any of the following techniques: Package-on-Package (POP) technique, Ball Grid Array (BGA) technique, Land Grid Array (LGA), Chip Scale Package (CSP) technique, Plastic Leaded Chip Carrier (PLCC) technique, Plastic Dual In-line Package (PDIP) technique, Die Grids technique, Die-Level Wafer Form technique, Chip-on-Board (COB) technique, Ceramic Dual In-line Package (CERDIP) technique, Plastic Metric Quad Flat Pack (PMQFP) technique, Plastic Quad Flat Pack (PQFP) technique, Small Outline Integrated Circuit (SOIC) technique, Shrink Small Outline Package (SSOP) technique, Thin Small Outline Package (TSOP) technique, Thin Quad Flat Pack (TQFP) technique, System-in-Package (SIP) technique, Multi-Chip Package (MCP) technique, Wafer-Level Fabrication Package (WFP) technique, Wafer-Level Process Stack Package (WSP) technique, or other techniques known to those skilled in the art.

[0088] Figure 4 FIG. 400 illustrates an example system 400 in accordance with one or more embodiments described herein. System 400 may represent a side view of a system based on a high bandwidth memory configuration. In the example shown, system 400 includes one or more 2.5D HBM stacks (e.g., HBM stack 405), a base die 410 (e.g., a buffer die), a compute die 415, one or more 3D HBM stacks (e.g., HBM stack 420, HBM stack 425), TSVs 430, a silicon interposer 435, HBM PHY 440, HBM PHY 445, HBM 3D PHY 450, and HBM 3D PHY 455. As shown, HBM stack 405 includes a stack of HBMs. Although system 400 is depicted as having a stack of HBMs, additionally or alternatively, other memory types are contemplated, and other memory types may include at least one of RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory (including various levels), flash memory, register memory, other types of memory, and / or any combination thereof.

[0089] System 400 may include various electrical connections, and the various electrical connections may include power connections, timing connections (e.g., clock signals), and / or electrical data communication connections (e.g., input / output connections). Although System 400 provides examples of given electrical connections, any of the electrical connections in System 400 may include at least one of through-silicon vias (TSVs), TSV-to-backside process module (BPM) bonds, Cu-to-Cu connections, hybrid bonds, microbumps, wafer-on-wafer bonds, and / or integrated system-on-chip (SoC) bonds. As shown, substrate die 410 (e.g., HBM substrate die, HBM buffer die) may be electrically connected to compute die 415, HBM stack 405 may be electrically connected to substrate die 410, HBM stack 420 may be electrically connected to HBM 3D PHY 450, and / or HBM stack 425 may be electrically connected to HBM 3D PHY 455.

[0090] In the example shown, HBM stack 405 includes a stack of memories, where each layer of memory is electrically connected (e.g., the first layer of memory die is connected to the second layer of memory die, the second layer of memory die is connected to the third layer of memory die, etc.). In some cases, HBM stack 405 may include a 2.5D stacked HBM. As shown, the first layer of HBM stack 405 may be electrically connected to substrate die 410. For example, the first layer of memory die or the first memory die in HBM stack 405 may be stacked on substrate die 410 and electrically connected to substrate die 410 (e.g., via TSV connections, etc.), and the second layer of memory die or the second memory die in HBM stack 405 may be stacked on the first layer of memory die or the first memory die and electrically connected to the first layer of memory die or the first memory die (e.g., via TSV connections, etc.). In some cases, the electrical connection between HBM stack 405 and / or substrate die 410 may include at least one of TSVs, TSV-to-BPM bonds, Cu-to-Cu connections, hybrid bonds, microbumps, wafer-on-wafer bonds, and / or integrated SoC (SoIC) bonds. As shown, HBM PHY 440 may be electrically connected to HBM PHY 445 through silicon interposer 435. Thus, substrate die 410 may be electrically connected to compute die 415 through HBM PHY 440, silicon interposer 435, and HBM PHY 445. In some cases, HBM PHY 440 and / or HBM PHY 445 may include a die-to-die (D2D) interface. For example, substrate die 410 may be connected to compute die 415 via HBM PHY connections and / or D2D connections.

[0091] In the illustrated example, each of HBM stack 420 and HBM stack 425 includes a stack of memories, where each layer of memory is electrically connected (e.g., for each respective stack, the first layer of memory die is connected to the second layer of memory die, the second layer of memory die is connected to the third layer of memory die, etc.). In some cases, HBM stack 420 and / or HBM stack 425 may include 3D stacked HBM. As shown, the first layer of HBM stack 420 may be electrically connected to HBM 3D PHY 450. Additionally or alternatively, the first layer of HBM stack 425 may be electrically connected to HBM 3D PHY 455. In some cases, the electrical connection of HBM stack 420 and / or HBM stack 425 may include at least one of TSV, TSV-BPM bonding, Cu-Cu connection, hybrid bonding, micro-bumps, wafer-on-wafer bonding, and / or integrated SoC (SoIC) bonding. In the illustrated example, the layers of HBM stack 420 may be electrically connected via TSV 430, where the TSV may include one or more through-silicon vias. As shown, HBM 3D PHY 450 may be electrically connected to the first layer of HBM stack 420 via TSV 430.

[0092] In the illustrated example, HBM 3D PHY 450 may be formed on the surface (e.g., front surface) of compute die 415. Additionally or alternatively, HBM 3D PHY 455 may be formed on the surface (e.g., front surface) of compute die 415. In some cases, HBM PHY 445 may be formed on one side or edge of compute die 415, and / or HBM PHY 440 may be formed on one side or edge of substrate die 410. As shown, compute die 415 may be electrically connected to silicon interposer 435 via electrical connection 460. In some examples, electrical connection 460 may include at least one of TSV, TSV-BPM bonding, Cu-Cu connection, hybrid bonding, micro-bumps, wafer-on-wafer bonding, and / or integrated SoC (SoIC) bonding.

[0093] In some examples, compute die 415 may be a compute die such as a GPU, CPU, NPU, etc. As shown, compute die 415 may be connected to silicon interposer 435 based on one or more HBM PHY 445 and / or based on one or more HBM PHY 440 on HBM substrate die 410 to improve processing power.

[0094] In some embodiments, the silicon interposer 435 may be formed using silicon and / or other conductive and / or semiconductor materials and may be used to implement a high-bandwidth memory configuration for system 400 (e.g., to implement a 3D integrated circuit (IC)). In some cases, the silicon interposer 435 may include one or more connections for multiple HBM stacks. For example, the silicon interposer 435 may include electrical connections 460 as electrical connections to HBM stack 420 and / or HBM stack 425. In some cases, the silicon interposer 435 may include a first electrical connection (e.g., electrical connection 460) to HBM stack 420, a second electrical connection to HBM stack 425, a third electrical connection to a third HBM stack, etc. In some cases, the silicon interposer 435 may be configured to connect multiple compute dies (e.g., connect compute die 415 to at least a second compute die, etc.). In some embodiments, in one memory compute package (e.g., one AI compute SoC package), multiple compute dies may be connected via the silicon interposer 435. The high-bandwidth memory systems and methods of system 400 (e.g., 3D stacked HBM and 2.5D stacked HBM) enable high-speed data transfer and high-bandwidth processing for advanced AI programs and complex computations such as computer vision, weather prediction.

[0095] In some examples, the silicon intermediate 435 may couple the compute die 415 to the substrate. For example, the silicon intermediate 435 may be formed on the substrate. In some cases, the HBM PHY 440 or HBM PHY 445 may include a physical layer that provides a physical interconnect, the physical interconnect including a power connection and / or a communication connection to the compute die 415. In some cases, the HBM PHY 440, HBM PHY 445, HBM 3D PHY 450, and / or HBM 3D PHY 455 may be configured to receive and / or transmit address, data, and / or control signals between connected components (e.g., between the HBM stack 405, the base die 410, the compute die 415, the HBM stack 420, and / or the HBM stack 425). In some cases, the HBM PHY 440, HBM PHY 445, HBM 3D PHY 450, and / or HBM 3D PHY 455 may include one or more clock mechanisms to ensure that information (e.g., synchronously or asynchronously depending on the application or use) is received and / or transmitted correctly. The HBM PHY 440, HBM PHY 445, HBM 3D PHY 450, and / or HBM 3D PHY 455 may (e.g., in conjunction with a memory controller, an HBM controller, etc.) identify and correct data communication errors. In some examples, each compute die (e.g., compute die 415) may include a controller (e.g., for timing control, data communication control). Optionally, one controller may be configured to control multiple compute dies (e.g., for timing control, data communication control on the system 400).

[0096] Figure 5 FIG. 500 shows an example system 500 in accordance with one or more embodiments described herein. The system 500 may represent a side view of a system based on a high bandwidth memory configuration. In the example shown, the system 500 includes an HBM stack 505, a base die 510, a compute die 515, an HBM stack 520, an HBM stack 525, TSVs 530, a silicon intermediate 535, D2D interfaces 540, D2D interfaces 545, HBM 3D PHYs 550, and HBM 3D PHYs 555. As shown, the HBM stack 505 includes a stack of HBMs. As shown, the compute die 515 may be electrically coupled to the silicon intermediate 535 via an electrical connection 560. In some examples, the electrical connection 560 may include at least one of a TSV, a TSV-BPM bond, a Cu-Cu connection, a hybrid bond, a microbump, a wafer-on-wafer bond, and / or an integrated SoC (SoIC) bond.

[0097] As shown, the base die 510 may include a D2D interface 540, and the compute die 515 may include a D2D interface 545. As shown, the compute die 515 may be electrically connected to the base die 510 via the D2D interface 545 and the D2D interface 540. Accordingly, data may be sent between the HBM stack 520 and the HBM stack 505 via the D2D interface 545 and the D2D interface 540.

[0098] Figure 6 FIG. 600 illustrates an example system in accordance with one or more embodiments described herein. The system 600 may represent a top view of a system based on a high bandwidth memory configuration. The system 600 may include a compute die 605, an HBM stack 610, an HBM stack 615, and an HBM PHY 620. In some examples, the compute die 605 may be an example of the compute die 515, the HBM stack 610 may be an example of the HBM stack 505, the HBM stack 615 may be an example of the HBM stack 520 or the HBM stack 525, the HBM PHY 620 may be an example of the HBM 3D PHY 550 or the HBM 3D PHY 555, and the silicon interposer (e.g., electrically connected to the compute die 605) of the system 600 may be an example of the silicon interposer 535. In some cases, the compute die 605 may be formed on the silicon interposer of the system 600.

[0099] As shown, the system 600 may include a combination of stacked memories (e.g., a combination of 2.5D stacked HBM and 3D stacked HBM). As shown, the combination of stacked memories may include a plurality of 2.5D HBM stacks (e.g., the HBM stack 610) and a plurality of 3D HBM stacks (e.g., the HBM stack 615). As shown, the plurality of 2.5D HBM stacks may be attached to the compute die 605. As shown, the HBM stack 610 may be connected to the compute die 605 via the HBM PHY 620. In some cases, the HBM stack 615 may be connected to the compute die 605 via an HBM 3D PHY (e.g., the HBM 3D PHY 550, the HBM 3D PHY 555).

[0100] In the illustrated example, one or more 2.5D HBM stacks (e.g., HBM stack 610) may be attached to one side or edge of compute die 605, while one or more 3D HBM stacks (e.g., HBM stack 615) may be attached to the inner surface of compute die 605 (e.g., toward the central surface of compute die 605, away from the edge of compute die 605). Additionally or alternatively, relative to the illustrated example, one or more 2.5D HBM stacks may be attached to the top edge, side edge, or bottom edge (bottom side) of compute die 605. As shown, HBM stack 610 may be attached to the top edge (top side) of compute die 605.

[0101] Exemplary arrangements, configurations, and quantities of 2.5D stacked HBMs and 3D stacked HBMs are shown. Any number of 2.5D HBM stacks and / or 3D HBM stacks may be connected. For example, compute die 605 may have 4, 8, 12, 16, 32 3D HBM stacks on the front surface of compute die 605. In some examples, one or more additional compute dies may be attached to compute die 605 via a D2D connection.

[0102] The high bandwidth memory systems and methods described herein achieve improved performance (including high speed data transfer, high capacity, and high bandwidth processing for programs such as workflow simulation, climate modeling, and other AI applications).

[0103] Figure 7 An example system 700 is shown in accordance with one or more embodiments described herein. System 700 may represent a top view of a system based on a high bandwidth memory configuration. System 700 may include silicon interposer 705, compute die 710, compute die 715, compute die 720, compute die 725, and one or more 2.5D HBM stacks (e.g., HBM stack 730). As shown, compute die 710 may include one or more HBM PHYs (e.g., HBM PHY 735), one or more 3D HBM stacks (e.g., HBM stack 740, HBM stack 745), and at least one D2D interface (e.g., D2D interface 750, D2D interface 755). In some examples, silicon interposer 705 may be an example of the silicon interposer of system 600, compute die 710, compute die 715, compute die 720, and / or compute die 725 may be corresponding examples of compute die 605, HBM stack 730 may be an example of HBM stack 610, HBM PHY 735 may be an example of HBM PHY 620, and HBM stack 740 or HBM stack 745 may be an example of HBM stack 615. In some cases, silicon interposer 705 may be formed on a substrate.

[0104] In the illustrated example, compute die 710, compute die 715, compute die 720, and / or compute die 725 may be formed on silicon intermediary 705. In some examples, silicon intermediary 705 may connect compute die 710 to HBM PHY 735, connect HBM stack 730 to compute die 710, connect the base die of HBM stack 730 to compute die 710, connect HBM stack 740 to compute die 710, connect HBM stack 740 to an additional HBM stack (e.g., HBM stack 745) on the front surface of compute die 710, connect D2D interface 750 to compute die 710, and connect at least one compute die (e.g., compute die 710) to at least one other compute die (e.g., compute die 715, compute die 720, and / or compute die 725).

[0105] As shown, D2D interface 750 may connect compute die 710 to compute die 715. Additionally or alternatively, D2D interface 755 may connect compute die 720 to compute die 725, enhancing the capacity and bandwidth capabilities of system 700. In some cases, the D2D interface may connect compute die 710 to compute die 720, and / or the D2D interface may connect compute die 715 to compute die 725.

[0106] In the illustrated example, the compute die of system 700 may include any number of 3D HBM stacks (e.g., 1, 2, 4, 8, 16, 32 HBM memory die layers, etc.). Additionally, as shown, the compute die may include one or more 2.5D HBM stacks attached to the top edge, bottom edge, right edge, and / or left edge based on HBM PHY connections (e.g., HBM PHY 735). The numbers, configurations, arrangements, and connections are provided as examples and are not intended to limit in any way.

[0107] In some embodiments, the HBM stack 740 may include a stack of DRAMs connected to the HBM 3D PHY (e.g., HBM 3D PHY 450) via TSVs. The HBM stack 740 may be attached to the compute die 710 and communicate via one or more controllers (e.g., one or more microcontrollers, one or more memory controllers, and / or one or more HBM controllers). In some cases, the HBM stack 740 may communicate with any compute die of the system 700, with the 3D HBM stack of the compute die 710 and / or the 3D HBM stacks of other compute dies, with the 2.5D HBM stack of the system 700 (e.g., HBM stack 730). In some cases, the HBM stack 730 may communicate with any compute die of the system 700 (e.g., via the silicon interposer 705), with any 3D HBM stack of the system 700 (e.g., HBM stack 740), with any other 2.5D HBM stack of the system 700, etc.

[0108] In some embodiments, the silicon interposer 705 may be formed using silicon and / or other conductive materials and / or semiconductor materials, and may be used to implement a high-bandwidth memory configuration of the system 700. The silicon interposer 705 may provide a connection between one or more 2.5D HBM stacks and / or one or more 3D HBM stacks. In some examples, the silicon interposer 705 may be formed on a substrate. One or more compute dies and one or more 2.5D HBM stacks may be formed on the silicon interposer 705. One or more 3D HBM stacks may be formed on the compute dies of the system 700.

[0109] Figure 8Shows an example system 800 in accordance with one or more embodiments described herein. System 800 may represent a top view of a system based on a high bandwidth memory configuration. System 800 may include a silicon interposer 805, compute die 810, compute die 815, and one or more 2.5D HBM stacks (e.g., HBM stack 830). As shown, compute die 810 may include one or more HBM PHYs (e.g., HBM PHY 835), one or more 3D HBM stacks (e.g., HBM stack 820), at least one D2D interface (e.g., D2D interface 825), and at least one controller (e.g., controller 840). As shown, compute die 815 may include one or more HBM PHYs, one or more 3D HBM stacks, at least one D2D interface (e.g., D2D interface 825), and at least one controller (e.g., controller 845). In some examples, silicon interposer 805 may be an example of silicon interposer 705, compute die 810 and / or compute die 815 may be examples of compute die 710, compute die 715, compute die 720, and / or compute die 725, HBM stack 830 may be an example of HBM stack 730, HBM PHY 835 may be an example of HBM PHY 735, HBM stack 820 may be an example of HBM stack 740 or HBM stack 745, and D2D interface 825 may be an example of D2D interface 750 or D2D interface 755. As shown, D2D interface 825 may connect compute die 810 (and / or components of compute die 810) to compute die 815 (and / or components of compute die 815). In some cases, silicon interposer 805 may be formed on a substrate.

[0110] In some examples, controller 840 and / or controller 845 may include a microcontroller, a memory controller, and / or an HBM controller. In some cases, controller 840 and / or controller 845 may be referred to as the host of system 800. In some embodiments, controller 840 and / or controller 845 may be configured to coordinate and manage addressing, sending, and / or receiving memory commands (e.g., read, write, modify, release, garbage collection, etc.) associated with and / or in conjunction with compute die 810, compute die 815, one or more 2.5D HBM stacks, one or more HBM PHYs, one or more 3D HBM stacks, one or more 3D HBM PHYs of the 3D HBM stack, one or more D2D interfaces, and / or at least one controller of system 800.

[0111] In some examples, controller 840 and / or controller 845 may include one or more processing units (such as, by way of example, an ASIC, CPU, GPU, NPU, or TPU). In some cases, controller 840 and / or controller 845 may send instructions and / or data to the 3D HBM stack and / or 2.5D HBM stack of system 800. In some cases, controller 840 and / or controller 845 may prioritize bandwidth based on the utilization of the 2.5D HBM stack and / or 3D HBM stack of system 800.

[0112] In some cases, controller 840 and / or controller 845 may manage memory data operations based on the memory configuration in system 800, the amount of memory, and the location of the memory. In some embodiments, controller 840 and / or controller 845 may divide data operations among compute dies (such as between compute die 810 and compute die 815) based on the number of 2.5D HBM stacks in system 800, the number of 3D HBM stacks, the number of layers (such as memory die layers) in the 2.5D HBM stack, and the number of layers (such as memory die layers) in the 3D HBM stack. In some cases, to manage memory data operations, controller 840 and / or controller 845 may determine the number of compute dies, the number of HBM stacks per compute die, the number of memory die layers per HBM stack, and / or the number of memory die layers per compute die. Additionally or alternatively, to manage memory data operations, controller 840 and / or controller 845 may determine the amount of memory per compute die, the amount of memory in system 800, etc. In some cases, to manage memory data operations, controller 840 and / or controller 845 may determine the amount of 2.5D HBM memory per compute die, the amount of 2.5D HBM memory in system 800, the amount of 3D HBM memory per compute die, and the amount of 3D HBM memory in system 800.

[0113] Figure 9 A flowchart depicting an example method 900 associated with the disclosed system in accordance with example embodiments described herein is shown. In some configurations, method 900 may be based on semiconductor manufacturing processes implemented by semiconductor manufacturing hardware, firmware, and / or software (such as machine 105). In some configurations, method 900 may be implemented in conjunction with machine 105, components of machine 105, or any combination thereof. The depicted method 900 is merely one implementation, and one or more operations of method 900 may be rearranged, reordered, omitted, and / or otherwise modified such that other implementations are feasible and contemplated.

[0114] At 905, method 900 may include setting a first memory physical layer (PHY) interface on a surface of a compute die. For example, an HBM 3D PHY 450 may be set on a surface of compute die 415.

[0115] At 910, method 900 may include connecting a first memory to the first memory PHY interface of the compute die via a first through-silicon via (TSV) connection. For example, TSV 430 may connect a 3D HBM stack (e.g., HBM stack 420) to HBM 3D PHY 450.

[0116] At 915, method 900 may include connecting a second memory to a substrate die that is connected to the compute die via a silicon interposer. For example, an electrical connection (e.g., TSV, microbump, etc.) may connect a 2.5D HBM stack (e.g., HBM stack 405) to substrate die 410.

[0117] At 920, method 900 may include setting the compute die on the silicon interposer. For example, compute die 415 may be set on silicon interposer 435. In some cases, an electrical connection (e.g., TSV, microbump, etc.) may connect compute die 415 to silicon interposer 435.

[0118] At 925, method 900 may include setting the substrate die (e.g., adjacent to the compute die) on the silicon interposer. For example, substrate die 410 may be set on silicon interposer 435 adjacent to compute die 415.

[0119] Figure 10 A flowchart depicting an example method 1000 associated with the disclosed system in accordance with example embodiments described herein is shown. In some configurations, method 1000 may be based on a semiconductor manufacturing process implemented by semiconductor manufacturing hardware, firmware, and / or software (e.g., machine 105). In some configurations, method 1000 may be implemented in conjunction with machine 105, components of machine 105, or any combination thereof. The depicted method 1000 is merely one embodiment, and one or more operations of method 1000 may be rearranged, reordered, omitted, and / or otherwise modified such that other embodiments are feasible and contemplated.

[0120] At 1005, method 1000 may include setting a first memory physical layer (PHY) interface on a surface of a compute die. For example, an HBM 3D PHY 450 may be set on a surface of compute die 415.

[0121] At 1010, method 1000 may include connecting a first memory to a first memory PHY interface of a compute die via a first through-silicon via (TSV) connection. For example, TSV 430 may connect a 3D HBM stack (e.g., HBM stack 420) to HBM 3D PHY 450.

[0122] At 1015, method 1000 may include connecting a second memory to a substrate die that is connected to the compute die via a silicon interposer. For example, electrical connections (e.g., TSVs, microbumps, etc.) may connect a 2.5D HBM stack (e.g., HBM stack 405) to substrate die 410.

[0123] At 1020, method 1000 may include placing the compute die on the silicon interposer. For example, compute die 415 may be placed on silicon interposer 435. In some cases, electrical connections (e.g., TSVs, microbumps, etc.) may connect compute die 415 to silicon interposer 435.

[0124] At 1025, method 1000 may include placing the substrate die on the silicon interposer. For example, substrate die 410 may be placed on silicon interposer 435 adjacent to compute die 415.

[0125] At 1030, method 1000 may include connecting a memory communication interface of the compute die to a memory communication interface of the substrate die. For example, the memory communication interface of compute die 415 is connected to the memory communication interface of substrate die 410 via silicon interposer 435. For example, HBM PHY 445 and HBM PHY 440 connect compute die 415 to substrate die 410 via silicon interposer 435. Optionally, D2D interface 545 and D2D interface 540 connect compute die 415 to substrate die 410 via silicon interposer 435.

[0126] In the examples described herein, the configurations and operations are example configurations and operations and may involve various additional configurations and operations not explicitly shown. In some examples, one or more aspects of the illustrated configurations and / or operations may be omitted. In some embodiments, one or more of the operations may be performed by components other than those shown herein. Additionally or optionally, the sequence and / or temporal order of the operations may be changed.

[0127] Certain embodiments may be implemented in hardware, firmware, and / or software. Other embodiments may be implemented as instructions stored on a computer-readable storage device that can be read and executed by at least one processor to perform the operations described herein. A computer-readable storage device may include any non-transitory memory mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a computer-readable storage device may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, and other storage devices and media.

[0128] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The terms "computing device", "user device", "communication station", "station", "handheld device", "mobile device", "wireless device", and "user equipment (UE)" as used herein refer to a wireless communication device (such as, a cellular phone, smart phone, tablet computer, netbook, wireless terminal, laptop computer, femtocell, high data rate (HDR) user station, access point, printer, point-of-sale device, access terminal, or other personal communication system (PCS) device). The device may be mobile or stationary.

[0129] As used within this document, the term "communicate" is intended to include sending, or receiving, or both sending and receiving. This can be particularly useful in the claims when describing the organization of data sent by one device and received by another device, but only the functionality of one of these devices is required to infringe the claim. Similarly, when only the functionality of one of those devices is claimed, a two-way data exchange between two devices (where both devices send and receive during the exchange) can be described as "communicating". The term "communicating" as used herein with respect to wireless communication signals includes sending wireless communication signals and / or receiving wireless communication signals. For example, a wireless communication unit capable of communicating wireless communication signals may include a wireless transmitter for sending wireless communication signals to at least one other wireless communication unit and / or a wireless communication receiver for receiving wireless communication signals from at least one other wireless communication unit.

[0130] Some embodiments may be used in conjunction with various devices and systems, such as personal computers (PCs), desktop computers, mobile computers, laptop computers, notebook computers, tablet computers, server computers, handheld computers, handheld devices, personal digital assistant (PDA) devices, handheld PDA devices, in-vehicle devices, non-vehicle devices, hybrid devices, vehicle devices, non-vehicle devices, mobile or portable devices, consumer devices, non-mobile or non-portable devices, wireless communication stations, wireless access points (APs), wired or wireless routers, wired or wireless modems, video devices, audio devices, audio-video (A / V) devices, wired or wireless networks, wireless local area networks, wireless video area networks (WVANs), local area networks (LANs), wireless LANs (WLANs), personal area networks (PANs), wireless PANs (WPANs), etc.

[0131] Some embodiments may be used in conjunction with the following devices: one-way and / or two-way radio communication systems, cellular wireless telephone communication systems, mobile phones, cellular phones, wireless phones, personal communication system (PCS) devices, PDA devices including wireless communication devices, mobile or portable global positioning system (GPS) devices, devices including GPS receivers or transceivers or chips, devices including RFID elements or chips, multiple-input multiple-output (MIMO) transceivers or devices, multiple-input single-output (MISO) transceivers or devices, devices having one or more internal antennas and / or external antennas, digital video broadcast (DVB) devices or systems, multi-standard radio devices or systems, wired or wireless handheld devices (such as smart phones), wireless application protocol (WAP) devices, etc.

[0132] Some embodiments may be used in conjunction with one or more wireless communication protocols, such as radio frequency (RF), infrared (IR), frequency division multiplexing (FDM), orthogonal FDM (OFDM), time division multiplexing (TDM), time division multiple access (TDMA), extended TDMA (E-TDMA), general packet radio service (GPRS), extended GPRS, code division multiple access (CDMA), wideband CDMA (WCDMA), CDMA 2000, single-carrier CDMA, multi-carrier CDMA, multi-carrier modulation (MDM), discrete multi-tone (DMT), Bluetooth TM , Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee TMin combination with one or more types of wireless communication signals and / or systems such as Ultra-Wideband (UWB), Global System for Mobile Communications (GSM), 2G, 2.5G, 3G, 3.5G, 4G, Fifth Generation (5G) mobile networks, 3GPP, Long Term Evolution (LTE), Advanced LTE, Enhanced Data Rates for GSM Evolution (EDGE), etc. Other embodiments may be used in a variety of other devices, systems, and / or networks.

[0133] Although example processing systems have been described above, embodiments of the subject matter and functional operations described herein may be implemented in other types of digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them.

[0134] Embodiments of the subject matter and operations described herein may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. Embodiments of the subject matter described herein may be implemented as one or more computer programs (i.e., one or more components of computer program instructions), the one or more computer programs being encoded on a computer storage medium for execution by, or to control the operation of, an information / data processing apparatus. Optionally or additionally, the program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) that is generated to encode the information / data for transmission to a suitable receiver device for execution by the information / data processing apparatus. A computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them, or be included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Further, although a computer storage medium is not a propagated signal, a computer storage medium may be the source or destination of computer program instructions encoded in an artificially generated propagated signal. A computer storage medium may also be one or more separate physical components or media (such as multiple CDs, disks, or other storage devices), or be included in one or more separate physical components or media (such as multiple CDs, disks, or other storage devices).

[0135] The operations described herein may be implemented as operations performed by an information / data processing apparatus on information / data stored on one or more computer-readable storage devices or received from other sources.

[0136] The term "data processing apparatus" encompasses all kinds of devices, apparatuses and machines for processing data, including, for example, programmable processors, computers, system-on-chips, or multiple or combinations of the foregoing. The apparatus may include dedicated logic circuitry (e.g., FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits)). In addition to hardware, the apparatus may also include code that creates an execution environment for the computer programs being discussed (e.g., code that constitutes processor firmware, protocol stacks, database management systems, operating systems, cross-platform execution-time environments, virtual machines, or combinations of one or more of them). The apparatus and the execution environment may implement various different computing model infrastructures (such as, network services, distributed computing, and grid computing infrastructures).

[0137] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language (including compiled or interpreted languages, declarative or procedural languages), and can be deployed in any form (including as a stand-alone program or as a component, component, subroutine, object, or other unit suitable for a computing environment). A computer program may correspond to a file in a file system, but does not have to correspond to a file in a file system. The program may be stored as part of a file that holds other programs or information / data (e.g., one or more scripts stored in a markup language document), stored in a single file dedicated to the program being discussed, or stored in multiple coordinated files (e.g., files that store one or more components, subroutines, or portions of code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0138] The processes and logical flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input information / data and generating output. As an example, processors suitable for executing computer programs include both general and special purpose microprocessors, as well as any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and information / data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing actions in accordance with instructions and one or more memory devices for storing the instructions and data. Generally, a computer will also include one or more mass storage devices for storing data (e.g., magnetic disks, magneto-optical disks, or optical disks), or be operatively coupled to receive information / data from one or more mass storage devices or transfer information / data to one or more mass storage devices or both. However, a computer need not have such devices. Devices suitable for storing computer program instructions and information / data include all forms of non-volatile memory, media, and memory devices (including, by way of example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disks; and CD-ROM and DVD-ROM disks). The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0139] To provide for interaction with a user, embodiments of the subject matter described herein can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information / data to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic, speech, or tactile input). In addition, a computer can interact with a user by sending documents to and receiving documents from the device used by the user; for example, by sending a web page to a web browser on a client device of the user in response to a request received from the web browser.

[0140] Embodiments of the subject matter described herein can be implemented in a computing system that includes a backend component (e.g., as an information / data server), or includes a middleware component (e.g., an application server), or includes a frontend component (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with embodiments of the subject matter described herein), or any combination of one or more such backend, middleware, or frontend components. The components of the system can be interconnected by any form or medium of digital information / data communication (e.g., a communication network). Examples of communication networks include local area networks (“LANs”) and wide area networks (“WANs”), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0141] The computing system can include clients and servers. The clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, the server sends information / data (e.g., an HTML page) to the client device (e.g., for the purpose of displaying information / data to a user interacting with the client device once receiving user input from the user interacting with the client device). Information / data generated at the client device (e.g., the result of a user interaction) can be received at the server from the client device.

[0142] Although this specification contains many specific implementation details, these should not be construed as limitations on the scope of any embodiment or of what may be claimed, but rather as descriptions of features specific to particular embodiments. The particular features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment can also be implemented separately or in any suitable sub-combination in multiple embodiments. Moreover, although the features may be described above as acting in a particular combination and even initially claimed as such, in some cases one or more features from a claimed combination can be deleted from the combination, and the claimed combination can relate to a sub-combination or a variant of a sub-combination.

[0143] Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Additionally, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0144] Accordingly, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the acts recited in the claims can be performed in a different order and still achieve the desired result. Additionally, the processes depicted in the figures need not be in the particular order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing may be advantageous.

[0145] Benefiting from the foregoing description and the teachings presented in the associated drawings, those skilled in the art to which these embodiments pertain will envision many modifications and other examples of the embodiments described herein. Accordingly, it is to be understood that the embodiments are not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method for configuring a memory, the method comprising: Disposing a first memory physical layer interface on a surface of a computing die; connecting the first memory to a first memory physical layer interface of the compute die via a first through silicon via connection; connecting a second memory to a base die, the base die being connected to the computing die via a silicon interposer; The compute die and the substrate die are disposed on a silicon interposer.

2. The method according to claim 1, wherein: The first memory includes a first memory die stacked on a first memory physical layer interface and a second memory die stacked on the first memory die.

3. The method according to claim 2, wherein: A first memory die is connected to a first memory physical layer interface via a first through silicon via connection, and The second memory die is connected to the first memory die via a first through silicon via connection.

4. The method according to claim 1, wherein: The second memory includes a third memory die stacked on the base die and a fourth memory die stacked on the third memory die.

5. The method according to claim 4, wherein: A third memory die is connected to the base die via a second through silicon via connection, and The fourth memory die is connected to the third memory die via a second through silicon via connection.

6. The method according to claim 1, wherein: The computing die includes a second memory physical layer interface of the computing die, A first memory physical layer interface is disposed on an inner surface of the computing die, and The second memory physical layer interface is disposed on a side of the compute die.

7. The method according to claim 1, wherein: The compute die includes a first die-to-die interface disposed on a side of the compute die.

8. The method according to claim 7, wherein: The compute die is connected to a second compute die via a first die-to-die interface of the compute die and a silicon intermediate.

9. The method according to claim 7, wherein: The base die includes a memory physical layer interface of the base die or a die-to-die interface of the base die.

10. The method according to any one of claims 1 to 9, wherein: The second memory or the first memory includes at least one of a high bandwidth memory, a static random access memory, a dynamic random access memory, and a flash memory.

11. The method according to any one of claims 1 to 9, wherein: Compute dies include graphics processor dies.

12. A memory package, comprising: A first memory physical layer interface is disposed on a surface of the computing die; a first memory connected to a first memory physical layer interface of the compute die via a first through silicon via connection; a base die combined with the computing die and disposed on the silicon intermediate, wherein the computing die is disposed on the silicon intermediate and connected to the base die via the silicon intermediate; as well as A second memory is connected to the base die.

13. The memory package according to claim 12, wherein: The first memory includes a first memory die stacked on a first memory physical layer interface and a second memory die stacked on the first memory die.

14. The memory package according to claim 13, wherein: A first memory die is connected to a first memory physical layer interface via a first through silicon via connection, and The second memory die is connected to the first memory die via a first through silicon via connection.

15. The memory package according to claim 12, wherein: The second memory includes a third memory die stacked on the base die and a fourth memory die stacked on the third memory die.

16. The memory package according to claim 15, wherein: A third memory die is connected to the base die via a second through silicon via connection, and The fourth memory die is connected to the third memory die via a second through silicon via connection.

17. The memory package according to any one of claims 12 to 16, wherein: The computing die includes a second memory physical layer interface of the computing die, A first memory physical layer interface is disposed on an inner surface of the computing die, and The second memory physical layer interface is disposed on a side of the compute die.

18. A system on chip, comprising: a computing die, mounted on a silicon interposer; a base die, combined with the computing die and disposed on the silicon intermediate; A first memory physical layer interface is disposed on a surface of the computing die; a first memory connected to a first memory physical layer interface of the compute die via a first through silicon via connection; as well as A second memory is connected to the base die via a second through silicon via connection.

19. The system on chip according to claim 18, wherein: The first memory includes a first memory die stacked on a first memory physical layer interface and a second memory die stacked on the first memory die.

20. The system on chip according to claim 19, wherein: A first memory die is connected to a first memory physical layer interface via a first through silicon via connection, and The second memory die is connected to the first memory die via a first through silicon via connection.

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