Ultrathin 2.5 D chip packaging method based on silicon interposer

Abstract

The invention discloses an ultrathin 2.5 D chip packaging method based on a silicon intermediary board, which comprises the following steps: providing the silicon intermediary board which is provided with a silicon through hole communicated with the front surface of the silicon intermediary board, a first circuit layer arranged on the front surface of the silicon intermediary board and a plurality of front surface micro salient points; welding a plurality of chips on the front micro convex points and communicating the front micro convex points; performing injection molding of insulating glue on the front surface of the silicon interposer to form a packaging body in which the chip is completely packaged; thinning the back surface of the silicon interposer to expose the TSV, and manufacturing a second circuit layer electrically communicated with the TSV on the back surface of the thinned silicon interposer; manufacturing a plurality of back bumps on the second circuit layer by using a bump manufacturing technology so as to manufacture an ultrathin silicon interposer; carrying out de-bonding on the packaging body and the temporary support plate; the thinned package is distal from an upper surface of the ultra-thin silicon interposer. The process flow is simple, the dielectric plate in silicon can be reduced to be very thin, and the yield is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to an ultra-thin 2.5D chip package based on a silicon interposer. Background Art

[0002] The 2.5D process in the field of semiconductor manufacturing refers to a manufacturing method between traditional 2D planar processes and 3D stacking technologies. It integrates multiple chips or different functional circuit layers (such as logic, memory, etc.) side by side on the same substrate and uses technologies such as Through-Silicon Via (TSV) to achieve vertical interconnection, thereby improving integration, performance, and power consumption efficiency. The main advantage of the 2.5D process is the ability to achieve high-bandwidth, low-latency data transmission while maintaining relatively low cost and complexity compared to full 3D integration. The concept of 2.5D packaging first emerged in the mid-2000s. With the growing demand for higher integration, faster speed, and lower power consumption, the industry began to explore how to go beyond traditional monolithic integration methods.

[0003] After entering 2010, with the maturity of the Through-Silicon Via (TSV) technology, significant progress has been made in 2.5D packaging technology. TSV allows signals to be directly connected through the silicon wafer, greatly improving the data transmission speed and efficiency between chips. In recent years, 2.5D packaging technology has been widely used in high-performance computing, data centers, graphics processing, and other fields. For example, AMD has adopted 2.5D packaging technology in its Radeon Instinct series of accelerator cards, integrating the GPU with High Bandwidth Memory (HBM) to achieve extremely high memory bandwidth. Currently, the industry is still continuously researching and developing new 2.5D packaging technologies to further improve integration, reduce costs, and improve heat dissipation performance, etc. For example, using thinner and more advanced silicon interposer technology to support more I / O counts and higher signal integrity.

[0004] Currently, in domestic 2.5D applications, OSAT (Outsourced Semiconductor Assembly and Test) uses a process flow of first thinning a 100um TSV silicon interposer and then soldering the chips. Due to the relatively large CTE (Coefficient of Thermal Expansion) and stress problems in the process of soldering the chips later, it restricts the product's need to use thinner silicon interposers (50um TSV), improve the signal transmission speed, increase the bandwidth, and achieve smaller device size. Currently, the process flow of first thinning the silicon interposer and then soldering the chips generally has the following problems: 1. Complicated process: The process of fabricating a thinned silicon interposer requires two temporary bonding steps. Meanwhile, the injection molding process is complex, and after injection molding, it is necessary to perform another circumferential cutting to expose the sidewalls of the wafer to facilitate subsequent debonding steps.

[0005] 2. Yield loss: In the process flow of first thinning a 50 - um TSV silicon interposer and then soldering chips, since the silicon interposer has been thinned to less than 50 um, which belongs to an ultra - thin process, during the chip flip - chip soldering process, the silicon interposer is prone to fragment under pressure.

[0006] 3. Cost increase: In the process flow of first thinning the silicon interposer and then soldering chips, the silicon interposer needs to be fabricated with two - sided processes, which requires two temporary bonding steps, significantly increasing the cost.

[0007] 4. Impact on reliability: Since the silicon interposer is first thinned to less than 50 um, the warpage and stress of the entire chip are relatively large, posing great challenges to subsequent process flows. Especially during the chip flip - chip soldering process, the quality and stability of solder joints are greatly challenged, and it will also affect the chip reliability.

[0008] Therefore, there is an urgent need for an ultra - thin 2.5D chip packaging method based on a silicon interposer that can solve the above problems. Summary of the Invention

[0009] The object of the present invention is to provide an ultra - thin 2.5D chip packaging method based on a silicon interposer, with a simple process flow, which can make the silicon interposer very thin and has a high yield.

[0010] To achieve the above object, the present invention provides an ultra - thin 2.5D chip packaging method based on a silicon interposer, including: providing a silicon interposer, the silicon interposer having silicon vias connecting the front side of the silicon interposer, a first circuit layer disposed on the front side of the silicon interposer, and a plurality of front micro - bumps formed on the first circuit layer; soldering a plurality of chips to be soldered on the front micro - bumps and electrically connecting the chips to the front micro - bumps; injecting an insulating adhesive on the front side of the silicon interposer to form a package body encapsulating the chips therein, the upper surface of the package body being higher than the upper surface of the chips with respect to the front side of the silicon interposer so that the package body wraps the upper surface of the chips; temporarily bonding the upper surface of the package body away from the silicon interposer to a temporary carrier; thinning the back side of the silicon interposer to expose the silicon vias, and fabricating a second circuit layer on the thinned back side of the silicon interposer that is electrically connected to the silicon vias; using a bump manufacturing technique to fabricate a plurality of back bumps on the second circuit layer to form an ultra - thin silicon interposer; debonding the package body from the temporary carrier; thinning the upper surface of the package body away from the ultra - thin silicon interposer.

[0011] Preferably, providing a silicon interposer specifically includes: providing a silicon interposer to be processed, where the silicon interposer to be processed has silicon vias communicating with the front side of the silicon interposer and a first circuit layer disposed on the front side of the silicon interposer, and using a bump manufacturing technique to form a plurality of front micro-bumps on the first circuit layer on the front side of the silicon interposer to fabricate the silicon interposer.

[0012] Preferably, the multiple chips to be welded are welded to the first circuit layer on the front side of the silicon interposer by using a thermocompression bonding method. Of course, the specific method of welding the chips to the silicon interposer is not limited to thermocompression bonding.

[0013] Preferably, injecting an insulating glue on the front side of the silicon interposer to form a package body encapsulating the chips therein specifically includes: filling an insulating glue between the front side of the silicon interposer and the bottom of the chips and removing air bubbles and curing to form a first protective layer, filling an insulating glue on the first protective layer to form a second protective layer wrapping the chips, and then curing the second protective layer to form the package body in one step.

[0014] Preferably, the cross-sectional area of the insulating glue injection is smaller than the cross-sectional area of the silicon interposer, and a spacing is provided between the edge of the package body and the edge of the silicon interposer so that the side surface of the silicon interposer is exposed outside the package body. This solution eliminates the need for subsequent circumcision and effectively reduces the waste of the injected insulating glue.

[0015] Specifically, the difference between the edge of the insulating glue injection and the edge of the silicon interposer is 0.5 - 3.5 mm.

[0016] Specifically, the silicon interposer is wafer-level circular, and the injection diameter of the insulating glue is smaller than the diameter of the silicon interposer.

[0017] Preferably, the upper surface of the package body away from the silicon interposer is temporarily bonded to a temporary carrier through a temporary bonding glue layer, and the thickness of the temporary bonding glue layer is 10 - 60 μm.

[0018] Preferably, fabricating a second circuit layer on the back side of the thinned silicon interposer that is electrically connected to the silicon vias specifically includes: using silicon etching, chemical vapor deposition, and copper leakage processes to fabricate the second circuit layer on the back side of the silicon interposer that is electrically connected to the silicon vias.

[0019] Preferably, the thickness of the ultra-thin silicon interposer is less than or equal to 50 μm.

[0020] Preferably, the ultra-thin silicon interposer is subjected to a reflow process to form back solder balls on the back side. The structure of the back solder balls facilitates subsequent substrate welding and has a closer connection with the second circuit layer.

[0021] Preferably, when thinning the upper surface of the package away from the silicon interposer, the upper surfaces of all the chips are exposed and flush, so that the tops of all the chips are at the same height, facilitating heat dissipation.

[0022] Preferably, after thinning one side of the package away from the ultra-thin silicon interposer, the method further includes the steps of: cutting the package and the ultra-thin silicon interposer to form a plurality of chip particles, and each chip particle contains a plurality of different types of chips.

[0023] Compared with the prior art, the present invention adopts a process flow of first soldering the chips and then thinning the silicon interposer, which only requires one temporary bonding process, and the process is simple. Moreover, since the chip mounting and the encapsulation injection molding of the package are carried out first, the chip and the silicon interposer form an integral body. When the silicon interposer is thinned later, the interposer can be thinned to a very thin thickness without fragmentation, greatly improving the product yield. On the other hand, when the chips are soldered in the present invention, the silicon interposer is not thinned, so the warping and stress of the silicon interposer have little influence, and the solder joint quality during chip soldering is high and the stability is good. On the other hand, when the package is encapsulated in the present invention, the package wraps the front surface of the chip, and then the upper surface of the package is temporarily bonded and then the middle interposer is thinned. After the temporary bonding between the package and the carrier plate is released after thinning, the package is thinned from the upper surface of the package, so that the chip will not be damaged during debonding, and the chip surface is avoided from being contaminated by the bonding adhesive, which can improve the product yield. On yet another hand, when the silicon interposer is thinned in the present invention, the package of the chip is temporarily bonded to the temporary carrier plate. Since the upper surface of the package is flat, the temporary bonding adhesive can be set very thin during temporary bonding. Description of the Drawings

[0024] Figure 1 is a flowchart of the first part of the ultra-thin 2.5D chip packaging method based on a silicon interposer according to the present invention.

[0025] Figure 2 is a flowchart of the second part of the ultra-thin 2.5D chip packaging method based on a silicon interposer according to the present invention.

[0026] Figure 3 is a flowchart of the third part of the ultra-thin 2.5D chip packaging method based on a silicon interposer according to the present invention.

[0027] Figure 4 is a flowchart of the fourth part of the ultra-thin 2.5D chip packaging method based on a silicon interposer according to the present invention.

[0028] Figure 5 is a flowchart of the fourth part of the ultra-thin 2.5D chip packaging method based on a silicon interposer according to the present invention.

[0029] Figure 6 is a flowchart of step S3 in a preferred embodiment of the present invention. Detailed implementation manners

[0030] To describe in detail the technical content, structural features, achieved objectives and effects of the present invention, the following will be described in detail in conjunction with the implementation manners and with reference to the accompanying drawings.

[0031] Refer to Figures 1 to 4 , the present invention discloses a method for ultra-thin 2.5D chip packaging based on a silicon interposer, including steps S1 to S8.

[0032] S1, refer to Figure 1 , provide a silicon interposer 10, the silicon interposer 10 having silicon vias 11 communicating with the front surface of the silicon interposer 10, a first wiring layer 12 disposed on the front surface of the silicon interposer 10, and a plurality of front microbumps 13 formed on the first wiring layer 12.

[0033] Specifically, step S1 includes: providing a silicon interposer 10 to be processed, the silicon interposer 10 to be processed having silicon vias 11 (formed by TSV technology) communicating with the front surface of the silicon interposer 10, a first wiring layer 12 disposed on the front surface of the silicon interposer 10, and using a bump manufacturing technology to form a plurality of front microbumps 13 on the first wiring layer 12 on the front surface of the silicon interposer 10 to fabricate the silicon interposer 10.

[0034] Specifically, using a bump manufacturing technology (bumping process) to form a plurality of front microbumps 13 on the first wiring layer 12 on the front surface of the silicon interposer 10 specifically includes: forming an electroplating seed layer on the first wiring layer 12 on the front surface of the silicon interposer 10 by a sputtering process; photolithographing the electroplating seed layer to form a bump pattern; electroplating on the bump pattern to form front microbumps 13; removing the photoresist and the excess electroplating seed layer. Preferably, after removing the electroplating seed layer, a defect inspection is also performed to exclude defective silicon interposers.

[0035] S2, refer to Figure 1 , weld a plurality of chips 20 to be welded on the front microbumps 13, and electrically connect the chips 20 to the front microbumps 13.

[0036] Specifically, use a thermal compression bonding (TCB) method to weld the plurality of chips 20 to be welded on the microbumps 13 on the front surface of the silicon interposer 10. Of course, the specific method of welding the chips 20 to the silicon interposer 10 is not limited to thermal compression bonding.

[0037] S3, refer to Figure 1, an insulating adhesive is injection-molded on the front surface of the silicon interposer 10 to form a package body 30 encapsulating the chip 20 therein. The upper surface of the package body 30 is higher than the upper surface of the chip 20 with respect to the front surface of the silicon interposer 10 so that the package body 30 wraps the upper surface of the chip 20.

[0038] Preferably, referring to Figure 6 , injection-molding an insulating adhesive on the front surface of the silicon interposer 10 to form a package body 30 encapsulating the chip 20 therein specifically includes: filling an insulating adhesive between the front surface of the silicon interposer 10 and the bottom of the chip 20 and degassing and curing it to form a first protective layer 31, filling an insulating adhesive on the first protective layer 31 to form a second protective layer 32 wrapping the chip 20, and then curing the second protective layer 32 to form the package body 30 in one step. Among them, the first protective layer 31 is filled in the gaps of the front microbumps 13 between the chip 20 and the front surface of the silicon interposer 10.

[0039] Preferably, the cross-sectional area of the injection-molded insulating adhesive is smaller than the cross-sectional area of the silicon interposer 10, and a spacing is provided between the edge of the package body 30 and the edge of the silicon interposer 10 so that the side surface of the silicon interposer 10 is exposed outside the package body 30. This solution eliminates the need for subsequent circumferential cutting and effectively reduces the waste of the injection-molded insulating adhesive. Specifically, the difference between the edge of the injection-molded insulating adhesive and the edge of the silicon interposer 10 is 0.5 - 3.5 mm.

[0040] Specifically, the silicon interposer 10 is wafer-level circular, and the injection diameter of the insulating adhesive is smaller than the diameter of the silicon interposer 10. The diameter of the package body 30 is smaller than the diameter of the silicon interposer 10. In this embodiment, the filling diameter is 293 mm - 299 mm, and the diameter of the silicon interposer 10 is 300 mm.

[0041] Among them, the insulating adhesive is a black plastic encapsulation adhesive, so that the package body 30 is a black package body, which can prevent laser from passing through and is convenient for protecting the chip 20 during subsequent debonding.

[0042] S4, referring to Figure 2 , the upper surface of the package body 30 away from the silicon interposer 10 is temporarily bonded to a temporary carrier 40. Among them, the temporary carrier 40 is a light-transmitting plate, such as a glass carrier, etc.

[0043] Specifically, the upper surface of the package body 30 away from the silicon interposer 10 is temporarily bonded to the temporary carrier 40 through a temporary bonding adhesive layer, and the thickness of the temporary bonding adhesive layer is 10 - 60 μm.

[0044] S5, perform the TSV back thinning through-hole process on the back surface of the silicon interposer 10.

[0045] Specifically, referring toFigure 2 In S5-(a), the back surface of the silicon interposer 10 is thinned to expose the silicon vias 11, refer to Figure 3 In S5-(b), a second wiring layer 14 electrically connected to the silicon vias 11 is formed on the back surface of the thinned silicon interposer 10a. Among them, the hole walls of the silicon vias 11 are provided with a metal material for conducting electricity.

[0046] Among them, Si grinding (grinding wheel grinding and thinning) or CMP (chemical mechanical polishing) is used to thin the back surface of the silicon interposer 10 to expose the silicon vias 11.

[0047] Step S5 specifically includes: using silicon etching (Silicon recess etch), chemical vapor deposition, and cuprotrusion processes to form a second wiring layer 14 electrically connected to the silicon vias 11 on the back surface of the thinned silicon interposer 10a.

[0048] S6, refer to Figure 3 , and a plurality of back bumps 15 are formed on the second wiring layer 14 by using a bumping technology (bumping process) to form an ultra-thin silicon interposer 10b.

[0049] Step S6 specifically includes: forming an electroplating seed layer on the back surface of the thinned silicon interposer 10a through a sputtering process; lithographing the electroplating seed layer to form a lithography pattern; performing electroplating on the lithography pattern to form back bumps 15; removing the photoresist and the excess electroplating seed layer. In this embodiment, the photoresist and the excess electroplating seed layer are removed through Strip (photoresist stripping) process and Wet Etch (wet etching) process. The back bumps 15 are higher than the front micro bumps 13. In this embodiment, the height of the back bumps is 80-100 μm.

[0050] Preferably, refer to Figure 4 In S6-(a) of, after step S6, the ultra-thin silicon interposer 10b is processed by reflow to make the back bumps 15 form back solder balls 15a.

[0051] S7, refer to Figure 4 , and the package body 30 is debonded from the temporary carrier 40.

[0052] Among them, the debonding in this embodiment can be a laser or ultraviolet light irradiation dissociation method, that is, laser or ultraviolet light irradiation is applied to one side of the temporary carrier 40 after bonding, and the temporary bonding adhesive layer 41 on the temporary carrier 40 loses its adhesiveness due to chemical decomposition under this laser or ultraviolet light irradiation, so as to dissociate the package body 30 from the temporary carrier 40.

[0053] S8, refer to Figure 4, thinning the upper surface of the package body 30 away from the ultra-thin silicon interposer 10b.

[0054] Among them, when thinning the upper surface of the package body 30 away from the ultra-thin silicon interposer 10b, the upper surfaces of all the chips 20 are exposed and flush.

[0055] Preferably, referring to Figure 5 , it further includes step S9 of cutting the package body 30 and the ultra-thin silicon interposer 10b to form a plurality of chip particles 100, and each chip particle 100 has a plurality of different types of chips 20. Among them, after step S9, processes such as marking will also be included.

[0056] The above-disclosed are only the preferred embodiments of the present invention. Of course, the scope of the rights of the present invention cannot be limited by this. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope covered by the present invention.

Claims

1. An ultra-thin 2.5D chip packaging method based on a silicon interposer, characterized in that: Including: Providing a silicon interposer, the silicon interposer having silicon vias communicating with the front surface of the silicon interposer, a first circuit layer disposed on the front surface of the silicon interposer, and a plurality of front microbumps formed on the first circuit layer; Welding a plurality of chips to be welded on the front microbumps and electrically connecting the chips to the front microbumps; Injecting an insulating glue on the front surface of the silicon interposer to form a package body encapsulating the chips therein, the upper surface of the package body being higher than the upper surface of the chips relative to the front surface of the silicon interposer so that the package body wraps the upper surface of the chips; Temporarily bonding the upper surface of the package body away from the silicon interposer to a temporary carrier; Thinning the back surface of the silicon interposer to expose the silicon vias and fabricating a second circuit layer on the thinned back surface of the silicon interposer that is electrically connected to the silicon vias; Fabricating a plurality of back bumps on the second circuit layer using a bump manufacturing technique to fabricate an ultra-thin silicon interposer; Debonding the package body from the temporary carrier; Thinning the upper surface of the package body away from the ultra-thin silicon interposer.

2. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 1, characterized in that: Providing the silicon interposer specifically includes: providing a silicon interposer to be processed, the silicon interposer to be processed having silicon vias communicating with the front surface of the silicon interposer, a first circuit layer disposed on the front surface of the silicon interposer, and using a bump manufacturing technique to form a plurality of front microbumps on the first circuit layer on the front surface of the silicon interposer to fabricate the silicon interposer.

3. The ultra-thin 2.5D chip packaging method based on a silicon interposer as claimed in claim 1, wherein: Welding the plurality of chips to be welded on the first circuit layer on the front surface of the silicon interposer by means of thermocompression bonding.

4. The ultra-thin 2.5D chip packaging method based on a silicon interposer as claimed in claim 1, wherein: Injecting an insulating glue on the front surface of the silicon interposer to form a package body encapsulating the chips therein specifically includes: Filling an insulating glue between the front surface of the silicon interposer and the bottom of the chips and degassing and curing to form a first protective layer, filling an insulating glue on the first protective layer to form a second protective layer wrapping the chips, and then curing the second protective layer to form the package body in one step.

5. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 1, wherein: The cross-sectional area of the insulating glue injection is smaller than the cross-sectional area of the silicon interposer, and there is a spacing between the edge of the package body and the edge of the silicon interposer so that the side surface of the silicon interposer is exposed outside the package body.

6. The ultra-thin 2.5D chip packaging method based on a silicon interposer as claimed in claim 5, wherein: The difference between the edge of the insulating glue injection and the edge of the silicon interposer is 0.5 - 3.5 mm.

7. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 5, wherein: The silicon interposer is wafer-level circular, and the injection diameter of the insulating glue is smaller than the diameter of the silicon interposer.

8. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 1, wherein: Temporarily bonding the upper surface of the package body away from the silicon interposer to a temporary carrier through a temporary bonding glue layer, and the thickness of the temporary bonding glue layer is 10 - 60 μm.

9. The ultra-thin 2.5D chip packaging method based on a silicon interposer as claimed in claim 1, wherein: Fabricating a second circuit layer on the thinned back surface of the silicon interposer that is electrically connected to the silicon vias specifically includes: using silicon etching, chemical vapor deposition, and copper leakage processes to fabricate a second circuit layer on the thinned back surface of the silicon interposer that is electrically connected to the silicon vias.

10. The ultra-thin 2.5D chip packaging method based on a silicon interposer as described in claim 1, wherein: The thickness of the ultra-thin silicon interposer is less than or equal to 50 μm.

11. The ultra-thin 2.5D chip packaging method based on a silicon interposer as described in claim 1, characterized in that: Subjecting the ultra-thin silicon interposer to a reflow process to form back solder balls on the back bumps.

12. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 1, characterized in that: When thinning the upper surface of the package body away from the ultra-thin silicon interposer, the upper surfaces of all the chips are exposed and flush.

13. The ultra-thin 2.5D chip packaging method based on a silicon interposer according to claim 1, characterized in that: After thinning the side of the package away from the ultra-thin silicon interposer, the method further includes the steps of: cutting the package and the ultra-thin silicon interposer to form a plurality of chiplets, each of the chiplets having a plurality of different types of chips.

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