Single-layer full-connection memory storage circuit and method based on nanometer memristor array

Abstract

The invention provides a single-layer full-connection memory storage circuit and method based on a nanometer memristor array, and relates to the technical field of memristor memory circuits. The circuit comprises an information input circuit, an information memory circuit and an information storage circuit which are connected in sequence, the information memory circuit comprises a plurality of groups of digital-to-analog converters (DAC) and a memristive cross array which are connected with one another, and the memristive cross array comprises a plurality of memristors and a plurality of MOS tubes. The information storage circuit comprises a plurality of I-V conversion circuits which are connected with one another, an analog-to-digital converter (ADC) and a field programmable gate array (FPGA). According to the technical scheme, the problems that in the prior art, a memristor circuit is complex in design principle, not easy to implement and low in accuracy are solved.

Description

Technical Field

[0001] The present invention relates to the field of memristor memory circuits, and particularly to a single-layer fully-connected memory storage circuit and method based on a nano-memristor array. Background Art

[0002] Neural networks imitate the neurons and synaptic connections of the human brain. Through a large amount of data learning and training, they can process complex pattern recognition and decision-making problems. This method of simulating biological neural network systems enables machines to perform intelligent decision-making, problem-solving, information memory recognition, etc., greatly promoting the development of artificial intelligence technology.

[0003] As the fourth basic circuit element in addition to capacitors, inductors, and resistors, the memristor is a major scientific discovery in the current field of electronic information. The current or conductance at both ends of the memristor can change with voltage, and after the voltage disappears, its conductance can still be "stored". These unique non-linear and non-volatile characteristics are similar to the Na+ and Ca2+ ion influx mechanisms in biological synapses, and it is considered to be one of the best candidate devices for simulating synaptic plasticity. The fully-connected single-layer neural network circuit constructed by memristors can achieve the function of memory storage and simulate the memory mode of organisms. Currently, many memory circuits have been proposed, but many circuits are designed based on analog memristors, and there is a large difference between the simulation results and the actual results. There is also a part that is designed based on physical memristor circuits, but its circuit is relatively complex and the result is only the synaptic display result, without truly demonstrating the memory effect.

[0004] Therefore, there is a need for a single-layer fully-connected memory storage circuit and method based on a nano-memristor array with a simple circuit principle, easy to implement, and high precision. Summary of the Invention

[0005] The main object of the present invention is to provide a single-layer fully-connected memory storage circuit based on a nano-memristor array to solve the problems of complex circuit design principle, difficult to implement, and low precision in the existing memristor circuits.

[0006] To achieve the above object, the present invention provides a single-layer fully-connected memory storage circuit based on a nano-memristor array, including: an information input circuit, an information memory circuit, and an information storage circuit connected in sequence. The information memory circuit includes: multiple groups of interconnected digital-to-analog converters (DACs) and a memristor crossbar array. The memristor crossbar array includes: multiple memristors and multiple MOS transistors. The information storage circuit includes: multiple interconnected I-V conversion circuits, an analog-to-digital converter (ADC), and an FPGA.

[0007] Further, the information input circuit includes: a PC terminal and an FPGA connected to each other.

[0008] Further, the FPGA is connected to N DACs. Each group of interconnected DACs and memristive crossbar arrays includes: one DAC, multiple memristors, and multiple MOS transistors. In each group, the DAC is connected to the drain of the first MOS transistor through the first memristor, the first DAC is also connected to the drain of the second MOS transistor through the second memristor, and the first DAC is also connected to the drain of the Nth MOS transistor through the Nth memristor; the gates of the first MOS transistors in each group are interconnected and connected to the serial port of the FGPA, the gates of the second MOS transistors in each group are interconnected and connected to the serial port of the FGPA, and the gates of the Nth MOS transistors in each group are interconnected and connected to the serial port of the FGPA; the sources of the first MOS transistors in each group are interconnected and connected to the first I-V conversion circuit, the sources of the second MOS transistors in each group are interconnected and connected to the second I-V conversion circuit, and the sources of the Nth MOS transistors in each group are interconnected and connected to the Nth I-V conversion circuit; each I-V conversion circuit is correspondingly connected to one ADC, and multiple ADCs are connected to the FPGA.

[0009] Further, the memristive crossbar array is a 1N1M memristive crossbar array, including: N×M memristors and N×M MOS transistors, where N is the number of rows of the memristive crossbar array and M is the number of columns of the memristive crossbar array.

[0010] Further, the surface of the memristor is coated with silicone electronic sealant.

[0011] Further, the I-V conversion circuit includes: the first resistor R 1 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the fifth resistor R 5 and an inverting amplifier. The first resistor R 1 is connected to the non-inverting input terminal of the inverting amplifier, the third resistor R 3 is connected to the inverting input terminal of the inverting amplifier. The other end of the first resistor R 1 is connected to the other end of the third resistor R 2 through the second resistor R 3 . One ends of the second resistor R 2 and the third resistor R 3 are grounded. The third resistor R 3 is connected to the fourth resistor R 4 . One ends of the first resistor R 1 and the second resistor R 2 are connected together as the current input terminal of the I-V conversion circuit. One end of the fifth resistor R 5 is connected to the output terminal of the inverting amplifier, and the other end is connected to the other end of the fourth resistor R 4 as the voltage output terminal of the I-V conversion circuit. The I-V conversion operation relationship is expressed as: ; Wherein, I is the input terminal current and V is the output terminal voltage.

[0012] Furthermore, the information output circuit includes: M I-V conversion circuits, M / 2 dual-channel 16-bit ADCs, and an FPGA.

[0013] The present invention also provides a single-layer fully-connected memory storage circuit method based on a nano memristor array, which specifically includes the following steps: S1, process the picture information to be stored in the PC end according to N×M-bit pixels, and convert the information into a serial digital signal in binary format through the USB interface of the PC end, and transmit it to the memory card accessed by the FPGA;

[0014] S2, convert the digital serial digital signal in the FPGA into an analog voltage signal through a DAC, and input it into the memristor crossbar array. Control the memristor conductance or current through the input voltage signal, and convert the picture information into a memristor conductance or current signal and store it in the memristor crossbar array;

[0015] S3, read the output current signal of the MOS transistor in the memristor crossbar array, convert and amplify it into a voltage signal through the I-V conversion circuit, then form a digital signal through the ADC, and send it back to the FPGA through the data bus. Calculate and compare the synaptic conductance weights through the FPGA platform to complete memory access.

[0016] The present invention has the following beneficial effects: The present invention simulates various plasticities of bionic synapses through a memristor crossbar array, improves the disadvantages of traditional synapses such as large volume, high energy consumption, and complex circuits. The obtained results are not simulation results, and the memory storage effect can be directly seen from the display screen. It can well simulate the bionic memory mode of the brain, increase the bionic function of the artificial network, and improve the practical application value of the memory storage circuit;

[0017] The single-layer fully-connected memory circuit based on a physical memristor crossbar array breaks through the multi-layer structure of complex neural networks in traditional memory circuits. Only a single-layer memristor crossbar array and the PFGA peripheral circuit can be used to construct a memory storage circuit, which has the advantages of simple circuit, easy debugging, clear and obvious results, etc., and provides flexibility and reusability. Description of the Drawings

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings: Figure 1 Shows a simplified circuit diagram of a single-layer fully-connected memory storage circuit based on a nano memristive cross array of the present invention.

[0019] Figure 2 Shows the I-V conversion circuit diagram of the present invention.

[0020] Figure 3 Shows the test result diagram of the double-facilitation synaptic plasticity of the memristor array in the present invention.

[0021] Figure 4 Shows the test result diagram of the synaptic plasticity of the memristor array under short-term learning stimulation in the present invention.

[0022] Figure 5 Shows the test result diagram of the synaptic plasticity of the memristor array under long-term learning stimulation in the present invention.

[0023] Figure 6 Shows the test result diagram of the "learning-forgetting-learning" process test of the memristive cross array simulating synapses provided by the present invention.

[0024] Figure 7 Shows the short-term picture memory result diagram of the memory experiment using the single-layer fully-connected memory storage circuit provided by the present invention.

[0025] Figure 8 Shows the long-term picture memory result diagram of the memory experiment using the single-layer fully-connected memory storage circuit provided by the present invention.

[0026] The reference numerals in the above-mentioned drawings are as follows: 1. PC side; 2. FPGA; 3. DAC; 4. Memristor; 5. MOS transistor; 6. I-V conversion circuit; 7. ADC. Specific embodiments

[0027] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0028] As Figure 1A single-layer fully-connected memory storage circuit based on a nano memristor array is shown, including: an information input circuit, an information memory circuit, and an information storage circuit connected in sequence. The information memory circuit includes: multiple groups of interconnected digital-to-analog converters DAC3 and memristor cross arrays. The memristor cross array includes: multiple memristors 4 and multiple MOS transistors 5. The information storage circuit includes: multiple interconnected I-V conversion circuits 6, an analog-to-digital converter ADC7, and an FPGA2.

[0029] Specifically, the DAC is 12-bit, and in this embodiment, TCL5615 is used. The MOS transistor is 2N7002. The DIN, SCLK, and CS pins of the DAC TCL5615 are connected to the serial port of the PFGA, the DOUT pin is left floating, the AGND pin is grounded, the REFIN pin is connected to a 2V DC power supply, the VDD pin is connected to a 7V DC power supply, and the OUT pin is connected to the bit line Vcc port of the memristor cross array.

[0030] Specifically, the information input circuit includes: a PC terminal 1 and an FPGA connected to each other.

[0031] Specifically, the FPGA is connected to N DACs. Each group of interconnected DACs and memristor cross arrays includes: one DAC, multiple memristors, and multiple MOS transistors. The DAC in each group is connected to the drain of the first MOS transistor through the first memristor. The first DAC is also connected to the drain of the second MOS transistor through the second memristor. The first DAC is also connected to the drain of the Nth MOS transistor through the Nth memristor. The gates of the first MOS transistors in each group are interconnected and connected to the serial port of the FGPA. The gates of the second MOS transistors in each group are interconnected and connected to the serial port of the FGPA. The gates of the Nth MOS transistors in each group are interconnected and connected to the serial port of the FGPA. The sources of the first MOS transistors in each group are interconnected and connected to the first I-V conversion circuit. The sources of the second MOS transistors in each group are interconnected and connected to the second I-V conversion circuit. The sources of the Nth MOS transistors in each group are interconnected and connected to the Nth I-V conversion circuit. Each I-V conversion circuit is correspondingly connected to an ADC, and multiple ADCs are connected to the FPGA.

[0032] Specifically, the memristor cross array is a 1N1M memristor cross array, including: N×M memristors and N×M MOS transistors, where N is the number of rows of the memristor cross array and M is the number of columns of the memristor cross array.

[0033] The 1N1M memristive crossbar array consists of 3×3 nano-memristors and 3×3 MOS transistors; the preparation process of the memristive crossbar array is as follows: The prepared memristors are cut into 3 mm×3 mm bare chips by a dicing machine, and there is one memristor on each chip. The bare chips are fixed on a printed circuit board (PCB) with epoxy resin glue, and then 2N7002 type MOS transistors are mounted on the back of the PCB, and their source, drain and gate leads are led to the front of the circuit board. The electrodes of the memristors are connected to the pads on the PCB with conductive silver glue. The top electrode of the memristor is connected to the bit line Vcc terminal and is connected to the output terminal of the DAC. The bottom electrode of the memristor is connected to the drain of the MOS transistor. The sources of the MOS transistors in the same column are connected together and connected to the input of the I-V conversion circuit, and are connected to R 1 and R 2 at one end. In addition, the gates of the MOS transistors in the same column are connected together and connected to the serial port of the FGPA to control the startup and disconnection of the MOS. To prevent oxidation and damage to the device, a layer of silicone electronic sealant is applied to the surface of the nano-memristor for covering and protection, and finally a 3×3 1N1M structure is formed;

[0034] Specifically, the surface of the memristor is coated with silicone electronic sealant.

[0035] Specifically, as Figure 2 shown, the I-V conversion circuit includes: the first resistor R 1 , the second resistor R 2 , the third resistor R 3 , the fourth resistor R 4 , the fifth resistor R 5 and an inverting amplifier. The first resistor R 1 is connected to the non-inverting input terminal of the inverting amplifier, the third resistor R 3 is connected to the inverting input terminal of the inverting amplifier, the other end of the first resistor R 1 is connected to the other end of the third resistor R 2 through the second resistor R 3 . One end of the second resistor R 2 and the third resistor R 3 is grounded. The third resistor R 3 is connected to the fourth resistor R 4 . One end of the first resistor R 1 and the second resistor R 2 are connected together as the current input terminal of the I-V conversion circuit. One end of the fifth resistor R 5 is connected to the output terminal of the inverting amplifier, and the other end is connected to the other end of the fourth resistor R 4 as the voltage output terminal of the I-V conversion circuit. The I-V conversion operation relationship is expressed as: ; Among them, I is the input terminal current, and V is the output terminal voltage. 1 + R 4 / R 3 The value of represents the voltage amplification factor.

[0036] The I-V conversion circuit, including an inverting proportional amplifier and five resistors, is configured to achieve an inverting proportional conversion relationship between the output voltage and the input current. The inverting proportional amplifier is composed of some pins of the TL082CP operational amplifier chip. R 1 and R 2 One end is connected together as the entrance of the I-V conversion circuit and is connected to the source electrodes of the MOS transistors in the same column bit of the 1N1M memristive crossbar array. R 2 The other end is connected to the ground; 3 One end of R 1 The other end is connected to the third pin (non-inverting input terminal) of the operational amplifier chip; 3 The other end is connected to R 4 and is connected to the second pin (inverting input terminal) of the operational amplifier chip; 5 One end is connected to the first pin (output terminal) of the operational amplifier chip, and the other end is connected to R 4 The other end is connected as the voltage output terminal of the I-V conversion circuit; the eighth and fourth (VCC + / - operating voltage terminals) of the operational amplifier chip are respectively connected to +12 V and -12 V DC voltage sources.

[0037] Specifically, the information output circuit includes: M I-V conversion circuits, M / 2 dual-channel 16-bit ADCs, and FPGA.

[0038] The present invention also provides a method for a single-layer fully-connected memory storage circuit based on a nano-memristive crossbar array, specifically including the following steps: S1, Process the picture information to be stored in the PC end according to N×M-bit pixels, and convert the information into a serial digital signal in binary format through the USB interface of the PC end, and transmit it to the memory card accessed by the FPGA.

[0039] S2, Convert the digital serial digital signal in the FPGA into an analog voltage signal through the DAC, and input it into the memristive crossbar array. Control the conductance or current of the memristor through the input voltage signal, and convert the picture information into a memristor conductance or current signal and store it in the memristive crossbar array.

[0040] S3, Read the output current signal of the MOS transistor in the memristive crossbar array, convert and amplify it into a voltage signal through the I-V conversion circuit, then form a digital signal through the ADC, and send it back to the FPGA through the data bus. Calculate and compare the synaptic conductance weights through the FPGA platform to complete memory access.

[0041] The 16-bit ADC (AD7705) is a dual-channel analog-to-digital converter that can directly receive the output voltage signal from the I-V conversion circuit, and then generate a serial digital output, which is transmitted back to the FPGA through the data bus. AD7705 has 16 chip pins. In this invention, the VHDL language is used to communicate between the FPGA communication interface and the CS, SCLK, and DOUT ports of AD7705 to complete the reception of serial data. The two groups of analog signal input terminals AIN1(+), AIN1(-) and AIN2(+), AIN2(-) are respectively configured for unipolar input and connected to the output terminals of two adjacent I-V conversion circuits. REF(+), REF(-) are the reference input terminals, connected to a 1.25 V DC voltage power supply. The power supply voltage VDD is connected to a 3 V DC voltage power supply, GND is grounded, and other pins are left floating.

[0042] Two positive pulses with an amplitude of 3 V and a duration of 26 ms are continuously input to the self-made memristive crossbar array. The interval between the two pulses is 150 ms. After each pulse, a read voltage with an amplitude of 0.1 V and a width of 10 ms follows to read the current value across the memristor, and the Figure 3 results shown are obtained. After the first pulse arrives, the current of the memristor rises rapidly, indicating a change in the state of the memristor; after the pulse ends, the current also drops back to the initial state; when the second pulse arrives, the current rises again and the state of the memristor changes; after the pulse ends, the current still drops and finally returns to the initial state. This result shows that the current or state of the fabricated memristive crossbar array can change with the input voltage pulse, and can return to the initial state when the pulse ends. Thus, it is verified that the fabricated memristive crossbar array can simulate the short-term plasticity of synapses, that is, a short learning stimulus can bring about short-term memory effects, and after a long time, the memory fades. In the experiment, the current across the memristor in the memristive crossbar array can represent the synaptic weight, which is used to reflect the degree of memory of information. The higher the current, the stronger the memory; conversely, the weaker the memory.

[0043] Thirty and 120 positive pulses with an amplitude of 3 V and a width of 26 ms are respectively and continuously input to the memristive crossbar array. The interval between adjacent two pulses is 50 ms. After each pulse, a read voltage with an amplitude of 0.2 V and a width of 10 ms follows to read the current value across the memristor, and the Figure 4 and Figure 5 results shown are obtained, where red represents the current results of 30 input pulses and green represents the current results of 120 input pulses. After 30 consecutive voltage pulses are input, the current of the fabricated memristor increases to and the current state cannot return to the initial state after a long time. After 120 consecutive voltage pulses are input, the current increases to . By comparing the results of 30 consecutive voltage pulses and 120 consecutive voltage pulses, it can be seen that the final current result of the latter is larger than that of the former, indicating that the longer the learning period of the memristor, the better the information memory effect and the less forgotten.

[0044] The three stages of the bionic memory model based on the short-term plasticity and long-term plasticity simulation of physical memristive synapses include: the learning stage, the short-term memory stage, and the long-term memory stage. In this memory model, information from the environment is first encoded in sensory memory through a short learning stage. If the information is perceived, it will be further stored as short-term memory. If the information retained in the short-term memory mode undergoes repeated rehearsal or training in the learning stage, it will be transformed into long-term memory. After applying a learning voltage pulse to the single-layer fully connected memory storage circuit based on the nano-memristive cross array, the conductance of the memristor increases. If learning does not continue and the voltage pulse disappears, the conductance rapidly decreases and finally returns to the initial state, representing short-term memory. If multiple repeated voltage pulses are repeatedly applied to the single-layer fully connected memory storage circuit of the nano-memristive cross array, the conductance of the memristor increases and after the voltage disappears, the conductance slightly decreases but does not return to the initial state, representing long and short-term memory.

[0045] Figure 6 This is the test result of the "learning - forgetting - learning" process of the memristive cross array simulating synapses in this embodiment. The learning process is represented by continuous pulses. A test cycle pulse with a voltage of 4 V and a width of 50 ms is continuously input to the memristive cross array 100 times, with a 50 ms interval between adjacent pulses. A read voltage with an amplitude of 0.2 V and a width of 10 ms follows each pulse to read the current value across the memristor. When 100 consecutive pulses are input, the peak memory current reaches and then remains unchanged, indicating that the memristor reaches the optimal memory state. When the memory current caused by the stimulus exceeds 7.30×10 -7When the perceptual peak memory level of A is reached, information is encoded into short-term memory. Subsequently, when the repeated training disappears, the magnitude of the memory current drops sharply and then gradually stabilizes, indicating the continuous consolidation of memory. Then, a second input of 50 consecutive identical pulses is given to the memristor, and the synaptic weight reaches the peak of the memory current. After the repeated training disappears, the magnitude of the memory current briefly drops again and reaches a stable state, and the stable current is greater than the final current of the first learning. After the repeated training disappears, the magnitude of the memory current only drops slightly, then quickly stabilizes and remains unchanged for a long time. It is worth noting that during the first learning rehearsal, 100 consecutive pulses are required for the synaptic weight to reach the peak of the memory current. However, after repeated learning, only 50 pulses are needed to restore the memory to the peak level. During the second learning, only one-twelfth of the number of pulses required in the first learning stage is sufficient to restore the memory level to the highest level. This phenomenon indicates that synaptic memory with a "learning - forgetting - learning" process helps to relearn forgotten information more easily, similar to the learning and memory recovery process of natural organisms. And the repeated learning memory consolidates and transitions into long-term memory.

[0046] Using the single-layer fully connected memory storage electricity provided by the present invention, a picture memory experiment is carried out, including the learning and testing processes.

[0047] The learning process is as follows: The computer first divides the training pictures into 3×3 pixels and converts them into binary pulse signals and stores them in the FPGA memory card. The FPGA first reads the initial weights and stores them in the SRAM; then a training picture is input into the memristive cross array, and the memristive current results output by columns are converted into weight results A and stored in the SRAM. Next, it is judged whether to continue learning. If continue learning, the training pictures are repeatedly input into the memristive cross array to output updated weight results until no longer continue learning, and the latest weight results are stored in the SRAM.

[0048] The testing process is as follows: The computer pre-sets a test cycle pulse sequence with a voltage of 0.2 V (the reading voltage cannot change the memristive cross array current value). After the learning process is completed, it is input into the memristive cross array, and the updated weight results B are read by columns (in order to test the picture memory effect, the updated weights can be repeatedly read 1 s, 5 s, and 50 s or longer after the learning process is completed) and stored in the FPGA memory card; the software program is used to compare the learning weights and the test weight values, and the results are mapped into pictures with different shades of color and displayed on the liquid crystal display of the FPGA to complete the picture memory test.

[0049] Figure 7This is the short-term picture memory result of the memory experiment in this embodiment. The "T" graphic picture is used as the learning picture, and one learning cycle is executed, that is, 30 times of circulation, to obtain the weight result A; subsequently, the test process is executed after 1 s, 5 s, and 50 s respectively, and the memory weight B of the memristor is read, which is the result obtained through picture mapping calculation. It can be found that when the picture is only learned once, the picture after 1 s can still be clearly remembered, and the picture after 50 s gradually becomes blurred. The experiment successfully simulates that in the case of the biological brain with short learning time, information is easily forgotten, reflecting short-term memory.

[0050] Figure 8 This is the long-term picture memory result of the memory experiment in this embodiment. When the "×" graphic picture is continuously learned for 4 cycles, that is, 120 times of circulation, the weights of the memristor are read after 1 s, 5 s, and 50 s respectively, and the obtained picture results are obtained. Figure 8 The pictures after 1 s of learning and after 50 s of learning are shown. It can be found that when the picture is only learned 4 times, the picture after 50 s can still be clearly remembered. The experiment successfully simulates that in the case of the biological brain with multiple learning times, information can be easily remembered by time and is not easily forgotten, reflecting long-term memory.

[0051] The present invention provides a learning and memory storage circuit based on a nano-memristor for simulating the bionic memory function of the brain. In the circuit based on the nano-memristor, the nano-memristor and the MOS transistor form a memristive crossbar array to simulate bionic synaptic plasticity, including short-term plasticity and long-term plasticity. The picture information to be stored in memory is converted into pulse information in binary format and input into the memory card accessed by the FPGA through the USB serial bus. After the FPGA reads the data into the internal SRAM one by one, it is input into the analog-to-digital converter DAC TCL5615 in a time-division multiplexing manner through the chip select new signal line and the data bus, and is converted into an analog voltage signal and input into the bit line of the memristive crossbar array; the current information is collected through the source line in the memristive crossbar array and input into the I-V conversion circuit and the 16-bit analog-to-digital converter ADC. Finally, the output voltage signal is transmitted back to the FPGA through the data bus to obtain the memory synaptic current weight A, which is recorded in the memory; subsequently, a read voltage pulse signal is input in the same way, and after passing through the memristive crossbar array, the I-V conversion circuit, and the analog-to-digital converter ADC in sequence, the signal is transmitted back to the FPGA to obtain the calculated synaptic current weight B again; compare the results of B and A, and convert the weight result into different shades of picture color information through linear mapping. The larger the current, the darker the picture color and the stronger the memory. On the contrary, the lighter the picture color, the stronger the memory; the result is displayed on the liquid crystal display through the VGA interface; if B is close to A, it means the picture memory is clear, and the smaller B is than A, the more the degree of memory forgetting and the more blurred the picture color.

[0052] Certainly, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those skilled in the art within the scope of the essence of the present invention shall also fall within the protection scope of the present invention.

Claims

1. A single-layer fully connected memory storage circuit based on a nano-memristor array, characterized in that: include: An information input circuit, an information memory circuit and an information storage circuit are connected in sequence, wherein the information memory circuit comprises: a plurality of groups of interconnected digital-to-analog converters DAC and memristor cross arrays, the memristor cross array comprises: a plurality of memristors and a plurality of MOS tubes, and the information storage circuit comprises: a plurality of interconnected IV conversion circuits, analog-to-digital converters ADC and FPGA.

2. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 1, characterized in that: The information input circuit includes: a PC terminal and an FPGA which are connected to each other.

3. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 2, characterized in that: The FPGA is connected to N DACs, and each group of interconnected DACs and memristor cross arrays includes: a DAC, multiple memristors and multiple MOS tubes, the DAC in each group is connected to the drain of the first MOS tube through the first memristor, the first DAC is also connected to the drain of the second MOS tube through the second memristor, and the first DAC is also connected to the drain of the Nth MOS tube through the Nth memristor; the gates of the first MOS tubes in each group are connected to each other and connected to the serial port of the FGPA, the gates of the second MOS tubes in each group are connected to each other and connected to the serial port of the FGPA, and the gates of the Nth MOS tubes in each group are connected to each other and connected to the serial port of the FGPA; the sources of the first MOS tubes in each group are connected to each other and connected to the first IV conversion circuit, the sources of the second MOS tubes in each group are connected to each other and connected to the second IV conversion circuit, and the sources of the Nth MOS tubes in each group are connected to each other and connected to the Nth IV conversion circuit; each IV conversion circuit is correspondingly connected to an ADC, and multiple ADCs are connected to the FPGA.

4. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 3, characterized in that: The memristor cross array is a 1N1M memristor cross array, including: N×M memristors, N×M MOS tubes, wherein N is the number of rows of the memristor cross array, and M is the number of columns of the memristor cross array.

5. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 3, characterized in that: The surface of the memristor is coated with silicone electronic sealant.

6. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 3, characterized in that: The IV conversion circuit includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and an inverse proportional device, wherein the first resistor R1 is connected to the positive input end of the inverse proportional device, the third resistor R3 is connected to the inverse input end of the inverse proportional device, the other end of the first resistor R1 is connected to the other end of the third resistor R3 through the second resistor R2, one end of the second resistor R2 and the third resistor R3 is grounded, the third resistor R3 is connected to the fourth resistor R4, one end of the first resistor R1 and the second resistor R2 are connected as the current input end of the IV conversion circuit, one end of the fifth resistor R5 is connected to the output end of the inverse proportional device, and the other end is connected to the other end of the fourth resistor R4 as the voltage output end of the IV conversion circuit, and the IV conversion operation relationship is expressed as: ； Among them, I is the input current and V is the output voltage.

7. A single-layer fully connected memory storage circuit based on a nano-memristor array according to claim 6, characterized in that: The information output circuit includes: M IV conversion circuits, M / 2 dual-channel 16-bit ADCs and FPGA.

8. A single-layer fully connected memory storage circuit method based on a nano-memristor array, using the circuit described in any one of claims 1 to 7, characterized in that: The specific steps include: S1, processes the image information to be stored in the PC according to N×M pixels, and converts the information into a serial digital signal in binary format through the USB interface of the PC, and transmits it to the memory card accessed by the FPGA; S2, converts the digital serial signal in the FPGA into an analog voltage signal through the DAC, and inputs it into the memristor crossbar array, controls the memristor conductance or current through the input voltage signal, and converts the image information into a memristor conductance or current signal and stores it in the memristor crossbar array; S3 reads the output current signal of the MOS tube in the memristor crossbar array, converts and amplifies it into a voltage signal through the IV conversion circuit, and then forms a digital signal through the ADC. It is transmitted back to the FPGA through the data bus, and the synaptic conductance weight is calculated and compared through the FPGA platform to complete memory access.

Images