Preparation method of trench type MOSFET

Abstract

The invention relates to a preparation method of a groove type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), which comprises the following steps of: forming a silicon oxide layer on the top surface of a silicon carbide substrate by adopting a thermal oxidation process, and then forming a groove in the silicon oxide layer; forming an initial gate electrode in the groove and on the top surface of a part of the silicon oxide layer on the outer side of the groove; etching the silicon oxide layer until the top surface of the silicon carbide substrate is exposed by taking the initial gate electrode as a mask, and forming a gate dielectric layer covering the bottom surface and the side wall of the groove; forming an epitaxial silicon carbide layer on the top surface of the silicon carbide substrate outside the gate dielectric layer; and removing a part of the epitaxial silicon carbide layer and a part of the initial gate electrode until the top surface of the gate dielectric layer is exposed, and taking the residual initial gate electrode in the groove as a gate electrode. According to the method, the gate dielectric layer of which the shape thickness can meet the design requirement is arranged at the bottom of the groove, so that the pressure resistance of the device is improved, the defects of the gate dielectric layer and a silicon carbide substrate interface are reduced, and the reliability of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly relates to a method for manufacturing a trench MOSFET. Background Art

[0002] As a third-generation wide bandgap semiconductor material, silicon carbide (SiC) has advantages such as a wide bandgap, a high critical breakdown electric field, a high electron saturation mobility, and a high thermal conductivity, and has become a hot topic in the research of current power devices. Among SiC switching devices, SiC MOSFETs have advantages such as fast switching speed, high voltage resistance, and low power consumption. SiC MOSFETs are mainly divided into planar and trench types. Compared with planar SiC MOSFETs, trench SiC MOSFETs have higher electron mobility, no JFET effect, lower on-resistance, lower conduction loss, and at the same time, the vertical channel distribution greatly improves the device density and reduces the cost.

[0003] Although SiC trench MOSFETs have excellent performance, there are many technological difficulties in the manufacturing process. For example, when forming a silicon oxide layer as a gate dielectric layer on the sidewalls and bottom of the trenches in the SiC substrate by thermal oxidation, the thickness of the silicon oxide layer at the bottom of the trenches will be much thinner than that of the silicon oxide layer on the sidewalls of the trenches, affecting the voltage resistance performance of the device, and a large number of defects are likely to occur at the interface between the silicon oxide layer and the SiC substrate, greatly reducing the reliability of the device. Summary of the Invention

[0004] Based on this, the present application provides a method for manufacturing a trench MOSFET to form a gate dielectric layer with a thickness that meets the design requirements at the bottom of the trench, so as to improve the voltage resistance performance of the device and reduce the defects at the interface between the gate dielectric layer and the silicon carbide substrate, thereby improving the reliability of the device.

[0005] An embodiment of the present application provides a method for manufacturing a trench MOSFET, including:

[0006] Providing a silicon carbide substrate;

[0007] Forming a silicon oxide layer on the top surface of the silicon carbide substrate by using a thermal oxidation process;

[0008] Forming trenches in the silicon oxide layer;

[0009] Forming an initial gate electrode on the top surface of the trenches and a part of the silicon oxide layer outside the trenches;

[0010] Using the initial gate electrode as a mask to etch the silicon oxide layer until the top surface of the silicon carbide substrate is exposed, forming a gate dielectric layer covering the bottom surface and sidewalls of the trenches;

[0011] An epitaxial silicon carbide layer is formed on the top surface of the silicon carbide substrate outside the gate dielectric layer;

[0012] Part of the epitaxial silicon carbide layer and part of the initial gate electrode are removed until the top surface of the gate dielectric layer is exposed, and the remaining initial gate electrode in the trench serves as the gate electrode.

[0013] In some embodiments of the present application, it further includes: forming a drain region in the silicon carbide substrate; forming a body region in the epitaxial silicon carbide around the gate electrode; forming a source region in the body region, and the types of impurity ions doped in the source region and the drain region are opposite to the types of impurity ions doped in the body region.

[0014] In some embodiments of the present application, the epitaxial silicon carbide layer is formed by an in-situ doping selective epitaxy process, and the type of impurity ions doped in the epitaxial silicon carbide is opposite to the type of impurity ions doped in the body region.

[0015] In some embodiments of the present application, the process of forming the initial gate electrode on the top surface of the part of the silicon oxide layer in the trench and outside the trench includes: forming a first sacrificial layer on the top surface of the silicon oxide layer, and the material of the first sacrificial layer is different from the material of the silicon oxide layer; forming a second sacrificial layer on the top surface of the first sacrificial layer, and the material of the second sacrificial layer is different from the material of the first sacrificial layer; forming a patterned photoresist layer on the top surface of the second sacrificial layer; using the patterned photoresist layer as a mask, etching the second sacrificial layer, the first sacrificial layer and the silicon oxide layer in sequence, forming openings in the second sacrificial layer and the first sacrificial layer, and forming trenches communicating with the openings in the silicon oxide layer; along the direction parallel to the top surface of the first sacrificial layer, removing a part of the width of the first sacrificial layer from part of the side walls of the opening, so that the width of the opening in the first sacrificial layer becomes larger, and the removed width of the first sacrificial layer is less than or equal to the thickness of the silicon oxide layer below the bottom surface of the trench; forming a gate electrode material layer filling the trench, the opening and covering the top surface of the second sacrificial layer; using a chemical mechanical polishing process to remove part of the gate electrode material layer and the second sacrificial layer, exposing the top surface of the first sacrificial layer, forming an initial gate electrode in the opening of the first sacrificial layer and the trench of the silicon oxide layer; removing the first sacrificial layer.

[0016] In some embodiments of the present application, the process of removing a part of the width of the first sacrificial layer from part of the side walls of the opening along the direction parallel to the top surface of the first sacrificial layer adopts an isotropic wet etching process.

[0017] In some embodiments of the present application, the material of the first sacrificial layer includes silicon nitride, silicon oxynitride or silicon carbonitride, the material of the second sacrificial layer includes silicon oxide, and the material of the gate electrode material layer includes polysilicon.

[0018] In some embodiments of the present application, the etching solution used in the isotropic wet etching process includes hot phosphoric acid.

[0019] In some embodiments of the present application, the gas used in the thermal oxidation process is oxygen or a mixed gas of oxygen and water vapor. The temperature range of the thermal oxidation process is 1100°C to 1400°C, and the time of the thermal oxidation process is greater than or equal to 30 minutes.

[0020] In some embodiments of the present application, the thickness range of the silicon oxide layer formed on the top surface of the silicon carbide substrate by the thermal oxidation process is 300 nm - 1000 nm; after forming a trench in the silicon oxide layer, the thickness range of the remaining silicon oxide layer at the bottom of the trench is 100 nm - 300 nm; the thickness range of the gate dielectric layer on the bottom surface of the trench is 100 nm - 300 nm, and the thickness range of the gate dielectric layer on the sidewall of the trench is 30 nm - 250 nm.

[0021] In some embodiments of the present application, using the initial gate electrode as a mask, the silicon oxide layer is etched until the top surface of the silicon carbide substrate is exposed by an anisotropic plasma etching process.

[0022] In some embodiments of the present application, it further includes: using a chemical mechanical polishing process to remove part of the epitaxial silicon carbide layer and part of the initial gate electrode until the top surface of the gate dielectric layer is exposed.

[0023] The embodiments of the present application can / at least have the following advantages:

[0024] In the method for manufacturing a trench MOSFET according to an embodiment of the present application, first, a thermal oxidation process is used to form a silicon oxide layer on the top surface of a silicon carbide substrate. After that, trenches are formed in the silicon oxide layer; an initial gate electrode is formed on the top surface of a part of the silicon oxide layer in the trenches and outside the trenches; using the initial gate electrode as a mask, the silicon oxide layer is etched until the top surface of the silicon carbide substrate is exposed, forming a gate dielectric layer covering the bottom and sidewalls of the trenches; an epitaxial silicon carbide layer is formed on the top surface of the silicon carbide substrate outside the gate dielectric layer; a part of the epitaxial silicon carbide layer and a part of the initial gate electrode are removed until the top surface of the gate dielectric layer is exposed, and the remaining initial gate electrode in the trenches serves as the gate electrode. In the present application, since the silicon oxide layer is formed by oxidizing a part of the thickness of the silicon carbide material on the top surface of the silicon carbide substrate using a thermal oxidation process, the formed silicon oxide has a higher density, better uniformity, and good bonding performance with the silicon carbide substrate. There are fewer defects at the interface between the silicon oxide layer and the silicon carbide substrate, improving the reliability of the subsequently formed trench MOSFET. And because the top surface of the silicon carbide substrate has the same crystal plane, the growth rate of the silicon oxide layer at different positions on the top surface can be kept consistent. By controlling the relevant parameters of the thermal oxidation process (such as the process time, etc.), a silicon oxide layer with a predetermined thickness can be formed. After forming the silicon oxide layer, when forming trenches in the silicon oxide layer, the etching depth of the trenches can be controlled to make the thickness of the remaining silicon oxide layer at the bottom of the trenches still meet the design requirements (such as when a thicker thickness of the gate dielectric layer is required at the bottom of the trenches), so as to improve the breakdown voltage performance of the trench MOSFET. Moreover, after forming the initial gate electrode on the top surface of a part of the silicon oxide layer in the trenches and outside the trenches, that is, part of the initial gate electrode fills the trenches and part of the initial gate electrode is located on the top surface of the silicon oxide layer outside the trenches. When etching the silicon oxide layer using the initial gate electrode as a mask, a gate dielectric layer can be formed self-alignedly on the sidewalls and bottom of the trenches, improving the accuracy of the thickness and position of the gate dielectric layer formed on the sidewalls of the trenches and the thickness uniformity. Especially when the thickness of the gate dielectric layer formed on the sidewalls of the trenches is relatively thin, the solution of the present application can also ensure the accuracy of the thickness and position of the gate dielectric layer formed on the sidewalls of the trenches and the thickness uniformity, further improving the reliability of the trench MOSFET.

[0025] Details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0027] Figures 1 - 10 It is a schematic cross-sectional structure diagram of each stage in the preparation process of a trench MOSFET provided by some embodiments of the present application.

[0028] Description of reference numerals:

[0029] 101 - silicon carbide substrate; 102 - silicon oxide layer; 103 - first sacrificial layer; 104 - second sacrificial layer; 105 - patterned photoresist layer; 106 - opening; 107 - trench; 108 - gate electrode material layer; 109 - initial gate electrode; 110 - gate dielectric layer; 111 - epitaxial silicon carbide layer; 112 - gate electrode; 113 - body region; 114 - source region; 115 - isolation region. Detailed implementation manners

[0030] To facilitate the understanding of the present application, the following will describe the present application more comprehensively with reference to the relevant accompanying drawings. Embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0032] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion.

[0033] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0034] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0035] The structure of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but includes shape deviations caused by, for example, manufacturing techniques.

[0036] It can be understood that in the accompanying drawings of the specification of this application, adjacent film layers with the same processed film layer material in some figures are drawn as connected to make them closer to the actual structure.

[0037] Currently, the preparation process of SiC trench MOSFET generally includes: etching the SiC epitaxial layer to form trenches; then, thermally oxidizing the SiC epitaxial layer exposed at the bottom and sidewalls of the trenches to generate a silicon oxide layer on the sidewalls and bottom of the trenches. This method will have various effects: on the one hand, when thermally oxidizing the SiC epitaxial layer to generate a silicon oxide layer, due to the different thermal oxidation rates of different crystal planes of the SiC epitaxial layer, the theoretical growth rate of silicon oxide on the crystal plane (1120) of the trench sidewall is 4 - 5 times that of the silicon oxide theoretical growth rate on the crystal plane (0001) of the trench bottom. And when the device is in the blocking state, the trench bottom bears a greater breakdown voltage. Therefore, a higher thickness of the silicon oxide layer is required at the trench bottom, that is, the thickness of the silicon oxide layer at the trench bottom is required to be thicker than that of the silicon oxide layer on the trench sidewall. The traditional thermal oxidation process cannot meet this requirement; on the other hand, when etching the SiC epitaxial layer to form trenches, a very high roughness will appear at the trench bottom. After thermal oxidation, a large number of defects will be generated at the interface between the SiC epitaxial layer and the silicon oxide layer, greatly reducing the reliability of the device. It is very difficult to avoid the high roughness at the trench bottom using traditional processes, and the process of improving the roughness of the trench bottom is also very complex.

[0038] Therefore, the embodiments of this application provide a method for preparing a trench MOSFET, which can form a gate dielectric layer with a thickness that meets the design requirements at the trench bottom to improve the breakdown voltage performance of the device and reduce the defects at the interface between the gate dielectric layer and the silicon carbide substrate, thereby improving the reliability of the device.

[0039] The following describes in detail the specific process of the method for preparing a trench MOSFET provided by this application in combination with the accompanying drawings in some embodiments. Figures 1 - 10 It is a schematic cross-sectional structure diagram of each stage in the preparation process of a trench MOSFET provided by some embodiments of this application.

[0040] With reference to Figure 1 , provide a silicon carbide substrate 101; form a silicon oxide layer 102 on the top surface of the silicon carbide substrate 101 using a thermal oxidation process.

[0041] The silicon carbide substrate 101 is part of a trench MOSFET. A drain region of the trench MOSFET can be formed in the silicon carbide substrate 101, and the drain region can be formed in the silicon carbide substrate 101 through an ion implantation process. According to the type of the trench MOSFET to be formed, the type of impurity ions doped in the drain region can be different. Specifically, when the type of the trench MOSFET to be formed is N-type, the impurity ions doped in the drain region are N-type impurity ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions; when the type of the trench MOSFET to be formed is P-type, the impurity ions doped in the drain region are P-type impurity ions, and the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions.

[0042] The silicon oxide layer 102 is subsequently used to form the gate dielectric layer of the trench MOSFET. A part of the silicon carbide material with a certain thickness on the top surface of the silicon carbide substrate 101 is oxidized by a thermal oxidation process to form the silicon oxide layer 102 on the top surface of the silicon carbide substrate 101. The silicon oxide layer 102 formed by the thermal oxidation process has a high density, good uniformity, and good bonding performance with the silicon carbide substrate 101. There are fewer defects at the interface between the silicon oxide layer 102 and the silicon carbide substrate 101, which improves the reliability of the subsequently formed trench MOSFET. Moreover, since the top surface of the silicon carbide substrate 101 has the same crystal plane, the growth rate of the silicon oxide layer at different positions on the top surface can be kept consistent. By controlling the relevant parameters of the thermal oxidation process (such as the process time, etc.), a silicon oxide layer 102 with a predetermined thickness can be formed. When forming a trench in the silicon oxide layer 102 subsequently, the depth of the formed trench can be controlled to control the thickness of the remaining silicon oxide layer 102 at the bottom of the trench, so that the thickness of the remaining silicon oxide layer 102 at the bottom of the trench can still meet the design requirements (such as when a thicker gate dielectric layer is required at the bottom of the trench) when it is used as the gate dielectric layer, so as to improve the breakdown voltage performance of the trench MOSFET.

[0043] In some embodiments, the thickness of the silicon oxide layer 102 formed on the top surface of the silicon carbide substrate 101 by the thermal oxidation process ranges from 300 nm to 1000 nm, and can be, for example, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm. In some embodiments, the gas used in the thermal oxidation process is oxygen or a mixed gas of oxygen and water vapor. The temperature range of the thermal oxidation process is 1100°C to 1400°C, and can be, for example, 1100°C, 1200°C, 1300°C, 1400°C. The time of the thermal oxidation process is greater than or equal to 30 minutes, and can be, for example, 30 minutes, 1 hour, 2 hours, 3 hours, 4 hours or longer.

[0044] In some embodiments, after forming the silicon oxide layer 102, the following steps are further included: forming a first sacrificial layer 103 on the top surface of the silicon oxide layer 102, where the material of the first sacrificial layer 103 is different from that of the silicon oxide layer 102; forming a second sacrificial layer 104 on the top surface of the first sacrificial layer 103, where the material of the second sacrificial layer 104 is different from that of the first sacrificial layer 103; forming a patterned photoresist layer 105 on the top surface of the second sacrificial layer 104.

[0045] The purposes of forming the first sacrificial layer 103 and the second sacrificial layer 104 are as follows: on the one hand, the first sacrificial layer 103 and the second sacrificial layer 104 can serve as masks when subsequently etching the silicon oxide layer 102 to form trenches 107 (refer to Figure 3 ); on the other hand, openings 106 with a specific shape communicating with the trenches can be formed in the first sacrificial layer 103 and the second sacrificial layer 104 (refer to Figure 3 ), so that an initial gate electrode 109 with a specific shape can be accurately formed in the trenches 107 and part of the openings 106 (refer to Figure 5 ).

[0046] The material of the first sacrificial layer 103 is different from that of the silicon oxide layer 102, and the material of the second sacrificial layer 104 is different from that of the first sacrificial layer 103. Subsequently, along the direction parallel to the top surface of the first sacrificial layer 103, a part of the first sacrificial layer 103 with a certain width is removed from the side walls of part of the openings 106, so that when the width of the openings 106 in the first sacrificial layer 103 becomes larger (refer to Figure 3 ), the first sacrificial layer 103 has a high etching selectivity (greater than 2:1) with respect to the silicon oxide layer 102 and the second sacrificial layer 104. While improving the accuracy of the removed width of the first sacrificial layer 103, the accuracy of the shapes of the openings 106 and the trenches 107 is ensured. In some embodiments, the material of the first sacrificial layer 103 includes silicon nitride, silicon oxynitride, or silicon carbonitride, and the material of the second sacrificial layer 104 includes silicon oxide. The processes for forming the first sacrificial layer 103 and the second sacrificial layer 104 include atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma chemical vapor deposition (HDPCVD).

[0047] The patterned photoresist layer 105 exposes part of the top surface of the second sacrificial layer 104. The formation process of the patterned photoresist layer 105 includes a spin coating process, an exposure process, and a development process.

[0048] Refer to Figures 2 - 6, a trench 107 is formed in the silicon oxide layer 102; an initial gate electrode 109 is formed on the top surface of the portion of the silicon oxide layer 102 outside the trench 107 and in the trench 107 (refer to Figure 6 ).

[0049] Next, in some embodiments, in combination with Figures 2 - 6 the specific process of forming the initial gate electrode 109 will be described.

[0050] First, refer to Figure 2 , after sequentially forming a first sacrificial layer 103, a second sacrificial layer 104, and a patterned photoresist layer 105 on the top surface of the silicon oxide layer, using the patterned photoresist layer 105 as a mask, sequentially etching the second sacrificial layer 104, the first sacrificial layer 103, and the silicon oxide layer 102, openings 106 are formed in the second sacrificial layer 104 and the first sacrificial layer 103, and a trench 107 communicating with the openings 106 is formed in the silicon oxide layer 102. The depth of the trench 107 in the silicon oxide layer 102 defines the thickness of the remaining silicon oxide layer 102 below the bottom surface of the trench 107. The thickness of the remaining silicon oxide layer 102 below the bottom surface of the trench 107 defines the thickness of the gate dielectric layer formed on the bottom surface of the trench 107 later. Therefore, by controlling the depth of the trench 107, it is possible to easily control the thickness of the gate dielectric layer formed on the bottom surface of the trench 107 to a relatively thick designed thickness, thereby improving the breakdown voltage performance of the trench-type MOSFET. In some embodiments, the sequential etching of the second sacrificial layer 104, the first sacrificial layer 103, and the silicon oxide layer 102 uses an anisotropic plasma etching process, and the etching gas used in the anisotropic plasma etching process is CF 4 , CHF 3 , C 4 F 8 or C 4 F 6 or one or several of them, or a mixed gas of any gas or multiple gases in CF 4 , CHF 3 , C 4 F 8 and C 4 F 6 and any gas in O 2 , Ar, CO, and He. It should be noted that the patterned photoresist layer 105 can be removed synchronously during the etching process.

[0051] Then, refer to Figure 3, along a direction parallel to the top surface of the first sacrificial layer 103, a part of the first sacrificial layer 103 with a partial width is removed from a part of the side wall of the opening 106, so that the width of the opening 106 in the first sacrificial layer 103 becomes larger. The removed width of the first sacrificial layer 103 is less than or equal to the thickness of the silicon oxide layer 102 below the bottom surface of the trench 107. The removed width of the first sacrificial layer 103 defines the thickness of the gate dielectric layer subsequently formed on the side wall of the trench 107. Specifically, after a part of the width of the first sacrificial layer 103 is removed, the opening 106 in the first sacrificial layer 103 will become wider. Subsequently, an initial gate electrode 109 is formed in the opening 106 in the first sacrificial layer 103 and the trench 107 in the silicon oxide layer 102 (reference Figure 5 ). After that, a part of the initial gate electrode 109 fills the trench 107, and a part of the initial gate electrode 109 is located on the top surface of the silicon oxide layer 102 outside the trench 107. When the silicon oxide layer 102 is etched using the initial gate electrode 109 as a mask (reference Figure 7 ), a gate dielectric layer 110 can be formed on the side wall and the bottom surface of the trench 107 in a self-aligned manner (reference Figure 7 ), which improves the accuracy of the thickness and position of the gate dielectric layer 110 formed on the side wall of the trench 107 and the thickness uniformity. Especially when the thickness of the gate dielectric layer 110 formed on the side wall of the trench 107 is relatively thin, the solution of the present application can also ensure the accuracy of the thickness and position of the gate dielectric layer 110 formed on the side wall of the trench 107 and the thickness uniformity, further improving the reliability of the trench MOSFET. In some embodiments, along a direction parallel to the top surface of the first sacrificial layer 103, from the side wall of the opening 106, the removed width of the first sacrificial layer 103 is 30 nm - 250 nm. The process of removing a part of the width of the first sacrificial layer 103 uses an isotropic wet etching process. The etching solution used in the isotropic wet etching process includes hot phosphoric acid. When removing a part of the width of the first sacrificial layer 103, the amount of the second sacrificial layer 104 and the silicon oxide layer 102 removed is very small and can be ignored.

[0052] Next, refer to Figure 4 , a gate electrode material layer 108 that fills the trench 107 and the opening 106 and covers the top surface of the second sacrificial layer 104 is formed. The gate electrode material layer 108 subsequently forms an initial gate electrode. In some embodiments, the material of the gate electrode material layer 108 is silicon oxide. The process of forming the gate electrode material layer 108 includes atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), high pressure chemical vapor deposition (HPCVD), plasma enhanced chemical vapor deposition (PECVD), and high density plasma chemical vapor deposition (HDPCVD).

[0053] Finally, refer toFigure 5 , a chemical mechanical polishing process is adopted to remove a part of the gate electrode material layer 108 (refer to Figure 4 ), and the second sacrificial layer 104 (refer to Figure 4 ), exposing the top surface of the first sacrificial layer 103. An initial gate electrode 109 is formed in the opening 106 of the first sacrificial layer 103 and the trench 107 of the silicon oxide layer 102. The initial gate electrode 109 includes a first part and a second part connected to each other. The first part is located in the trench 107, the second part is located above the first part, and a part of the second part covers the top surface of the silicon oxide layer 102 outside the trench 107; refer to Figure 6 , the first sacrificial layer 103 is removed (refer to Figure 5 ). The first sacrificial layer 103 can be removed by an isotropic wet etching process, and the etching solution used in the isotropic wet etching process includes hot phosphoric acid.

[0054] Refer to Figure 7 , using the initial gate electrode 109 as a mask, the silicon oxide layer 102 is etched (refer to Figure 6 ) until the top surface of the silicon carbide substrate 101 is exposed, and a gate dielectric layer 110 covering the bottom surface and side walls of the trench 107 is formed.

[0055] The silicon oxide layer 102 is etched by an anisotropic plasma etching process, and the etching gas used in the anisotropic plasma etching process is CF 4 , CHF 3 , C 4 F 8 or C 4 F 6 or one or more of them, or a mixed gas of any gas or multiple gases in CF 4 , CHF 3 , C 4 F 8 and C 4 F 6 and any gas in O 2 , Ar, CO and He. In a specific embodiment, the etching gas used in the anisotropic plasma etching process includes CF 4 (flow rate range is 20 - 50 sccm), CHF 3(Flow rate range: 10 - 30 sccm), Ar (flow rate range: 50 - 180 sccm), chamber pressure range: 10 - 100 mTorr, source power (ICP) range: 500 - 1400 W, bias power (RF bias) range: 30 - 200 W, which improves the etching selectivity of the oxide layer 103 relative to the silicon carbide substrate 101 (greater than 10:1), making the thickness and position accuracy of the gate dielectric layer 110 formed on the sidewalls of the trench 107 higher. While the morphology of the outer sidewalls is better, it prevents damage to the silicon carbide substrate 101, facilitating the formation of the subsequent epitaxial silicon carbide layer.

[0056] The thickness T1 of the gate dielectric layer 110 on the bottom surface of the trench 107 can be greater than or equal to the thickness T2 of the gate dielectric layer 110 on the side surface of the trench 107, or the thickness T2 of the gate dielectric layer 110 on the side surface of the trench 107 can be less than or equal to the thickness T1 of the gate dielectric layer 110 on the bottom surface of the trench 107. In some embodiments, the range of the thickness T1 of the gate dielectric layer 110 on the bottom surface of the trench 107 is 100 nm - 300 nm, and the range of the thickness T2 of the gate dielectric layer 110 on the sidewall of the trench 107 is 30 nm - 250 nm.

[0057] Reference Figure 8 , an epitaxial silicon carbide layer 111 is formed on the top surface of the silicon carbide substrate 101 outside the gate dielectric layer 110; Reference Figure 9 , part of the epitaxial silicon carbide layer 111 and part of the initial gate electrode 109 are removed (Reference Figure 8 ), until the top surface of the gate dielectric layer 110 is exposed, and the remaining initial gate electrode in the trench 107 serves as the gate electrode 112.

[0058] The epitaxial silicon carbide layer 111 is used to form the drift region and channel region of the trench MOSFET.

[0059] In the epitaxial silicon carbide layer 111, different types of doped ions can be referred to according to the type of the formed trench MOSFET. The type of impurity ions doped in the epitaxial silicon carbide layer 111 is opposite to the type of impurity ions doped in the body region. Specifically, when the type of the trench MOSFET to be formed is N-type, the impurity ions doped in the epitaxial silicon carbide layer 111 are N-type impurity ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions, or antimony ions; when the type of the trench MOSFET to be formed is P-type, the impurity ions doped in the epitaxial silicon carbide layer 111 are P-type impurity ions, and the P-type impurity ions include one or more of boron ions, gallium ions, or indium ions.

[0060] In some embodiments, the epitaxial silicon carbide layer 111 may be formed by an in-situ doping selective epitaxy process.

[0061] In some embodiments, a chemical mechanical polishing process is used to remove part of the epitaxial silicon carbide layer and part of the initial gate electrode until the top surface of the gate dielectric layer is exposed.

[0062] In some embodiments, referring to Figure 10 , it further includes: forming a body region 113 in the epitaxial silicon carbide layer 111 around the gate electrode 112; forming a source region 114 in the body region 113, and the type of impurity ions doped in the source region 114 is opposite to the type of impurity ions doped in the body region 113.

[0063] When the type of the trench MOSFET to be formed is N-type, the type of impurity ions doped in the body region 113 is P-type impurity ions, the impurity ions doped in the source region 114 are N-type impurity ions, the P-type impurity ions include one or more of boron ions, gallium ions or indium ions, and the N-type impurity ions include one or more of phosphorus ions, arsenic ions or antimony ions; when the type of the trench MOSFET to be formed is P-type, the type of impurity ions doped in the body region 113 is N-type impurity ions, and the impurity ions doped in the source region 114 are P-type impurity ions. The body region 113 and the source region 114 are formed by different ion implantation processes.

[0064] In some embodiments, an isolation region 115 may also be formed between adjacent source regions 114. The isolation region 115 is formed by an ion implantation process, and the type of impurity ions doped in the isolation region 115 is opposite to the type of impurity ions doped in the source region 114. Specifically, when the type of impurity ions doped in the source region 114 is N-type impurity ions, the type of impurity ions doped in the isolation region 115 is P-type impurity ions; when the type of impurity ions doped in the source region 114 is P-type impurity ions, the type of impurity ions doped in the isolation region 115 is N-type impurity ions.

[0065] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0066] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0067] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a trench MOSFET, characterized in that: include: Providing a silicon carbide substrate; forming a silicon oxide layer on the top surface of the silicon carbide substrate by a thermal oxidation process; forming a trench in the silicon oxide layer; forming an initial gate electrode in the trench and on a top surface of a portion of the silicon oxide layer outside the trench; Using the initial gate electrode as a mask, etching the silicon oxide layer until the top surface of the silicon carbide substrate is exposed to form a gate dielectric layer covering the bottom surface and sidewalls of the trench; forming an epitaxial silicon carbide layer on the top surface of the silicon carbide substrate outside the gate dielectric layer; A portion of the epitaxial silicon carbide layer and a portion of the initial gate electrode are removed until the top surface of the gate dielectric layer is exposed, and the remaining initial gate electrode in the trench is used as a gate electrode.

2. The method for preparing a trench MOSFET according to claim 1, wherein: Also includes: forming a drain region in the silicon carbide substrate; forming a body region in the epitaxial silicon carbide around the gate electrode; A source region is formed in the body region, and the type of impurity ions doped in the source region and the drain region is opposite to the type of impurity ions doped in the body region.

3. The method for preparing a trench MOSFET according to claim 2, characterized in that: The epitaxial silicon carbide layer is formed by an in-situ doping selective epitaxial process, and the type of impurity ions doped in the epitaxial silicon carbide is opposite to the type of impurity ions doped in the body region.

4. The method for preparing a trench MOSFET according to claim 1 or 2, characterized in that: The process of forming an initial gate electrode on the top surface of the silicon oxide layer in the groove and on the part outside the groove comprises: forming a first sacrificial layer on the top surface of the silicon oxide layer, wherein the material of the first sacrificial layer is different from the material of the silicon oxide layer; forming a second sacrificial layer on the top surface of the first sacrificial layer, wherein the material of the second sacrificial layer is different from the material of the first sacrificial layer; forming a patterned photoresist layer on the top surface of the second sacrificial layer; using the patterned photoresist layer as a mask, sequentially etching the second sacrificial layer, the first sacrificial layer and the silicon oxide layer, forming an opening in the second sacrificial layer and the first sacrificial layer, and forming a gate electrode connected to the opening in the silicon oxide layer. The invention relates to a method for forming a through groove; removing a portion of the width of the first sacrificial layer from a portion of the sidewall of the opening in a direction parallel to the top surface of the first sacrificial layer, so that the width of the opening in the first sacrificial layer becomes larger, and the removed width of the first sacrificial layer is less than or equal to the thickness of the silicon oxide layer below the bottom surface of the groove; forming a gate electrode material layer that fills the groove and the opening and covers the top surface of the second sacrificial layer; removing a portion of the gate electrode material layer and the second sacrificial layer by a chemical mechanical polishing process to expose the top surface of the first sacrificial layer, and forming an initial gate electrode in the opening of the first sacrificial layer and the groove of the silicon oxide layer; and removing the first sacrificial layer.

5. The method for preparing a trench MOSFET according to claim 4, characterized in that: An isotropic wet etching process is used to remove a portion of the width of the first sacrificial layer from a portion of the sidewall of the opening along a direction parallel to the top surface of the first sacrificial layer.

6. The method for preparing a trench MOSFET according to claim 5, characterized in that: The material of the first sacrificial layer includes silicon nitride, silicon oxynitride or silicon nitride carbide, the material of the second sacrificial layer includes silicon oxide, and the material of the gate electrode material layer includes polysilicon.

7. The method for preparing a trench MOSFET according to claim 6, characterized in that: The isotropic wet etching process uses an etching solution including hot phosphoric acid.

8. The method for preparing a trench MOSFET according to claim 1, wherein: The gas used in the thermal oxidation process is oxygen or a mixed gas of oxygen and water vapor, the temperature range of the thermal oxidation process is 1100°C ~ 1400°C, and the time of the thermal oxidation process is greater than or equal to 30 minutes.

9. The method for preparing a trench MOSFET according to claim 1 or 8, characterized in that: The thickness of the silicon oxide layer formed on the top surface of the silicon carbide substrate by the thermal oxidation process is in the range of 300nm-1000nm; after the groove is formed in the silicon oxide layer, the thickness of the silicon oxide layer remaining at the bottom of the groove is in the range of 100nm-300nm; the thickness of the gate dielectric layer at the bottom of the groove is in the range of 100nm-300nm, and the thickness of the gate dielectric layer at the side wall of the groove is in the range of 30nm-250nm.

10. The method for preparing a trench MOSFET according to claim 1 or 2, characterized in that: Using the initial gate electrode as a mask, etching the silicon oxide layer until the top surface of the silicon carbide substrate is exposed by an anisotropic plasma etching process; also including: using a chemical mechanical polishing process to remove part of the epitaxial silicon carbide layer and part of the initial gate electrode until the top surface of the gate dielectric layer is exposed.

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