OIO core particle and AI computing cluster

Abstract

The invention provides an OIO core particle and an AI computing cluster, which are applied to the technical field of photoelectric transmission, and the OIO core particle comprises an optical chip, an electric chip and a micro-control chip or a micro-control application-specific integrated circuit. An optical chip, an electric chip and a control unit are packaged into an OIO core particle, the core particle works independently as an OIO, and the bandwidth and linearity of a system are improved by adopting an analog light and electric equalization technology in the optical chip and the electric chip. And the core particles are applied to a Scale-up network in the node and are used for interconnection between GPUs (Graphics Processing Unit). Compared with a copper cable interconnection scheme, the method has the advantages that the interconnection distance can be greatly increased, and the scale of a Scale-up network for GPU interconnection is expanded; compared with the existing optical module interconnection scheme, the optical module interconnection method has the advantages of low time delay, low power consumption, high bandwidth density and high reliability; the chip particle interconnection can adapt to the diversity requirements of AI chips and systems, and can be integrated into their systems by clients according to their own requirements.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic transmission technologies, and particularly to OIO dies and AI computing clusters. Background Art

[0002] Currently, Artificial Intelligence (AI) has become the focus of social attention. AI has not only attracted the attention of the scientific and technological community but also drawn the attention of the whole society. Due to reasons such as an increasing number of AI participants, more complex models, and more parameters, the market's demand for AI computing clusters is getting higher and higher. Since a GPU (Graphics Processing Unit) can achieve large-scale parallel computing, an AI computing cluster based on GPUs can be realized through the interconnection of the front-end network, the interconnection of the back-end Scale-out network, and the interconnection of the back-end Scale-up network, etc., to achieve large-scale all-round interconnection.

[0003] Among them, the Scale-up network is mainly an interconnection network for inter-chip communication, especially for the interconnection between GPUs. The Scale-up network can achieve direct interconnection between GPU chips, and can achieve pooling and resource sharing between GPUs and storage chips (for example, HBM - High Bandwidth Memory). Expanding the scale of the Scale-up network can greatly improve the computing efficiency of the AI computing power cluster. However, in the prior art, the Scale-up network is limited by the interconnection method between its internal GPUs, resulting in difficulty in expanding the scale of the Scale-up network and limited improvement in the computing efficiency of computing power nodes. Summary of the Invention

[0004] The purpose of this application is to provide OIO dies and an AI computing cluster to solve the above problems existing in the prior art.

[0005] In the first aspect, a first type of OIO die is provided, including:

[0006] An optical chip, the optical chip includes a photodetector and an electro-optic modulator. The photodetector is used to receive an optical signal, and the electro-optic modulator modulates an input optical continuous wave according to an input electrical signal and outputs an optical signal. The electro-optic modulator improves the bandwidth through analog equalization;

[0007] An electrical chip, the electrical chip includes a driver amplifier, a transimpedance amplifier, and an application-specific integrated circuit. The driver amplifier provides a driving signal for the electro-optic modulator, and the transimpedance amplifier amplifies the electrical signal generated by the photodetector; the application-specific integrated circuit includes an analog equalization module for improving the linearity of the driver amplifier and the transimpedance amplifier;

[0008] A microcontroller chip, which is connected to the feedback ends of a photodetector and a photomodulator, and sends control signals to the photodetector and the photomodulator to adjust the output.

[0009] An interposer, on which the optical chip, the electrical chip, and the microcontroller chip are stacked in a die form, and communication between them is achieved through through-silicon vias.

[0010] In an alternative embodiment, the photomodulator includes a traveling-wave electrode and an active region. The traveling-wave electrode is divided into multiple segments of the same length, and each segment of the traveling-wave electrode is loaded with an active region of different capacitance or impedance to form a gradient.

[0011] In an alternative embodiment, the analog equalization module includes multiple equalizers. The driver amplifier and the transimpedance amplifier include multiple cascaded amplification stages, and one equalizer is provided for each amplification stage.

[0012] In an alternative embodiment, the optical chip is disposed on the interposer, and through-silicon vias are provided in the optical chip. The microcontroller chip and the electrical chip are disposed on the optical chip.

[0013] In an alternative embodiment, the electrical chip and the microcontroller chip are disposed on the interposer, and through-silicon vias are provided in the electrical chip. The optical chip is disposed on the electrical chip and the microcontroller chip.

[0014] In a second aspect, a second OIO die is provided, including:

[0015] An optical chip, which includes a photodetector and a photomodulator. The photodetector is used to receive an optical signal, and the photomodulator modulates the optical continuous wave generated by a laser according to an input electrical signal and outputs an optical signal. The bandwidth of the photomodulator is improved through analog equalization.

[0016] An electrical chip, which includes a driver amplifier, a transimpedance amplifier, and an application-specific integrated circuit. The driver amplifier provides a driving signal for the photomodulator, and the transimpedance amplifier amplifies the electrical signal generated by the photodetector. The application-specific integrated circuit includes an analog equalization module and a microcontrol circuit for improving the linearity of the driver amplifier and the transimpedance amplifier. The microcontrol circuit is connected to the feedback ends of the photodetector and the photomodulator, and sends control signals to the photodetector and the photomodulator to adjust the output.

[0017] An interposer, on which the optical chip and the electrical chip are stacked in a die form, and communication between them is achieved through through-silicon vias.

[0018] In an alternative embodiment, the electro-optical modulator includes a traveling-wave electrode and an active region. The traveling-wave electrode is divided into N segments of the same length, and each segment of the traveling-wave electrode is loaded with an active region having different capacitances or impedances to form a gradient.

[0019] In an alternative embodiment, the analog equalization module includes a plurality of equalizers. The driver amplifier and the transimpedance amplifier include a plurality of cascaded amplification stages, and one equalizer is provided for each amplification stage.

[0020] In an alternative embodiment, the optical chip is disposed on the interposer, through-silicon vias are provided in the optical chip, and the electrical chip is disposed on the optical chip.

[0021] In an alternative embodiment, the electrical chip is disposed on the interposer, through-silicon vias are provided in the electrical chip, and the optical chip is disposed on the electrical chip.

[0022] In a third aspect, an AI computing cluster is provided, which includes a plurality of nodes. Each node includes a plurality of GPUs. The nodes are interconnected through a Scale-out network, and the inside of each node is interconnected through a Scale-up network. The GPUs inside each node are interconnected through an optical fiber array and the OIO die of the first aspect or the second aspect, and the optical fiber array is connected to the corresponding OIO die.

[0023] In an alternative embodiment, the OIO die and the corresponding GPU are disposed on the same PCB board, and the OIO die is packaged on the PCB board through a ball grid array.

[0024] In an alternative embodiment, the GUP and the corresponding OIO die are packaged on the same substrate.

[0025] The beneficial effects of the present application are as follows:

[0026] By packaging the optical chip, the electrical chip, and the MCU into an OIO die, and the die works independently as an OIO, the interconnection distance can be greatly increased, the scale of the Scale-up network for GPU interconnection can be expanded, and it has the advantages of low latency, low power consumption, high bandwidth density, and high reliability. The analog optical and electrical equalization technologies are adopted in the optical chip and the electrical chip to improve the system bandwidth and linearity, and the normal operation of high-speed channel transmission can be realized without a DSP. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 Schematic diagram of copper cable interconnection adopted by the traditional Scale-up network in the embodiment of the present application;

[0029] Figure 2 Pluggable optical module interconnection solution adopted by the traditional Scale-up network in the embodiment of the present application;

[0030] Figure 3 Architecture diagram of the AI cluster in the embodiment of the present application;

[0031] Figure 4 Schematic diagram of the backend Scale-up network in the AI cluster in the embodiment of the present application;

[0032] Figure 5 Functional block diagram of one of the OIO dies provided in the embodiment of the present application;

[0033] Figure 6 Equilibrium schematic diagram of the optical chip of the OIO die provided in the embodiment of the present application;

[0034] Figure 7 Equilibrium schematic diagram of the electrical chip of the OIO die provided in the embodiment of the present application

[0035] Figure 8 Bandwidth expansion effect diagram after analog equalization of the optical chip and the electrical chip in the embodiment of the present application;

[0036] Figure 9 One of the package schematic diagrams of the OIO die provided in the embodiment of the present application;

[0037] Figure 10 One of the package schematic diagrams of the OIO die provided in the embodiment of the present application;

[0038] Figure 11 Functional block diagram of one of the OIO dies provided in the embodiment of the present application;

[0039] Figure 12 One of the package schematic diagrams of the OIO die provided in the embodiment of the present application;

[0040] Figure 13 One of the package schematic diagrams of the OIO die provided in the embodiment of the present application;

[0041] Figure 14 Connection schematic diagram between GPUs in the AI computing cluster provided in the embodiment of the present application. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application. Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the ordinary meaning understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second" and similar terms used in the present application do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] To facilitate better understanding of the present application by those skilled in the art, the technical terms involved in the present application will be briefly introduced below.

[0044] The OIO chiplet (Optical Input Output Chiplet) is a chiplet integrated with optical input output (Optical Input Output, OIO) functions. The OIO chiplet uses optical signals for data transmission and has the following advantages: (1) High-speed communication: It provides higher bandwidth than traditional electrical interfaces; (2) Low latency: The OIO chiplet has no signal processing delay, thus greatly reducing the interconnection delay; (3) Low power consumption: It adopts analog signal processing technology, and the power consumption is much lower than that of current optical modules; (4) Modular design: It can be flexibly combined to adapt to different application scenarios and requirements.

[0045] The Scale-up network expands network performance by enhancing the capabilities of network devices or infrastructure. It is an interconnection network for inter-chip communication, which improves the computing power of nodes and the computing efficiency of clusters. The Scale-up network has the following advantages: (1) Improving the performance of a single node: For example, by realizing resource pooling and resource sharing of computing power chips and storage chips, etc., to improve the performance of a single node; (2) Optimizing the network architecture: For example, by improving routing algorithms, protocol stacks, etc., to optimize the network architecture; (3) Integrating more efficient technologies: For example, by using faster network interfaces, more advanced switches, etc., to achieve more efficient data transmission.

[0046] An AI computing cluster is a group of high-performance computer systems specifically designed to accelerate the training and inference of AI models. The AI computing cluster accelerates complex computing tasks on large-scale datasets through parallel processing. The components of an AI computing cluster include: (1) Multiple nodes: Each physical or virtual computing unit in the cluster, including: CPU: Central Processing Unit, responsible for executing general computing tasks; GPU: Graphics Processing Unit, which is good at handling parallel computing tasks and is widely used in the training of deep learning models; TPU: Tensor Processing Unit, a dedicated hardware accelerator designed specifically for machine learning. (2) Memory and storage: High-bandwidth memory (HBM), large-capacity memory (RAM), and fast storage devices (such as SSDs) to support efficient data reading and writing. (3) Interconnect network: Used for high-speed communication between nodes. In this application, the nodes are interconnected through a Scale-out network, and the GPUs are interconnected through a scale-up network using OIO die. (3) Management node: Responsible for the overall management and scheduling of the AI computing cluster, including resource allocation, task scheduling, and monitoring. The workflow of the AI computing cluster includes: (1) Task submission: Users submit AI model training or inference tasks to the cluster management system. (2) Task scheduling: The management system automatically allocates tasks to appropriate nodes for execution based on the current resource usage. (3) Data distribution: Distribute the dataset to each node to ensure that each node can access the required data. (4) Parallel computing: Each node executes the computing task in parallel, using multi-core CPUs, GPUs, or TPUs for acceleration. (5) Result aggregation: After the calculation is completed, the results of each node are aggregated and integrated to form the final output. The AI computing cluster has the following advantages: (1) High efficiency: Significantly shorten the training time through parallel computing and improve the model iteration speed. (2) Scalability: Can flexibly expand the cluster scale according to needs and add more nodes to handle larger computing tasks. (3) Resource sharing: Multiple users or projects can share the same cluster resources, improving resource utilization. (4) Cost-effectiveness: Compared with single-machine configurations, the cluster can complete more computing tasks per unit time, reducing the overall cost. Given the above advantages, AI computing clusters are widely used in the following multiple scenarios: (1) Deep learning model training: Such as large language models (LLMs) like image recognition, natural language processing (NLP), speech recognition, ChatGPT (Chat Generative Pre-trained Transformer), etc. (2) Autonomous driving: Train complex perception and decision-making models to achieve the safety and reliability of autonomous vehicles. (3) Medical image analysis: Analyze medical images through deep learning algorithms to assist doctors in making diagnoses.(4) Financial risk prediction: Using large-scale datasets for risk assessment and market prediction. (5) Natural science research: Complex computational tasks in fields such as climate simulation and astrophysics.

[0047] After introducing the technical terms involved in this application, the application scenarios and design concepts of this application will be briefly introduced next.

[0048] In traditional Scale-up networks, such as Figure 1 shown, GPUs can be interconnected using copper cables. Due to the limited bandwidth of copper cables, the transmission distance is severely restricted, so the distance of copper cable interconnection is limited within a single rack. Since the Scale-up network is spatially confined within a single rack, this causes a significant increase in rack power consumption, posing great difficulties for rack power supply and heat dissipation. The scale of this copper cable-interconnected Scale-up network is difficult to expand, and the improvement of the computing efficiency of the computing nodes achieved thereby is limited. In another type of Scale-up network, such as Figure 2 shown, GPUs can be interconnected using pluggable optical modules through optical fibers. Using optical modules can greatly increase the interconnection distance, enabling cross-rack interconnection of the Scale-up network and expanding the scale of the Scale-up network. However, currently, optical modules are difficult to meet the higher requirements brought about by the improvement of computing efficiency with the Scale-up network in terms of latency, power consumption, and cost. In addition, optical modules are usually located at the edge of the motherboard, occupying a certain amount of space, which may limit the miniaturization design of the system. Figure 1 and Figure 2 shown is the direct interconnection between GPUs. In actual applications, GPUs can also be connected through a switch.

[0049] Therefore, in the embodiments of this application, an OIO die is formed by packaging an optical chip, an electrical chip, and an MCU. The die works independently as an OIO. Compared with the copper cable interconnection solution, it can greatly increase the interconnection distance and expand the scale of the Scale-up network for GPU interconnection. Compared with the existing optical module interconnection solution, it has the advantages of low latency, low power consumption, high bandwidth density, and high reliability; analog optical and electrical equalization technologies are used in the optical chip and electrical chip to improve the system bandwidth and linearity, enabling normal operation of high-speed channel transmission without a DSP.

[0050] In addition, the OIO die provided in the embodiments of this application can be applied in the system architecture of the AI computing cluster shown in Figure 3 shown. As shown in Figure 3 this system can include: a front-end network, a back-end Scale-out network, and GPU servers.

[0051] The front-end network includes multiple interconnected switches ( Figure 3The SW in it is the interface between the AI cluster and the external world, responsible for connecting clients (such as user devices, application servers, or data sources) to the AI cluster. Its main task is to receive input data and return the processing results of the GPU server. It needs to support large-scale data transmission and usually uses high-speed Ethernet technology. It generally has the characteristics of low latency and scalability.

[0052] The backend Scale-out network includes multiple interconnected switches ( Figure 3 the SW in it), mainly used for communication between GPU servers within the AI cluster, especially in distributed training scenarios. Its goal is to achieve high-performance and low-latency data exchange to support large-scale model training. It supports parameter synchronization, gradient update, and data sharing between GPU or CPU servers.

[0053] The AI cluster can include multiple computing nodes, each computing node includes multiple GPU servers, and multiple acceleration chips such as GPUs are connected within a single GPU server through a Scale-up network. The Scale-up network is mainly used to achieve interconnection within the computing node, such as communication between GPUs within a GPU server and communication between GPU servers. As Figure 4 shown, Figure 4 shows the architecture diagram of a single GPU server. The GPU server includes multiple GPUs, multiple CPUs, and multiple NICs (network interface cards). Among them, multiple GPUs are interconnected through the Scale-up network.

[0054] GPU servers are usually used for tasks that require a large amount of parallel computing, such as deep learning. Each GPU has its own computing power, but they need to work in coordination with the CPU and network interface cards. The figure shows multiple GPUs connected to the CPU and then connected to the external network through the network interface card.

[0055] In the embodiments of this application, an OIO die is provided for Scale-up network interconnection. In one embodiment, the OIO die is placed on a PCB board close to the GPU chip. After direct optoelectronic conversion on the board, it is connected to a remote GPU through an optical fiber. In another embodiment, the OIO die and the GPU can be packaged on the same substrate, and externally it appears as an input / output port where the GPU directly emits light.

[0056] The preferred embodiments of this application will be described below in conjunction with the accompanying drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain this application and are not used to limit this application. And without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.

[0057] Figure 5Schematic diagram of an OIO die provided by an embodiment of the present application. As Figure 5 shown, the OIO die includes an optical chip, an electrical chip, and a microcontroller chip.

[0058] Among them, the optical chip (Photonic Integrated Circuit, PIC) integrates multiple optical components onto a single chip. By manufacturing micro-optical devices (such as waveguides, electro-optic modulators, photodetectors, lasers, etc.) on a silicon-based or other material, functions such as the generation, transmission, modulation, and detection of optical signals are realized. And by using optical signals instead of electrical signals for data transmission and processing, it has the characteristics of high bandwidth, low latency, and low power consumption.

[0059] The laser is used as a continuous-wave light source and can be a distributed feedback laser (DFB Laser) or a vertical cavity surface emitting laser (VCSEL). The laser can be built inside the optical chip or can be external. When the laser is external, the laser can be set on the PCB of the GPU corresponding to the OIO die or inserted on the panel of the GPU server, or the laser can be set on the interposer of the OIO die and connected to the optical chip through optical fiber or free-space coupling.

[0060] The waveguide is the core structure of the PIC chip and is used to guide optical signals to propagate inside the chip. Common materials include silicon (Si), silicon nitride (SiN), and indium phosphide (InP).

[0061] The photodetector receives optical signals through the waveguide and the fiber array. Common materials include silicon (Si) and indium gallium arsenide (InGaAs). The beam splitter is used to split the optical signal into multiple outputs, and the coupler is used to couple the optical signal from the optical fiber to the internal waveguide of the chip. The filter realizes the selective transmission of a specific wavelength and is commonly used in wavelength division multiplexing (WDM) systems.

[0062] The electro-optic modulator modulates the continuous optical wave generated by the laser according to the input electrical signal and outputs the optical signal through the fiber array and the waveguide. The continuous optical wave refers to a stable and continuous optical output emitted by a laser or other light source, and its intensity and frequency remain constant within a certain period of time. Different from pulsed light, continuous optical light has no temporal interruption or modulation and is a continuous and stable optical signal.

[0063] In this embodiment, the electro-optic modulator improves the bandwidth through analog equalization. The electro-optic modulator includes a traveling-wave electrode and an active region. The traveling-wave electrode and the active region are two key components in the design of the electro-optic modulator.

[0064] The traveling-wave electrode is a special electrode structure used to transmit radio-frequency signals and ensure that the electrical signal and the optical signal have the same propagation speed in the modulator. It is designed to make the electric field move synchronously with the optical field, thereby improving the modulation efficiency. The radio-frequency signal is input from the outside into the modulator, and through reasonable electrode design, it is ensured that the electric field is evenly distributed in the active region. The propagation speed of the electrical signal is adjusted to be consistent with the group velocity of the optical signal.

[0065] The traveling-wave electrode usually consists of multiple metal strips, forming a microstrip line or a coplanar waveguide. Its length is comparable to the length of the optical waveguide of the modulator to ensure uniform electric field distribution throughout the modulation region. The material is usually gold (Au) or other highly conductive metals. If the propagation speed of the electrical signal does not match the group velocity of the optical signal, it will lead to a decrease in modulation efficiency. The traveling-wave electrode achieves phase velocity matching by adjusting geometric dimensions (such as width, spacing) and material properties.

[0066] The active region is the core region in the electro-optic modulator that modulates the optical signal. It is an optical waveguide made of materials with electro-optic effects (such as lithium niobate LiNbO or silicon-based materials). Under the action of an externally applied electric field, the refractive index of the material is changed, thereby modulating the phase or amplitude of the optical signal. As an optical waveguide, it guides the optical signal to propagate inside the chip. The active region is usually a miniaturized optical waveguide, whose width and height are precisely designed to support the propagation of light in a specific mode. The material selection depends on the application scenario of the modulator. LiNbO has excellent electro-optic effects and is suitable for high-performance modulators. Silicon-based materials have low cost and are compatible with CMOS processes, making them suitable for large-scale production.

[0067] The active region can be regarded as the load of the traveling-wave electrode because it exerts additional capacitance or resistance effects on the electrical signal. The load characteristics will affect the impedance matching and frequency response of the traveling-wave electrode, so an optimized design is required. This embodiment is for the analog equalization optimization of the active region.

[0068] Specifically, as Figure 6 shown, the traveling-wave electrode is evenly divided into N segments, such as 4 - 8 segments, and the length of each segment needs to be less than the microwave wavelength, such as each segment can be λ / 10 - λ / 4. The capacitance or impedance of each segment of the active region changes according to a specific rule, such as exponential decay, to balance the high-frequency loss and phase matching:

[0069] Taking impedance as an example, in this embodiment, the impedance value of the active region of the Nth segment is (100 - N×10)% of that of the first segment.

[0070] There are two methods to change the load of the active region. One is the gradient doping of the active region: controlling the doping concentration of each segment through ion implantation to adjust the capacitance value. The other is to dynamically adjust the electrical properties of the material by local heating or applying a bias voltage. In addition, distributed resistive loads can be connected in series or parallel on the traveling-wave electrode to adjust the equivalent impedance. Besides the above methods of changing the active region structure, the impedance of each segment can also be changed by loading a resistor-capacitor network. For example, metal resistors or other types of resistive elements are integrated at different positions of the traveling-wave electrode. By optimizing the resistance value and distribution position, precise control of the active region load can be achieved, the load characteristics can be flexibly adjusted, and the optical performance will not be significantly affected. A variable capacitor is introduced near the active region, and the bias voltage of the capacitor is dynamically adjusted to change its capacitance value, which is suitable for application scenarios that require dynamic adjustment of the load. The load of the active region can also be adjusted by stacking multiple layers of materials with different characteristics. For example, one or more dielectric layers are added above or below the active region to change the overall dielectric constant. By adjusting the thickness and material parameters of each layer to optimize the load characteristics, more precise load control can be achieved.

[0071] In this embodiment, the load characteristics of the traveling-wave electrode are adjusted in segments to compensate for high-frequency signal attenuation and achieve the flattening of the modulator bandwidth. The larger the number N of segments, the higher the bandwidth equalization resolution of the modulator. The more the load of each stage is reduced compared to the previous stage segment, the more the high-frequency part is lifted.

[0072] The electrical chip includes a driver amplifier, a transimpedance amplifier, and an application-specific integrated circuit. The driver amplifier provides a driving signal for the photoelectric modulator, and the transimpedance amplifier amplifies the electrical signal generated by the photodetector. There are two application-specific integrated circuits. One is for controlling the transimpedance amplifier, and the other is for the driver amplifier.

[0073] The driver amplifier is one of the core components for realizing optical signal modulation. Its main function is to amplify the input electrical signal to a sufficient power level to drive the photoelectric modulator. In the optical chip, the main tasks of the driver amplifier include: amplifying the input low-power electrical signal to the radio frequency power level required to drive the photoelectric modulator or laser; ensuring impedance matching between the output end of the amplifier and the input end of the photoelectric modulator or laser to maximize power transmission and reduce reflection. Providing a flat gain curve to ensure good performance throughout the operating frequency range; reducing nonlinear distortion to avoid adverse effects on the waveform of the modulation signal. In this application, higher gain is achieved through cascading multiple stages of amplifiers. In this application, the driver amplifier and the photoelectric modulator are integrated together through 3D packaging to reduce signal transmission loss and improve overall performance. Compared with the traditional driver amplifier of the optical module, the chip-level driver amplifier has higher bandwidth, linearity, smaller size, and lower power consumption.

[0074] The transconductance amplifier is one of the indispensable core components in the optical receiving system. Its main function is to convert the weak current signal output by the photodetector into a voltage signal and amplify it. A transconductance amplifier is a circuit that converts an input current signal into an output voltage signal. Its core characteristic can be described by transconductance, which is defined as the ratio of the change in output voltage to the change in input current. Ideally, the input impedance of the transconductance amplifier is close to zero to maximize the reception of the current signal output by the photodetector. Similar to the driver amplifier, in this application, the transconductance amplifier uses multiple amplifier units to achieve higher gain and bandwidth.

[0075] The application-specific integrated circuit (ASIC) for transimpedance amplifier control is a specially designed integrated circuit for optimizing and controlling the performance of the transimpedance amplifier. The ASIC for transimpedance amplifier control can dynamically adjust the gain of the transimpedance amplifier to adapt to different input signal strengths. It reduces the gain in the case of strong signals to avoid saturation and increases the gain in the case of weak signals to enhance sensitivity. The bandwidth of the transimpedance amplifier is inversely proportional to its gain, and the ASIC for transimpedance amplifier control can optimize the bandwidth-gain balance according to application requirements. The ASIC for transimpedance amplifier control includes a noise filtering and suppression module to reduce the impact of thermal noise, shot noise, and other interferences on the signal. The ASIC for transimpedance amplifier control provides precise bias voltage or current for the active components in the photodetector and the transimpedance amplifier to ensure their optimal operation.

[0076] The ASIC for driver amplifier is used to optimize and control the performance of the driver amplifier. It can dynamically adjust the gain of the driver amplifier to adapt to different input signal strengths and load requirements. In some application scenarios, it may be necessary to automatically adjust the gain according to real-time conditions, such as temperature or load changes. The bandwidth of the driver amplifier determines the range of signal frequencies it can handle. The ASIC for driver amplifier can ensure good performance of the driver amplifier within the target frequency range by optimizing circuit parameters, such as the feedback network and compensation capacitors. The driver amplifier may introduce nonlinear distortion, affecting the quality of the output signal. The ASIC for driver amplifier includes linearization algorithms or predistortion techniques to reduce nonlinear effects. It provides overvoltage, overcurrent, and electrostatic discharge protection to prevent external interferences or abnormal conditions from damaging the driver amplifier or the load. It provides precise bias voltage or current for the active components in the driver amplifier to ensure its optimal operation.

[0077] In an amplifier circuit, the frequency response characteristic directly affects the signal transmission quality. When the load characteristic changes, it often causes the dual problems of gain decline in the high-frequency band and insufficient gain in the low-frequency band. This non-linear frequency response will cause the bandwidth curve of the output signal to exhibit obvious fluctuation characteristics. In the high-frequency operating state, the parasitic parameters of the amplifier circuit begin to show significant effects. When the load impedance decreases, the cut-off frequency of the low-pass filter network formed by the output capacitance of the transistor and the load impedance will decrease significantly. Taking a typical common-emitter amplifier circuit as an example, its high-frequency gain can be expressed as: Av_HF = -gm(RL||ro) / (1 + jω(Cob + Cμ)RL), where Av_HF represents the high-frequency gain, gm is the transconductance, ro is the output impedance, Cob is the output capacitance, and RL is the load impedance. The main pole frequency fp = 1 / (2πRL(Cob + Cμ)). When the load impedance RL decreases, the main pole frequency will shift to the low frequency, resulting in an earlier roll-off of the high-frequency gain. In addition, the effect of distributed inductance cannot be ignored in the frequency band above MHz. The resonant circuit formed by the parasitic inductance of the load wire (about 1 - 10 nH / cm) and the distributed capacitance of the circuit board may cause abnormal fluctuations in the gain curve.

[0078] In the low-frequency band (usually <1 kHz), the capacitive reactance of the coupling capacitor increases significantly, resulting in an increase in the effective impedance of the signal path. For an amplifier circuit using RC coupling, the low-frequency cut-off frequency is determined by the following formula: fL = 1 / (2π(Ro + RL)Cc), where fL is the low-frequency cut-off frequency, Ro is the output impedance of the previous stage, and Cc is the coupling capacitor. When RL decreases, the equivalent series impedance decreases, causing the low-frequency cut-off frequency to shift to the high frequency, resulting in a decrease in the effective low-frequency gain.

[0079] To improve the above frequency response, in this embodiment, an analog equalization circuit is provided in both the dedicated integrated circuit for transimpedance amplifier control and the dedicated integrated circuit for driver amplifier. Specifically, an equalizer is provided in each amplification stage of the driver amplifier and the transimpedance amplifier. Figure 7 For the equalization principle of the amplifier circuit, the equalizer R CTLE and the equalizer C CTLE can be used to adjust its gain bandwidth. The goal of equalization control in this embodiment is to adjust the signal gain in different frequency ranges so that the overall bandwidth curve tends to be flat. Through equalization control of each different stage of the amplifier, the bandwidth curves of different loads can be compensated to obtain a relatively flat and desired bandwidth and curve.

[0080] The equalizer R CTLE is composed of a resistor and a capacitor and is usually used to compensate for the loss in the transmission line. In the high-frequency band, the impedance of the capacitor is low, allowing more high-frequency signals to pass through. In the low-frequency band, the resistor plays a dominant role, restricting the gain of the low-frequency signals. R CTLEImprove the high-frequency gain and expand the bandwidth of the amplifier. Compensate for the insertion loss in the transmission line. Equalizer C CTLE Achieve signal equalization through capacitive coupling. Equalizer C CTLE Utilize the frequency-selective characteristics of the capacitor to enhance the gain of high-frequency signals. Equalizer C CTLE Reduce the gain of low-frequency signals to avoid overload or distortion. Optimize the transmission characteristics of high-frequency signals to improve the linearity and stability of the amplifier.

[0081] Figure 8 Shows the bandwidth expansion effect of the optical chip and the electrical chip after adopting the equalization technology. It can be seen from this figure that the equalization of the optical chip and the electrical chip mainly improves the response at high frequencies, thereby increasing the bandwidth of the system, enabling the chiplet to operate without a digital signal processor (DSP), and greatly reducing the power consumption, cost, and latency of the optical interconnection.

[0082] The microcontroller chip is connected to the feedback terminals of the photodetector and the electro-optic modulator, and sends control signals to the photodetector and the electro-optic modulator to adjust the output. The microcontroller chip is responsible for managing and coordinating the operation of the entire chiplet. The microcontroller chip is also responsible for controlling the operating states of the laser, modulator, and detector to ensure high-quality signal transmission. Through real-time monitoring and adjustment, compensate for the performance degradation caused by temperature changes or aging effects. The microcontroller chip and the transimpedance amplifier control the application-specific integrated circuit for driving the amplifier, and the application-specific integrated circuit can achieve complementary functions.

[0083] Such as Figure 9 and Figure 10As shown in the figure, the 3D packaging technology is adopted in this embodiment. 3D packaging is a technology that stacks multiple chips (such as processors, memories, sensors, etc.) together and realizes communication between chips through vertical interconnection technology. It breaks through the limitations of traditional planar layouts, making the distance between chips shorter, thereby reducing signal transmission latency and improving overall performance. The optical chip 1, the electrical chip 3, and the microcontroller chip 2 are stacked on the interposer 4 in the form of bare dies, and communication with each other is achieved through through-silicon vias 5. A bare die refers to an unpackaged chip that directly exposes its circuit structure. As a basic building unit, the unpackaged characteristics of the bare die bring significant advantages: the thickness can be controlled within 50 - 200μm, reducing the volume by 90% compared with traditional packaged chips; the signal transmission path is shortened to the micron level, reducing power consumption losses caused by parasitic effects by 30 - 50%. Stacking in the form of bare dies in this embodiment can minimize the additional volume and power consumption brought by packaging. The interposer 4, as the nerve center of 3D packaging, uses silicon-based or glass-based materials to achieve high-density wiring. Taking the TSMC CoWoS technology as an example, the interposer with a 65nm process can achieve a wiring density of 1μm / 1μm for line width / line pitch and integrate more than 10,000 through-silicon via channels. In this embodiment, the interposer 4 is used to carry multiple bare dies and provide a high-density interconnection network. Through-silicon via technology allows direct electrical connection when bare dies are stacked, significantly shortening the signal path and reducing latency. Bumps 6 are also provided between the optical chip 1 and the electrical chip 3 for connection. Bumps 6 are one of the important structures for realizing inter-chip interconnection. They are used for electrical and mechanical connections between chips at different levels or between chips and the interposer and the substrate. The interposer 4 can be packaged on the PCB board through ball grid array packaging 7. The label 8 in the figure represents the fiber array.

[0084] Here, there are two packaging methods. The first one is as Figure 9 shown, the optical chip 1 is arranged on the interposer 4, through-silicon vias are arranged in the optical chip 1, and the microcontroller chip 2 and the electrical chip 3 are arranged on the optical chip 1.

[0085] The second one is as Figure 10 shown, the electrical chip 3 and the microcontroller chip 2 are arranged on the interposer 4, through-silicon vias are arranged in the electrical chip 3, and the optical chip 1 is arranged on the electrical chip and the microcontroller chip.

[0086] Communication between chips in the same plane is achieved through metal interconnect lines on the interposer. Vertical signal transmission between stacked chips is achieved through through-silicon vias (TSVs).

[0087] By manufacturing through-conductive channels in a silicon wafer or chip to directly connect the stacked chips, the signal transmission efficiency and system integration can be significantly improved. By vertically stacking chips, the overall size of the system can be greatly reduced. The signal transmission path is shortened, and parasitic effects and energy losses are reduced.

[0088] Figure 11 Another schematic diagram of the OIO die provided by the embodiment of the present application. Its basic structure is basically the same as that of the first OIO die. The difference is that the microcontroller unit is integrated inside the electrical chip in the form of an application-specific integrated circuit, and further can be integrated inside the driver amplifier and integrated into the application-specific integrated circuit for driving amplifier control. In this architecture, the application-specific integrated circuit is used to implement fixed control logic or algorithms, such as bandwidth equalization, temperature compensation, or bias control of the modulator.

[0089] Although the MCU is programmable, in some scenarios, using an application-specific integrated circuit has more advantages:

[0090] High performance: The application-specific integrated circuit is optimized for specific tasks and runs faster.

[0091] Low power consumption: The circuit design of the application-specific integrated circuit is more efficient and has lower power consumption.

[0092] High reliability: The fixed functions of the application-specific integrated circuit reduce the possibility of software errors.

[0093] Small size: The highly integrated characteristics of the application-specific integrated circuit can significantly reduce the chip area.

[0094] Once the application-specific integrated circuit is designed, it cannot be changed, so it needs to be customized for each optical modulator.

[0095] The optical chip and the electrical chip are stacked on the interposer in the form of bare dies, and communicate with each other through through-silicon vias.

[0096] Here, 3D packaging technology is adopted. The optical chip and the electrical chip are stacked on the interposer in the form of bare dies, and communicate with each other through through-silicon vias.

[0097] Similarly, there are also two packaging methods here. The first one is as Figure 12 shown. The optical chip is arranged on the interposer, through-silicon vias are arranged in the optical chip, and the microcontroller chip and the electrical chip are arranged on the optical chip.

[0098] The second one is as Figure 13 shown. The electrical chip and the microcontroller chip are arranged on the interposer, through-silicon vias are arranged in the electrical chip, and the optical chip is arranged on the electrical chip and the microcontroller chip.

[0099] Corresponding to the above OIO die, the embodiment of the present application also provides an AI computing cluster, which includes multiple nodes. Each node includes multiple GPUs, CPUs, and dedicated interfaces. The schematic diagram inside the node is as Figure 2As shown in the figure. The nodes are interconnected through a Scale-out network, and the internal of the nodes are interconnected through a Scale-up network. The GPUs inside the nodes are interconnected through an optical fiber array and the above-mentioned OIO die, and the optical fiber array is connected to the corresponding OIO die.

[0100] Regarding the connection method between the OIO chip and the optical fiber, a direct coupling method can be adopted. The optical fiber is directly physically coupled to the optical module or optical component on the OIO chip, without an additional pluggable interface. At the chip packaging stage, the optical fiber is aligned with the optical waveguide or optical transceiver on the chip with micron-level or nanometer-level precision. The optical fiber is permanently connected to the chip using gluing, soldering or other fixing techniques. Direct coupling can reduce the reflection and scattering of signals at the interface, thereby reducing transmission loss. High reliability, no moving parts, reducing the possibility of mechanical failure. Compact design: No additional interface hardware is required, saving space.

[0101] As Figure 14 shown in the figure, the OIO die and the corresponding GPU can be set on the same PCB board, and the OIO die is packaged on the PCB board through a ball grid array. In this architecture, the OIO die is placed on the PCB board close to the GPU to reduce the loss and delay on the signal transmission path. The high-speed optical signal transmission ability of the OIO die combined with the powerful computing ability of the GPU realizes higher data throughput and lower latency, improving the overall performance of the system. Integrating the OIO die and the GPU on the same PCB board reduces the number of external connectors and cables, simplifies the system design, and reduces the manufacturing cost. By optimizing the PCB wiring and heat dissipation design, the reliability and stability of the system are improved, and the service life is extended.

[0102] In addition, the GUP and the corresponding OIO die can also be packaged on the same substrate. The OIO die and the GPU are placed on the same silicon interposer and interconnected through high-density metal interconnects. From the outside, OIO is the input / output port where the GPU directly emits light, which is a highly integrated design solution. This architecture not only improves the compactness of the system, but also further optimizes the efficiency and performance of data transmission.

[0103] Compared with the copper cable interconnection solution, the OIO die and the AI computing cluster provided in the embodiments of the present application can greatly increase the interconnection distance and expand the scale of the Scale-up network for GPU interconnection; compared with the existing optical module interconnection solution, it has the advantages of low latency, low power consumption, high bandwidth density, and high reliability; the OIO die can adapt to the diverse needs of AI chips and systems and can be integrated into their systems by customers according to their own needs, such as NPO (Near-Packaged Optics) or CPO (Co-Packaged Optics) systems, thereby improving the computing efficiency.

[0104] It should be noted that although several units or subunits of the device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present application, the features and functions of two or more of the above-described units may be embodied in one unit. Conversely, the features and functions of one unit described above may be further divided and embodied by multiple units.

[0105] Obviously, those skilled in the art can make various changes and modifications to the embodiments in the embodiments of the present application without departing from the spirit and scope of the embodiments in the embodiments of the present application. Thus, if these modifications and variations of the embodiments in the embodiments of the present application fall within the scope of the claims of the embodiments in the present application and their equivalent technologies, the embodiments in the present application are also intended to include these changes and modifications.

Claims

1. An OIO core particle, characterized in that: include: An optical chip, the optical chip comprising a photodetector and an optoelectronic modulator, the photodetector being used to receive an optical signal, the optoelectronic modulator modulating an input optical continuous wave according to an input electrical signal and outputting an optical signal, the optoelectronic modulator increasing bandwidth by analog equalization; An electrical chip, the electrical chip comprising a driving amplifier, a transimpedance amplifier and a dedicated integrated circuit, the driving amplifier providing a driving signal for the photoelectric modulator, the transimpedance amplifier amplifying the electrical signal generated by the photodetector; the dedicated integrated circuit comprising an analog equalization module for improving the linearity of the driving amplifier and the transimpedance amplifier; A microcontroller chip, wherein the microcontroller chip is connected to the feedback ends of the photodetector and the photoelectric modulator, and sends a control signal to the photodetector and the photoelectric modulator to adjust the output; The optical chip, the electric chip and the microcontroller chip are stacked on the intermediary layer in a bare crystal manner and communicate with each other through silicon vias.

2. The OIO core particle according to claim 1, characterized in that: The photoelectric modulator comprises a traveling wave electrode and an active area. The traveling wave electrode is divided into a plurality of sections with the same length. Each section of the traveling wave electrode is loaded with an active area with different capacitance or impedance to form a gradient.

3. The OIO core particle according to claim 2, characterized in that: The analog equalization module includes a plurality of equalizers, and the driving amplifier and the transimpedance amplifier include a plurality of cascaded amplifier stages, each of which is provided with an equalizer.

4. The OIO core particle according to claim 2, characterized in that: The optical chip is arranged on the intermediate layer, a through silicon via is arranged in the optical chip, and the microcontroller chip and the electric chip are arranged on the optical chip.

5. The OIO core particle according to claim 2, characterized in that: The electric chip and the microcontroller chip are arranged on the intermediate layer, a through silicon via is arranged in the electric chip, and the optical chip is arranged on the electric chip and the microcontroller chip.

6. An OIO core particle, characterized in that: include: An optical chip, the optical chip comprising a photodetector and a photoelectric modulator, the photodetector is used to receive an optical signal, the photoelectric modulator modulates an input optical continuous wave according to an input electrical signal and outputs an optical signal, and the photoelectric modulator increases bandwidth by analog equalization; An electrical chip, the electrical chip comprising a driving amplifier, a transimpedance amplifier and a dedicated integrated circuit, the driving amplifier providing a driving signal for the photoelectric modulator, the transimpedance amplifier amplifying the electrical signal generated by the photoelectric detector; the dedicated integrated circuit comprising a microcontroller circuit and an analog equalizer module for improving the linearity of the driving amplifier and the transimpedance amplifier, the microcontroller circuit connecting the feedback end of the photoelectric detector and the photoelectric modulator, and sending a control signal to the photoelectric detector and the photoelectric modulator to adjust the output; The optical chip and the electrical chip are stacked on the intermediary layer in a bare crystal manner and communicate with each other through silicon vias.

7. The OIO core particle according to claim 6, characterized in that: The photoelectric modulator comprises a traveling wave electrode and an active area. The traveling wave electrode is divided into a plurality of sections with the same length. Each section of the traveling wave electrode is loaded with an active area with different capacitance or impedance to form a gradient.

8. The OIO core particle according to claim 7, characterized in that: The analog equalization module includes a plurality of equalizers, and the driving amplifier and the transimpedance amplifier include a plurality of cascaded amplifier stages, each of which is provided with an equalizer.

9. The OIO core particle according to claim 7, characterized in that: The optical chip is arranged on the intermediate layer, a through silicon via is arranged in the optical chip, and the electrical chip is arranged on the optical chip.

10. The OIO core particle according to claim 6, characterized in that: The electric chip is arranged on the intermediate layer, a through silicon via is arranged in the electric chip, and the optical chip is arranged on the electric core.

11. An AI computing cluster, comprising a plurality of nodes, each node comprising a plurality of GPUs, the nodes being interconnected via a scale-out network, and the nodes being interconnected via a scale-up network, characterized in that: The GPUs inside the node are interconnected via an optical fiber array and the OIO core particles as described in any one of claims 1 to 10, and the optical fiber array is connected to the corresponding OIO core particles.

12. The AI ​​computing cluster according to claim 11, wherein: The OIO core and the corresponding GPU are arranged on the same PCB board, and the OIO core is packaged on the PCB board through a ball grid array.

13. The AI ​​computing cluster of claim 11, wherein: The GPU and the corresponding OIO core are packaged on the same substrate.

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