Kernel control method and device and electronic equipment

Abstract

The invention provides a kernel control method and device and electronic equipment. Relates to the technical field of inner cores. The method comprises the following steps: acquiring inner core state information of an inner core under the condition of processing a current thread; determining a target running state of the kernel in response to the condition that the kernel state information meets a set control condition or a running control instruction for the kernel is received; the target operation state comprises a target operation state of a power domain and / or a target operation state of a clock domain of the kernel; the power consumption corresponding to the target operation state is smaller than the power consumption of the kernel in a normal operation state; and determining an adjustment signal corresponding to the kernel based on the target operation state, and sending the adjustment signal to a power domain and / or a clock domain of the kernel so as to control the operation state of the kernel. According to the invention, the fineness of power consumption management can be improved, and the flexibility of kernel control in a low power consumption mode can be improved.

Description

Technical Field

[0001] This application relates to the field of kernel technologies, and in particular, to a kernel control method, apparatus, and electronic device. Background Art

[0002] In current kernel control methods, power state switching is usually based on a fixed state, lacking dynamic monitoring and adjustment of the real-time state of the kernel. In terms of clock control, although existing methods can adjust the clock frequency according to task requirements, power consumption waste may still occur in low-load scenarios. There are problems in existing kernel control methods that power consumption management is not fine enough and the flexibility of kernel control in the low-power mode is poor. Summary of the Invention

[0003] Embodiments of this application provide a kernel control method, apparatus, and electronic device.

[0004] According to a first aspect of this application, a kernel control method is provided. The method includes: obtaining kernel state information of a kernel when processing a current thread; determining a target operating state of the kernel in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel; the target operating state includes a target operating state of a power domain of the kernel and / or a target operating state of a clock domain of the kernel; the power consumption corresponding to the target operating state is less than the power consumption of the kernel in a normal operating state; determining an adjustment signal corresponding to the kernel based on the target operating state, and sending the adjustment signal to the power domain and / or clock domain of the kernel to control the operating state of the kernel.

[0005] According to an embodiment of this application, the obtaining kernel state information of the kernel when processing the current thread includes: obtaining the usage frequency and cache hit situation of the kernel when processing the current thread; in the case of processing the current thread, obtaining instruction type information of an executed instruction from a decoding stage corresponding to the kernel; determining the kernel state information based on the usage frequency, cache hit situation, and instruction type information.

[0006] According to an embodiment of this application, the determining the target operating state of the kernel includes at least one of the following: determining a target operating state of the power domain of the kernel based on the kernel state information or the running control instruction; the power domain at least includes a main domain, a security domain, a storage domain, and an always-on domain; determining a target operating state of the clock domain of the kernel based on the kernel state information or the running control instruction; the clock domain at least includes a main clock domain, a data transfer clock domain, a computing clock domain, a debugging domain, and an always-on clock domain.

[0007] According to an embodiment of the present application, determining the target operating state of the power domain of the kernel includes at least one of the following: determining the power switch states of the respective domains included in the power domain based on the power switch signals included in the operation control instruction; determining the voltage states of the respective domains included in the power domain based on the voltage control signals included in the operation control instruction; determining the power switch states of the respective domains included in the power domain based on the register information included in the kernel state information.

[0008] According to an embodiment of the present application, determining the target operating state of the clock domain of the kernel includes at least one of the following: determining the clock switch states of the respective domains included in the clock domain based on the clock switch signals included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the clock frequency control signals included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the kernel state information obtained according to a set operation period.

[0009] According to an embodiment of the present application, the kernel state information includes the usage frequency of the kernel, the cache hit situation, and instruction type information. Determining the clock frequency states of the respective domains included in the clock domain based on the kernel state information obtained according to a set operation period includes at least one of the following: in response to the usage frequency of the kernel obtained according to a set first operation period satisfying a set frequency threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; in response to the cache hit situation obtained according to a set second operation period satisfying a set hit rate threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; determining the first instruction quantity of the vector type calculation instructions included in the instruction type information obtained according to a set third operation period, and adjusting the clock frequencies of the respective domains included in the clock domain based on the first instruction quantity to obtain corresponding clock frequency states; determining the second instruction quantity of the floating-point type calculation instructions included in the instruction type information obtained according to a set fourth operation period, and adjusting the clock frequencies of the respective domains included in the clock domain based on the second instruction quantity to obtain corresponding clock frequency states.

[0010] According to an embodiment of the present application, the method further includes: in response to the completion of the execution of the current thread, storing the target address information and the target operating state corresponding to the current thread in a history information table; adjusting the kernel from the target operating state to a normal operating state; in response to the address information of the next thread matching the target address information, determining the corresponding target operating state from the history information table; based on the determined target operating state, determining an adjustment signal corresponding to the kernel, and sending the adjustment signal to the power domain and / or clock domain of the kernel to control the operating state of the kernel.

[0011] According to a second aspect of the present application, there is provided a kernel control device, the device including: an acquisition module for acquiring kernel state information of a kernel when processing a current thread; a determination module for determining a target operating state of the kernel in response to the kernel state information satisfying a set control condition or receiving an operation control instruction for the kernel; the target operating state including a target operating state of a power domain and / or a clock domain of the kernel; the power consumption corresponding to the target operating state being less than the power consumption of the kernel in a normal operating state; a control module for determining an adjustment signal corresponding to the kernel based on the target operating state and sending the adjustment signal to the power domain and / or clock domain of the kernel to control the operating state of the kernel.

[0012] According to an embodiment of the present application, the acquisition module is used to: acquire the usage frequency and cache hit situation of the kernel when processing the current thread; in the case of processing the current thread, acquire instruction type information of the executed instructions from the decoding stage corresponding to the kernel; based on the usage frequency, cache hit situation, and instruction type information, determine the kernel state information.

[0013] According to an embodiment of the present application, the determination module is used for at least one of the following: determining a target operating state of the power domain of the kernel based on the kernel state information or the operation control instruction; the power domain at least includes a main domain, a security domain, a storage domain, and a always-on domain; determining a target operating state of the clock domain of the kernel based on the kernel state information or the operation control instruction; the clock domain at least includes a main clock domain, a data transfer clock domain, a calculation clock domain, a debug domain, and a always-on clock domain.

[0014] According to an embodiment of the present application, the determination module is used for at least one of the following: determining the power switch state of each domain included in the power domain based on the power switch signal included in the operation control instruction; determining the voltage state of each domain included in the power domain based on the voltage control signal included in the operation control instruction; determining the power switch state of each domain included in the power domain based on the register information included in the kernel state information.

[0015] According to an embodiment of the present application, the determining module is configured to perform at least one of the following: determining the clock switching states of the respective domains included in the clock domain based on the clock switching signal included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the clock frequency control signal included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the kernel state information obtained according to a set operation period.

[0016] According to an embodiment of the present application, the kernel state information includes the usage frequency of the kernel, the cache hit situation, and instruction type information, and the determining module is configured to perform at least one of the following: in response to the usage frequency of the kernel obtained according to a set first operation period satisfying a set frequency threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; in response to the cache hit situation obtained according to a set second operation period satisfying a set hit rate threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; determining a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to a set third operation period, and based on the first instruction quantity, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; determining a second instruction quantity of floating-point type calculation instructions included in the instruction type information obtained according to a set fourth operation period, and based on the second instruction quantity, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states.

[0017] According to an embodiment of the present application, the device further includes a storage module, and the storage module is configured to: in response to the completion of the execution of the current thread, storing the target address information and the target operation state corresponding to the current thread in a historical information table; adjusting the kernel from the target operation state to the normal operation state; in response to the address information of the next thread matching the target address information, determining the corresponding target operation state from the historical information table; based on the determined target operation state, determining an adjustment signal corresponding to the kernel, and sending the adjustment signal to the power domain and / or the clock domain of the kernel to control the operation state of the kernel.

[0018] According to a third aspect of the present application, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the present application.

[0019] The method of the embodiment of the present application obtains the kernel state information of the kernel when processing the current thread; in response to the kernel state information satisfying the set control condition or receiving a running control instruction for the kernel, determines the target running state of the kernel; the target running state includes the target running state of the power domain and / or the clock domain of the kernel; the power consumption corresponding to the target running state is less than the power consumption of the kernel in the normal running state; determines an adjustment signal corresponding to the kernel based on the target running state, and sends the adjustment signal to the power domain and / or the clock domain of the kernel to control the running state of the kernel. In this way, the precision of power consumption management can be improved and the flexibility of kernel control in the low-power mode can be enhanced.

[0020] It should be understood that the teachings of the present application do not require achieving all the beneficial effects described above. Instead, specific technical solutions can achieve specific technical effects, and other embodiments of the present application can also achieve beneficial effects not mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] By referring to the accompanying drawings and reading the following detailed description, the above and other objects, features, and advantages of the exemplary embodiments of the present application will become readily understood. In the drawings, several embodiments of the present application are shown in an exemplary rather than restrictive manner, wherein: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0022] Figure 1 Shows the processing flow diagram of the kernel control method provided by the embodiment of the present application Figure 1 ; Figure 2 Shows the processing flow diagram of the kernel control method provided by the embodiment of the present application Figure 2 ; Figure 3 Shows the processing flow diagram of the kernel control method provided by the embodiment of the present application Figure 3 ; Figure 4 Shows the processing flow diagram of the kernel control method provided by the embodiment of the present application Figure 4 ; Figure 5 Shows the application scenario of the kernel control method provided by the embodiment of the present application Figure 1 ; Figure 6 Shows the application scenario of the kernel control method provided by the embodiment of the present application Figure 2 ; Figure 7 Shows the application scenario of the kernel control method provided by the embodiment of the present application Figure 3; Figure 8 Shows the application scenario of the kernel control method provided by the embodiments of the present application Figure 4 ; Figure 9 Shows an optional schematic diagram of the kernel control device provided by the embodiments of the present application; Figure 10 Shows an optional schematic diagram of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0023] To make the objectives, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0024] In the following descriptions, "some embodiments" are involved, which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0025] In the following descriptions, the terms "first / second" involved are only used to distinguish similar objects, and do not represent a specific order for the objects. It can be understood that "first / second" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0027] Before further elaborating on the embodiments of the present application, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0028] CSR (Control and Status Registers): CSR in the RISC-V architecture are registers used to configure and record the operating status of the processor. CSR registers are located inside the processor core, using an independent address encoding space, which is independent of the address range for memory addressing. There are a wide variety of CSR registers, which can be classified into different categories, including but not limited to: registers related to processor information, registers related to interrupt configuration, registers related to exception handling, registers related to memory protection, registers related to performance statistics, registers related to debug interfaces, etc.

[0029] WFI (Wait For Interrupt) instruction: The WFI instruction in the RISC-V architecture is an instruction used to implement a low-power state. When the processor executes the WFI instruction, it pauses the current instruction execution flow and enters a low-power waiting state until the next interrupt or triggering event occurs. This state is usually referred to as the "sleep" state, and the power consumption of the CPU drops to the lowest level in this state. The WFI instruction is often used as a standby instruction for energy saving and power consumption optimization, allowing the processor to reduce energy consumption while waiting for tasks.

[0030] PC (Program Counter): In computer architecture, the kernel uses the program counter to track the address of the next instruction to be executed. The PC is a special register that holds the address of the instruction in memory, which will be fetched and executed by the execution unit of the processor. In the RISC-V architecture, the PC register is used to retrieve instructions from the Instruction Cache (I-Cache).

[0031] Offset: The address space provided by the operating system for each process is called the virtual address. By paging, the virtual address is divided into fixed-size units. For virtual addresses in the same page, the high bits are the same, and the low bits can be used to represent the offset within the page, which is called Offset here.

[0032] Decode stage: In computer architecture, the instruction decode stage is a key step in the processor's instruction execution cycle. This stage occurs after the fetch stage and before the execute stage. The main task of the decode stage is to convert the instruction fetched from memory into control signals that the processor can understand and execute.

[0033] PLL (Phase-Locked Loop): It is an electronic circuit whose core function is to generate an output signal that maintains a constant phase relationship with the input signal (reference signal). PLLs are widely used in fields such as clock synchronization, frequency synthesis, signal recovery, and modulation and demodulation.

[0034] Cache: It is a component in a computer system used to reduce the average time required for the processor to access memory. The cache is located in the memory hierarchy, between the processor and the main memory. The main purpose of the cache is to alleviate the difference in speed between the processor and the memory, as the processor is generally much faster than the memory.

[0035] The processing flow in the kernel control method provided by the embodiments of this application will be described. Refer to Figure 1 , Figure 1 is a schematic diagram of the processing flow of the kernel control method provided by the embodiments of this application Figure 1 , and will be described in combination with Figure 1 the steps S101 - S103 shown.

[0036] Step S101, obtain the kernel state information of the kernel when processing the current thread.

[0037] In some embodiments, the kernel may include: the kernel of a processor under the RISC-V architecture. The current thread may include an instruction sequence that the kernel is processing or about to process. Specifically, when the kernel executes a program, the kernel processes multiple threads according to a certain scheduling policy, and the current thread refers to the thread that is currently being executed by the kernel or occupying kernel resources for processing. The kernel can process the instructions in the current thread in a pipelined manner. The kernel state information may include: information that reflects the current operating status of the kernel when processing the current thread. The kernel state information may specifically include information such as the usage frequency of the kernel, the instruction type information of the executed instructions, and the cache hit situation. Among them, the usage frequency of the kernel and the cache hit situation can be obtained from the CSR register, and the instruction type information of the executed instructions can be obtained from the decoding module.

[0038] Step S102, in response to the kernel state information satisfying the set control conditions, or receiving a running control instruction for the kernel, determine the target running state of the kernel; the target running state includes the target running state of the power domain of the kernel and / or the target running state of the clock domain; the power consumption corresponding to the target running state is less than the power consumption of the kernel in the normal running state.

[0039] In some embodiments, the control conditions may include: pre-set conditions for determining whether to adjust the kernel operating state. The operation control instructions may include: instructions received from the outside for controlling the kernel operating state. Specific operation control instructions may include: operation control instructions such as the RISC-V WFI instruction and the SoC low-power regulation instruction. The target operating state may include: the kernel's desired operating state determined according to the kernel state information or the operation control instructions. The power consumption of the kernel in the target operating state is lower than that in the normal operating state of the kernel. The target operating state may specifically include the target operating states of the power domain and / or the clock domain of the kernel. The embodiments of the present application do not limit the specific target operating state. The power domain may include: different power regions divided in the kernel architecture. Specific power domains may be divided into a main domain, a security domain, a storage domain, and an always-on domain, etc., and independent power switch control and voltage control can be performed on each domain in the power domain. The clock domain may include: different clock regions divided in the kernel architecture. Specific clock domains may be divided into a main clock domain, a data transfer clock domain, a computing clock domain, a debug domain, and an always-on clock domain, etc., and independent clock frequency and clock switch control can be performed on each domain in the clock domain.

[0040] Step S103, determine the adjustment signal corresponding to the kernel based on the target operating state, and send the adjustment signal to the power domain and / or the clock domain of the kernel to control the operating state of the kernel.

[0041] In some embodiments, the adjustment signal may include: a signal for adjusting the operating state of the kernel power domain and / or the clock domain generated according to the target operating state. The adjustment signal may be generated by a power domain status table and / or a clock domain status table maintained inside the monitoring and regulation unit. The power domain status table and the clock domain status table record information such as the current state and the target state of each power domain and clock domain. When it is necessary to adjust the operating state of the kernel, the monitoring and regulation unit determines the target operating state according to the kernel state information or the operation control instructions, and then obtains the corresponding information from the corresponding power domain status table and / or clock domain status table to generate the adjustment signal. The power domain status table may include information such as the power domain identifier, status, and valid bit. The clock domain status table may include information such as the clock domain identifier, status, and valid bit. Sending these adjustment signals to the corresponding power domain and / or clock domain can achieve the control of the kernel operating state.

[0042] The method of the embodiment of the present application effectively implements the RISC-V WFI low-power instruction by reasonably dividing the clock domain and power domain, enabling the kernel to retain necessary states in the shallow low-power state, and dynamically adjusting the power-off range, clock-off area, and reducing the clock frequency according to actual needs, thereby achieving refined power consumption control and improving system energy efficiency. At the same time, the monitoring and regulation unit can perform fine-grained internal clock frequency regulation on the computing unit, L2 Cache, and bus. Automatically reducing the frequency of use of fewer logic units at the hardware level effectively shares the regulation pressure of the overall PMU (Power Management Unit), making power consumption management more efficient and flexible. In addition, the kernel control method supports software shutdown of the security unit, can flexibly adjust the operating state of the security unit according to different application scenario requirements, and takes into account power consumption optimization while ensuring system security. Moreover, the low-power mode regulation mechanism based on the thread situation can record the low-power state in a timely manner after the current thread ends. When encountering a similar scenario next time, it can quickly restore to the corresponding low-power state, significantly reducing the delay of power consumption control and improving the response speed and energy efficiency performance of the system.

[0043] In some embodiments, the processing flow of the kernel control method is schematically shown Figure 2 , as Figure 2 shown, obtaining the kernel state information of the kernel when processing the current thread in step S101 may include: Step S201, obtaining the usage frequency and cache hit situation of the kernel when processing the current thread.

[0044] In this embodiment, the usage frequency may include: how many cycles and instructions have been run in total since the CPU reset obtained from the CSR register (cycle and instret counters) every fixed clock cycle. The usage frequency can be used to determine the current load situation of the kernel. The cache hit situation may include: the ratio of the number of times the required data or instruction is successfully obtained from the cache to the total number of accesses when the kernel accesses data or instructions. Specifically, the cache hit situation can be obtained and counted from the LSU (Load / Store Unit) and D-Cache. The cache hit situation can be used to evaluate the usage efficiency of the cache.

[0045] Step S202, obtaining the instruction type information of the executed instruction from the decoding stage corresponding to the kernel when processing the current thread.

[0046] In this embodiment, the instruction type information may include the types of instructions executed by the kernel when processing the current thread. Specifically, the instruction type information may include types such as vector calculation instructions and floating-point calculation instructions. The instruction type information can be obtained from a vector counter and a floating-point counter. The vector counter can be used to count the number of executions of vector calculation instructions. The floating-point counter can be used to count the number of executions of floating-point calculation instructions. The instruction type of the executed instruction is obtained from the decoding stage of the kernel pipeline. When the instruction is a vector calculation instruction, the vector counter is incremented by 1; when the instruction is a floating-point calculation instruction, the floating-point counter is incremented by 1.

[0047] Step S203: Determine the kernel status information based on the usage frequency, cache hit situation, and instruction type information.

[0048] As an example, a fixed clock cycle is set as the working cycle. At the beginning of each working cycle, the counters for counting the kernel status information are cleared. These counters include the cycle and instret counters for counting the kernel usage frequency, the cache access counter and cache hit counter for counting the cache hit situation, and the vector counter and floating-point counter for counting the instruction type, etc. In the decoding stage of the kernel pipeline, the instruction types executed within each working cycle are monitored, and the corresponding counters are updated. For each decoded instruction, if it is a vector calculation instruction, the vector counter is incremented by 1; if it is a floating-point calculation instruction, the floating-point counter is incremented by 1. At the same time, within each working cycle, the cache access requests and hit situations of the kernel are monitored. Whenever the kernel accesses the cache, the cache access counter is incremented by 1; if the access is a hit, the cache hit counter is also incremented by 1. The number of cycles and instructions run since the CPU reset is obtained from the cycle and instret counters, and based on this, the usage frequency of the kernel is counted. At the end of the working cycle, the kernel status information is calculated according to the collected counter data.

[0049] In some embodiments, the processing flow diagram of the kernel control method Figure 3 , such as Figure 3 shown, the kernel control method may include: Step S301a: Determine the target operating state of the power domain of the kernel based on the kernel status information or the operation control instruction.

[0050] In some embodiments, step S301a may include at least one of the following: Determine the power switch states of the respective domains included in the power domain based on the power switch signal included in the operation control instruction; Determine the voltage states of the respective domains included in the power domain based on the voltage control signal included in the operation control instruction; Determine the power switch states of the respective domains included in the power domain based on the register information included in the kernel status information.

[0051] In some embodiments, the power domain status table inside the monitoring and control unit can determine the power switch status and voltage status of the power domain. The target operating status of the power domain of the kernel can include: Stop mode, unsafe mode, Wait mode, unsafe_wait mode, unsafe_stop mode, etc. The normal operating status of the power domain can include: Run mode. Overall, the kernel architecture can be divided into four power domains: the main domain, the security domain, the storage domain, and the always-on domain. The main domain can include the main functional units and the debug interface module of the kernel. The security domain can include security and encryption units. The storage domain can include caches and memory management units. The always-on domain can include Timer, management modules, and interrupt-related units.

[0052] As an example, based on the power switch signal included in the operation control instruction, determine the power switch status of each domain included in the power domain; based on the voltage control signal included in the operation control instruction, determine the voltage status of each domain included in the power domain, which can include: switching the power switch status of each domain through the RISC-V WFI instruction, interrupt request, and software security regulation. Under normal circumstances, the kernel of the processor is in Run, which is the normal operating state, and all domains in the power domain are in the powered state. When the monitoring and control unit receives the RISC-V WFI instruction, according to the power switch signal and voltage control signal included in the RISC-V WFI instruction, adjust the power domain status table inside the monitoring and control unit, and convert the operating status of the power domain to Wait. In the Wait state, the kernel can wait to return to Run after receiving an interrupt request. In the Wait state, the power of the main domain is turned off, and the voltages of the storage domain and the security domain are reduced. The voltage of the always-on domain is maintained. Among them, the reduced voltage can be determined by the voltage control signal. When the kernel of the processor is in the Wait state, if the monitoring and control unit receives the WFI instruction again, according to the power switch signal and voltage control signal included in the RISC-V WFI instruction, adjust the power domain status table inside the monitoring and control unit, and convert the operating status of the power domain to the Stop state. In the Stop state, the power of the main domain, the storage domain, and the security and encryption domain are all turned off, the voltage of the always-on domain is reduced, and the status of the kernel of the processor at this time is reported to the bus PMU.

[0053] As an example, determining the power switch states of each domain included in the power domain based on the register information included in the kernel state information may include: The monitoring and control unit determines whether the register information included in the kernel state information represents that the security domain in the power domain is turned off. In response to the register information representing that the security domain in the power domain is turned off, the power domain status table inside the monitoring and control unit is adjusted based on the register information, and the operating state of the power domain is converted to unsafe. In the unsafe state, the power supply of the security domain is turned off, and the other domains remain normally powered.

[0054] In some embodiments, in the unsafe state, when the monitoring and control unit receives the RISC-V WFI instruction, according to the power switch signal and voltage control signal included in the RISC-V WFI instruction, the power domain status table inside the monitoring and control unit is adjusted, and the operating state of the power domain is converted to the Unsafe Wait state, or the operating state of the power domain is converted to the Unsafe_stop state. Unsafe_wait is similar to the Wait state, except that the power supply of the security domain is turned off. Unsafe_stop is also similar to the stop state, except that the power supply of the security domain is turned off. Here, how to convert the operating state of the power domain to the Unsafe_wait state and the Unsafe_stop state will not be elaborated.

[0055] Step S301b, determining the target operating state of the clock domain of the kernel based on the kernel state information or the operation control instruction.

[0056] In some embodiments, step S301b may include at least one of the following: determining the clock switch states of each domain included in the clock domain based on the clock switch signal included in the operation control instruction; determining the clock frequency states of each domain included in the clock domain based on the clock frequency control signal included in the operation control instruction; determining the clock frequency states of each domain included in the clock domain based on the kernel state information obtained according to the set operating period.

[0057] In some embodiments, the clock domain status table inside the monitoring and control unit can determine the clock switch status and clock frequency status of the clock domain. The target operating status of the clock domain of the kernel can include operating statuses such as Stop mode and Wait mode. The normal operating status of the clock domain can include Run mode. There is no need to set a separate unsafe status for the clock domain because when the kernel is in the unsafe state, the secure domain in the power domain is in the off state and the clock signal cannot be generated normally. Overall, the kernel architecture can be divided into five clock domains: the main clock domain, the data transfer clock domain, the computing clock domain, the debug domain, and the always-on clock domain. The main clock domain can include the main functional units of the kernel, the secure computing part of the secure encryption unit, as well as the first-level cache and the memory management unit. The data transfer clock domain can include the encryption transfer unit, the second-level cache, and the system bus. The computing clock domain can include the vector computing unit and the floating-point computing unit. The debug domain can include JTAG debugging. The always-on clock domain can include modules such as the management module, Timer, and interrupt module.

[0058] As an example, based on the clock switch signal included in the operation control instruction, determining the clock switch status of each domain included in the clock domain; based on the clock frequency control signal included in the operation control instruction, determining the clock frequency status of each domain included in the clock domain can include: switching the clock switch status of each domain through the RISC-V WFI instruction, interrupt request, and software security regulation. Normally, the kernel of the processor is in Run, which is the normal operating state, and all domains in the clock domain are powered on. When the monitoring and control unit receives the RISC-V WFI instruction, according to the clock switch signal and clock frequency control signal included in the RISC-V WFI instruction, the clock domain status table inside the monitoring and control unit is adjusted, and the operating status of the clock domain is converted to Wait. In the Wait state, the kernel can wait to return to Run after receiving an interrupt request. In the Wait state, the main clock domain and the computing clock domain are turned off, and the clock frequency of the data transfer clock domain is reduced. The clock frequency of the always-on domain remains unchanged. Among them, the reduced clock frequency can be determined by the clock frequency control signal. When the kernel of the processor is in the Wait state, if the monitoring and control unit receives the WFI instruction again, according to the clock switch signal and clock frequency control signal included in the RISC-V WFI instruction, the clock domain status table inside the monitoring and control unit is adjusted, and the operating status of the clock domain is converted to the Stop state. In the Stop state, the main clock domain, the data transfer clock domain, and the computing clock domain are all turned off, and the clock frequency of the always-on domain is reduced.

[0059] In some embodiments, determining the clock frequency status of each domain included in a clock domain based on kernel status information obtained according to a set operating cycle may include at least one of the following: in response to the usage frequency of the kernel obtained according to a set first operating cycle satisfying a set frequency threshold, adjusting the clock frequencies of each domain included in the clock domain to obtain a corresponding clock frequency status; in response to the cache hit situation obtained according to a set second operating cycle satisfying a set hit rate threshold, adjusting the clock frequencies of each domain included in the clock domain to obtain a corresponding clock frequency status; determining a first instruction count of vector type calculation instructions included in the instruction type information obtained according to a set third operating cycle, and based on the first instruction count, adjusting the clock frequencies of each domain included in the clock domain to obtain a corresponding clock frequency status; determining a second instruction count of floating point type calculation instructions included in the instruction type information obtained according to a set fourth operating cycle, and based on the second instruction count, adjusting the clock frequencies of each domain included in the clock domain to obtain a corresponding clock frequency status.

[0060] In some embodiments, the first operating cycle may be a fixed clock cycle for counting the usage frequency of the kernel. The second operating cycle may be a fixed clock cycle for counting the cache hit situation. The third operating cycle may be a fixed clock cycle for counting the number of vector type calculation instructions. The fourth operating cycle may be a fixed clock cycle for counting the number of floating point type calculation instructions. The first operating cycle, the second operating cycle, the third operating cycle, and the fourth operating cycle may be the same fixed clock cycle or different fixed clock cycles.

[0061] As an example, the kernel status register in the monitoring and control unit counts the usage frequency of the kernel itself, and dynamically adjusts the clock domain of the overall kernel when the usage frequency changes. Specifically, every fixed clock cycle, the usage frequency of the kernel is obtained from the kernel status register and compared with a preset frequency threshold. The preset frequency threshold is: when the usage frequency is lower than 30%, it is regarded as low load, and when it is higher than 70%, it is regarded as high load. Within a fixed clock cycle, the statistical result shows that the usage frequency of the kernel reaches 80%, exceeding the high load threshold. The monitoring and control unit adjusts the clock frequencies of the main clock domain and the calculation clock domain, and raises the clock frequencies from the normal mode to the high performance mode to enhance the computing power. If the usage frequency in a subsequent fixed clock cycle drops to 25%, which is lower than the low load threshold, the clock frequencies of the main clock domain and the calculation clock domain are adjusted back to the low power consumption mode to reduce power consumption.

[0062] As an example, the kernel status register in the monitoring and control unit counts the cache hits of the kernel and dynamically adjusts the clock domain of the overall kernel when the cache hit situation changes. Specifically, at fixed clock intervals, the cache hit situation of the L1 D-Cache of the kernel is obtained from the kernel status register to judge the cache hit situation of the L2 Cache, and the cache hit situation of the L1 D-Cache is compared with a preset hit rate threshold. The preset hit rate threshold is: when it is lower than 40%, it is considered that the cache efficiency is low; when it is higher than 70%, it is considered that the cache efficiency is high. During a fixed clock cycle, the statistical result shows that the cache hit situation of the L1 D-Cache reaches 80%, exceeding the high cache efficiency threshold. The monitoring and control unit adjusts the clock frequency of the data transfer clock domain, increasing the clock frequency from the normal mode to the high-performance mode to improve the data transfer rate. If the cache hit situation in a subsequent fixed clock cycle drops to 25%, which is lower than the low cache efficiency threshold, the clock frequency of the data transfer clock domain is adjusted back to the low-power mode to reduce power consumption.

[0063] As an example, the vector counter in the monitoring and control unit counts the number of the first instructions of the vector type calculation instructions executed by the kernel and dynamically adjusts the clock domain of the overall kernel when the number of the first instructions changes. Specifically, at fixed clock intervals, the number of the first instructions is obtained from the vector counter and compared with a preset number threshold. The preset number threshold is: when the number of the first instructions is less than 20 per cycle, it is considered a light load; when the number of the first instructions is more than 50 per cycle, it is considered a heavy load. During a fixed clock cycle, the statistical result shows that the number of the first instructions reaches 60, exceeding the high load threshold. The monitoring and control unit adjusts the clock frequency of the vector calculation unit in the calculation clock domain, increasing the clock frequency from the normal mode to the high-performance mode to enhance the calculation ability. If the number of the first instructions in a subsequent fixed clock cycle reaches 10, which is lower than the low load threshold, the clock frequency of the vector calculation unit in the calculation clock domain is adjusted to the low-power mode to reduce power consumption, and the vector counter is cleared.

[0064] As an example, the floating-point counter in the monitoring and regulation unit counts the number of second instructions of the floating-point type calculation instructions executed by the kernel, and dynamically adjusts the clock domain of the overall kernel when the number of second instructions changes. Specifically, at fixed clock intervals, the number of second instructions is obtained from the floating-point counter and compared with a preset number threshold. The preset number threshold is as follows: when the number of second instructions is less than 20 per cycle, it is regarded as a light load; when the number of second instructions is more than 50 per cycle, it is regarded as a heavy load. During a fixed clock cycle, the statistical result shows that the number of second instructions reaches 60, exceeding the high-load threshold. The monitoring and regulation unit adjusts the clock frequency of the floating-point calculation unit in the calculation clock domain, increasing the clock frequency from the normal mode to the high-performance mode to enhance the calculation ability. If the number of first instructions in a subsequent fixed clock cycle reaches 10, which is lower than the low-load threshold, the clock frequency of the floating-point calculation unit in the calculation clock domain is adjusted to the low-power mode to reduce power consumption, and the floating-point counter is cleared.

[0065] Step S302: Determine an adjustment signal corresponding to the kernel based on the target operating state, and send the adjustment signal to the power domain and / or clock domain of the kernel to control the operating state of the kernel.

[0066] In this embodiment, the description of step S302 is similar to that of step S103, and will not be elaborated here.

[0067] In some embodiments, the adjustment of the voltage of the power domain can be achieved by sending an instruction to the bus PMU unit, and the voltage transmitted by the PMU to this module is controlled through feedback information. The PMU unit is a unit that performs on-off control and voltage regulation on the internal LDO of the SoC.

[0068] In some embodiments, the adjustment of the clock frequency of the clock domain can be achieved by using a frequency hopping technique. In the embodiments of the present application, a simple circuit of a counter and a multiplexer is used to implement the frequency hopping technique. The counter uses the clock signal output by the PLL as the counting clock, and the divided-by-two, divided-by-four, and other required divided clock signals output enter the multiplexer together with the original clock, and are selected by the control signal as the clock signal actually used in the clock domain. The adjustment signal is given by the clock management unit of the monitoring and regulation unit according to the actual working conditions of the kernel. The embodiments of the present application can reduce the working frequency to 1 / 2, 1 / 4, or even lower than the normal working frequency when the chip enters the low-power mode, effectively reducing the overall power consumption of the circuit. The clock frequencies in different low-power modes can be different. For example, the clock frequency in the low_power_0 mode is divided by two, the clock frequency in the low_power_1 mode is divided by four, the clock frequency in the low_power_2 mode is divided by eight, and the clock frequency in the low_power_3 mode is divided by sixteen.

[0069] In some embodiments, the processing flow of the kernel control method is schematically shown Figure 4 as Figure 4 shown. The kernel control method may further include: Step S401: In response to the completion of the execution of the current thread, store the target address information and the target running state corresponding to the current thread in the historical information table.

[0070] Step S402: Adjust the kernel from the target running state to the normal running state.

[0071] Step S403: In response to the address information corresponding to the next thread matching the target address information, determine the corresponding target running state from the historical information table.

[0072] Step S404: Based on the determined target running state, determine the adjustment signal corresponding to the kernel, and send the adjustment signal to the power domain and / or clock domain of the kernel to control the running state of the kernel.

[0073] In this embodiment, the target address information may include the first-occurring PC and Offset, where Offset comes from the lower bits of the virtual address where the first occurrence occurs. The historical information table can be used to find and determine the target running state of the kernel when subsequent threads are started, reducing the latency of power consumption control.

[0074] As an example, when a thread first runs in the kernel, the first-occurring PC and Offset are recorded in the register, where Offset comes from the lower bits of the virtual address where the first occurrence occurs. When the current thread finishes running, the corresponding PC and Offset information and the low-power mode status in the power domain status table and clock domain status table at this time are recorded in the historical information table together, and the power and clock states are restored to the normal working mode. In response to the address information corresponding to the next thread matching the PC and Offset information included in the target address information, the corresponding low-power mode status is sent to the corresponding power domain status table and clock domain status table to quickly restore the previous low-power mode status.

[0075] Figure 5 Shows an application scenario of the kernel control method provided by the embodiments of the present application Figure 1 .

[0076] Referring to Figure 5 , Application scenario 1 of the kernel control method provided by the embodiments of the present application is applied to the low-power module of the kernel control system.

[0077] The overall architecture of the low-power module is as Figure 5As shown in the figure, the architecture includes three sub-modules: a monitoring and control unit, a power management unit, and a clock management unit. A historical information table is also set up to record historical information and quickly enter an appropriate low-power mode. The monitoring and control unit obtains the kernel status information in the CSR register group and the decoder. Among them, the CSR register group includes an interrupt register and a performance counter. According to the kernel status information, signals are sent to the power management unit and the clock management unit to adjust the switch and voltage status of the kernel's power domain in the power management unit, and to adjust the clock frequency and switch of the specified clock domain in the clock management unit. The monitoring and control unit can also receive external low-power signals (RISC-V WFI instruction or SoC low-power control). For SoC low-power control, directly change the corresponding bit values in the power management unit and the clock management unit.

[0078] Figure 6 The application scenario of the kernel control method provided by the embodiment of the present application is shown. Figure 2 。

[0079] Reference Figure 6 In the second application scenario of the kernel control method provided by the embodiment of the present application, it is applied to the monitoring and control unit in the low-power module. The monitoring and control unit includes a vector counter, a floating-point counter, a kernel status register, a power domain status table, a clock domain status table, and a TIMER. The monitoring and control unit adjusts the kernel operating state by obtaining the information of the CSR register and recording the execution of vector and floating-point instructions in the decoder during a fixed working cycle.

[0080] Figure 7 The application scenario of the kernel control method provided by the embodiment of the present application is shown. Figure 3 。

[0081] Reference Figure 7 In the third application scenario of the kernel control method provided by the embodiment of the present application, it is applied to the power domain division in the kernel. The main domain includes: the main functional units of the kernel and the debug interface module (JTAG). The always-on domain includes: Timer, management module, and interrupt-related unit (ECLIC). The storage domain includes: cache, memory management unit. The security domain includes: security and encryption units.

[0082] Figure 8 The application scenario of the kernel control method provided by the embodiment of the present application is shown. Figure 4 。

[0083] Reference Figure 8, Application scenario 4 of the kernel control method provided by the embodiments of the present application is applied to the clock domain division in the kernel. The kernel modules are divided into five clock domains, and independent gated clock signals are set for each clock domain, and unused modules can be shut down or downclocked. The main clock domain includes the main functional units in the kernel, the secure computing in the secure encryption unit, the first-level cache, and the bypass translation buffer. The data transfer clock domain includes the encryption transfer unit, the second-level cache, and the system bus, and is downclocked when it is detected that the hit rate of the first-level cache is extremely high so that data hardly needs to be fetched from the second-level cache. The computing clock domain includes: a vector computing unit and a floating-point computing unit. A separate JTAG debugging domain is set up for JTAG debugging. The always-on clock domain includes: a power management module, a Timer, an ECLIC, a DEBUG, and a clock management module.

[0084] It can be understood that Figures 5 - 8 the application scenarios of the kernel control method are only some exemplary implementation manners in the embodiments of the present application. The application scenarios of the kernel control method in the embodiments of the present application include but are not limited to Figures 5 - 8 the application scenarios of the kernel control method shown.

[0085] Next, continue to describe the exemplary structure of the software modules included in the kernel control device 90 provided by the embodiments of the present application. In some embodiments, as Figure 9 shown, the kernel control device 90 may include: an acquisition module 901, configured to acquire the kernel state information of the kernel when processing the current thread; a determination module 902, configured to determine the target operating state of the kernel in response to the kernel state information satisfying a set control condition or receiving a running control instruction for the kernel; the target operating state includes the target operating state of the power domain of the kernel and / or the target operating state of the clock domain; the power consumption corresponding to the target operating state is less than the power consumption of the kernel in the normal operating state; a control module 903, configured to determine an adjustment signal corresponding to the kernel based on the target operating state, and send the adjustment signal to the power domain and / or the clock domain of the kernel to control the operating state of the kernel.

[0086] In some embodiments, the acquisition module 901 is configured to: acquire the usage frequency and cache hit situation of the kernel when processing the current thread; obtain the instruction type information of the executed instructions from the decoding stage corresponding to the kernel when processing the current thread; and determine the kernel state information based on the usage frequency, cache hit situation, and instruction type information.

[0087] In some embodiments, the determination module 902 is configured to perform at least one of the following: determining a target operating state of the power domain of the kernel based on the kernel state information or the operation control instruction; the power domain at least includes a main domain, a security domain, a storage domain, and an always-on domain; determining a target operating state of the clock domain of the kernel based on the kernel state information or the operation control instruction; the clock domain at least includes a main clock domain, a data transfer clock domain, a computation clock domain, a debug domain, and an always-on clock domain.

[0088] In some embodiments, the determination module 902 is configured to perform at least one of the following: determining the power switch states of the respective domains included in the power domain based on the power switch signals included in the operation control instruction; determining the voltage states of the respective domains included in the power domain based on the voltage control signals included in the operation control instruction; determining the power switch states of the respective domains included in the power domain based on the register information included in the kernel state information.

[0089] In some embodiments, the determination module 902 is configured to perform at least one of the following: determining the clock switch states of the respective domains included in the clock domain based on the clock switch signals included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the clock frequency control signals included in the operation control instruction; determining the clock frequency states of the respective domains included in the clock domain based on the kernel state information obtained according to a set operation period.

[0090] In some embodiments, the kernel state information includes the usage frequency of the kernel, the cache hit situation, and instruction type information. The determination module 902 is configured to perform at least one of the following: in response to the usage frequency of the kernel obtained according to a set first operation period satisfying a set frequency threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; in response to the cache hit situation obtained according to a set second operation period satisfying a set hit rate threshold, adjusting the clock frequencies of the respective domains included in the clock domain to obtain corresponding clock frequency states; determining a first instruction quantity of the vector type calculation instructions included in the instruction type information obtained according to a set third operation period, and adjusting the clock frequencies of the respective domains included in the clock domain based on the first instruction quantity to obtain corresponding clock frequency states; determining a second instruction quantity of the floating-point type calculation instructions included in the instruction type information obtained according to a set fourth operation period, and adjusting the clock frequencies of the respective domains included in the clock domain based on the second instruction quantity to obtain corresponding clock frequency states.

[0091] In some embodiments, the kernel control device 90 further includes a storage module, which is configured to: store the target address information and the target operating state corresponding to the current thread in the historical information table in response to the completion of the execution of the current thread; adjust the kernel from the target operating state to the normal operating state; determine the corresponding target operating state from the historical information table in response to the match between the address information corresponding to the next thread and the target address information; determine the adjustment signal corresponding to the kernel based on the determined target operating state, and send the adjustment signal to the power domain and / or clock domain of the kernel to control the operating state of the kernel. It should be noted that the description of the device in the embodiments of the present application is similar to the description of the above method embodiments, and has similar beneficial effects to the method embodiments, so details will not be repeated. For the technical details not described in the kernel control device provided in the embodiments of the present application, they can be understood according to Figures 1 to 10 the description of any one of the accompanying drawings.

[0092] According to an embodiment of the present application, the present application also provides an electronic device and a non-transitory computer-readable storage medium.

[0093] Figure 10 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement the embodiments of the present application. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present application described herein and / or claimed.

[0094] As Figure 10 shown, the electronic device 800 includes a computing unit 801, which can execute various appropriate actions and processes according to the computer program stored in the ROM 802 or the computer program loaded from the storage unit 808 into the RAM 803. In the RAM 803, various programs and data required for the operation of the electronic device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other through a bus 804. The I / O interface 805 is also connected to the bus 804.

[0095] Multiple components in the electronic device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disc, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the electronic device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0096] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include but are not limited to a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as the kernel control method. For example, in some embodiments, the kernel control method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the kernel control method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute the kernel control method in any other suitable way (e.g., by means of firmware).

[0097] The various embodiments of the systems and technologies described above in this article can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, where the programmable processor can be a special or general-purpose programmable processor, and can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The program code for implementing the methods of the present application can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program codes can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0099] In the context of the present application, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0100] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0101] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0102] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, can also be a server of a distributed system, or a server incorporating a blockchain.

[0103] It should be understood that the various forms of processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps recited in this application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this application can be achieved, and no limitations are imposed herein.

[0104] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of this application, "a plurality" means two or more, unless otherwise specifically defined.

[0105] As described above, the above are only specific embodiments of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A kernel control method, characterized in that: The method comprises: Get kernel status information of the kernel in processing the current thread; In response to the kernel state information satisfying a set control condition, or receiving an operation control instruction for the kernel, determining a target operation state of the kernel; the target operation state includes a target operation state of a power domain of the kernel and / or a target operation state of a clock domain; the power consumption corresponding to the target operation state is less than the power consumption of the kernel in a normal operation state; An adjustment signal corresponding to the core is determined based on the target operating state, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

2. The method according to claim 1, characterized in that The obtaining of kernel state information of the kernel when processing the current thread includes: Obtaining the usage frequency and cache hit status of the core when processing the current thread; In the case of processing the current thread, obtaining instruction type information of the executed instruction from the decoding stage corresponding to the kernel; The kernel status information is determined based on the usage frequency, cache hit status and instruction type information.

3. The method according to claim 1, characterized in that Determining the target operating state of the kernel includes at least one of the following: Based on the kernel state information or the operation control instruction, determining the target operation state of the power domain of the kernel; the power domain includes at least a main domain, a security domain, a storage domain and a normally open domain; Determining a target operating state of a clock domain of the kernel based on the kernel state information or the operating control instruction; The clock domains at least include a main clock domain, a data transmission clock domain, a calculation clock domain, a debugging domain and a normally-on clock domain.

4. The method according to claim 3, characterized in that: Determining the target operating state of the power domain of the core includes at least one of the following: Determine the power switch state of each domain included in the power domain based on the power switch signal included in the operation control instruction; Determining the voltage state of each domain included in the power domain based on the voltage control signal included in the operation control instruction; Based on the register information included in the core status information, the power switch status of each domain included in the power domain is determined.

5. The method according to claim 3, characterized in that: Determining the target operating state of the clock domain of the core includes at least one of the following: Determining the clock switch state of each domain included in the clock domain based on the clock switch signal included in the operation control instruction; Determining the clock frequency status of each domain included in the clock domain based on the clock frequency control signal included in the operation control instruction; Based on the core status information acquired according to the set operation cycle, the clock frequency status of each domain included in the clock domain is determined.

6. The method according to claim 5, characterized in that The kernel status information includes kernel usage frequency, cache hit status, and instruction type information. The determining of the clock frequency status of each domain included in the clock domain based on the kernel status information obtained according to the set operation cycle includes at least one of the following: In response to the usage frequency of the core acquired according to the set first operation cycle meeting the set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; In response to the cache hit status obtained according to the set second operation cycle meeting the set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; Determine a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to the set third operation cycle, and adjust the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency state; Determine a second instruction quantity of floating-point type calculation instructions included in the instruction type information obtained according to the set fourth operation cycle, and adjust the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency state.

7. The method according to claim 1, characterized in that The method further comprises: In response to the current thread completing execution, storing the target address information and the target running state corresponding to the current thread into a history information table; Adjusting the kernel from a target operating state to a normal operating state; In response to the address information corresponding to the next thread matching the target address information, determining the corresponding target running state from the history information table; Based on the determined target operating state, an adjustment signal corresponding to the core is determined, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

8. A kernel control device, characterized in that: The device comprises: An acquisition module, used to obtain kernel state information of the kernel when processing the current thread; a determination module, configured to determine a target operating state of the core in response to the core state information satisfying a set control condition or receiving an operating control instruction for the core; the target operating state includes a target operating state of a power domain of the core and / or a target operating state of a clock domain; and the power consumption corresponding to the target operating state is less than the power consumption of the core in a normal operating state; A control module is used to determine an adjustment signal corresponding to the core based on the target operating state, and send the adjustment signal to a power domain and / or a clock domain of the core to control the operating state of the core.

9. The device according to claim 8, characterized in that The acquisition module is used for: Obtaining the usage frequency and cache hit status of the core when processing the current thread; In the case of processing the current thread, obtaining instruction type information of the executed instruction from the decoding stage corresponding to the kernel; The kernel status information is determined based on the usage frequency, cache hit status and instruction type information.

10. The device according to claim 8, characterized in that The determination module is used for at least one of the following: Based on the kernel state information or the operation control instruction, determining the target operation state of the power domain of the kernel; the power domain includes at least a main domain, a security domain, a storage domain and a normally open domain; Determining a target operating state of a clock domain of the kernel based on the kernel state information or the operating control instruction; The clock domains at least include a main clock domain, a data transmission clock domain, a calculation clock domain, a debugging domain and a normally-on clock domain.

11. The device according to claim 10, characterized in that The determination module is used for at least one of the following: Determine the power switch state of each domain included in the power domain based on the power switch signal included in the operation control instruction; Determining the voltage state of each domain included in the power domain based on the voltage control signal included in the operation control instruction; Based on the register information included in the core status information, the power switch status of each domain included in the power domain is determined.

12. The device according to claim 10, characterized in that The determination module is used for at least one of the following: Determining the clock switch state of each domain included in the clock domain based on the clock switch signal included in the operation control instruction; Determining the clock frequency status of each domain included in the clock domain based on the clock frequency control signal included in the operation control instruction; Based on the core status information acquired according to the set operation cycle, the clock frequency status of each domain included in the clock domain is determined.

13. The device according to claim 12, characterized in that The kernel status information includes kernel usage frequency, cache hit status, and instruction type information, and the determination module is used for at least one of the following: In response to the usage frequency of the core acquired according to the set first operation cycle meeting the set frequency threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; In response to the cache hit status obtained according to the set second operation cycle meeting the set hit rate threshold, adjusting the clock frequency of each domain included in the clock domain to obtain a corresponding clock frequency state; Determine a first instruction quantity of vector type calculation instructions included in the instruction type information obtained according to the set third operation cycle, and adjust the clock frequency of each domain included in the clock domain based on the first instruction quantity to obtain a corresponding clock frequency state; Determine a second instruction quantity of floating-point type calculation instructions included in the instruction type information obtained according to the set fourth operation cycle, and adjust the clock frequency of each domain included in the clock domain based on the second instruction quantity to obtain a corresponding clock frequency state.

14. The device according to claim 8, characterized in that The device further comprises a storage module, wherein the storage module is used for: In response to the current thread completing execution, storing the target address information and the target running state corresponding to the current thread into a history information table; Adjusting the kernel from a target operating state to a normal operating state; In response to the address information corresponding to the next thread matching the target address information, determining the corresponding target running state from the history information table; Based on the determined target operating state, an adjustment signal corresponding to the core is determined, and the adjustment signal is sent to a power domain and / or a clock domain of the core to control the operating state of the core.

15. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

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