Method for realizing 4G5G synchronization based on CAT1 module

Abstract

The invention discloses a method for realizing 4G5G synchronization based on a CAT1 module, relates to the technical field of bandwidth management, is used for solving the problem of synchronization between a TDD wireless repeater and a base station when a wireless network covers a weak blind area, and comprises the following steps: demodulating base station data, demodulating a corresponding time sequence according to the base station data, enabling the repeater to be accurately aligned with the time of the base station, and collecting base station application data. Performing network load evaluation on each application by using an analytic hierarchy process according to the historical data and the application data, setting different load weights according to the network load of each application to analyze the overall network load degree, and collecting application behavior data after determining the overall network load degree; and calculating and analyzing the data condition of the repeater by using a logistic regression method according to the load degree of the whole network and the application behavior data, adjusting an alarm threshold value according to the data condition of the repeater, collecting feedback data before and after the alarm threshold value is adjusted, and selecting to carry out alarm threshold value processing or power failure optimization processing according to the feedback data.

Description

Technical Field

[0001] The present invention relates to the field of data communication technologies, and more specifically, to a method for achieving 4G and 5G synchronization based on a CAT1 module. Background Art

[0002] Data communication technology is a technical system that efficiently and reliably transmits digital information from a sending end to a receiving end through physical or wireless channels. It is the core infrastructure of modern information society, supporting the operation of all digital scenarios such as the Internet, Internet of Things, industrial control, and cloud computing.

[0003] The prior art has the following deficiencies: Traditional SRAM adopts a planar layout, where P-type and N-type transistors occupy a large substrate area, resulting in limited storage array density; the logic circuit and the storage array compete for chip space, affecting the improvement of the overall capacity; there is a lack of a hardware-level locking mechanism for multi-queue resource access, posing a risk of data conflict. Summary of the Invention

[0004] To overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a method for achieving 4G and 5G synchronization based on a CAT1 module. By integrating P-type transistors on the front-end device layer and stacking N-type transistors on the back-end device layer, the storage density is increased through the reduction of the vertical projection area; the logic circuit and the storage array are hierarchically laid out to optimize the chip space utilization rate to solve the problems proposed in the above background art.

[0005] To achieve the above object, the present invention provides the following technical solutions: A method for achieving 4G and 5G synchronization based on a CAT1 module, including: A four-layer modular architecture: consisting of a hardware abstraction layer, a real-time operating system layer, a protocol processing layer, and an application logic layer. The hardware abstraction layer encapsulates the CAT1 module driver and integrates the FPGA hardware trigger module, and the protocol processing layer optimizes the TCP / IP protocol stack by using a pre-allocated memory and a heartbeat keep-alive mechanism; A hybrid synchronization signal processing flow: based on Hamming window filtering and frequency offset compensation to achieve signal preprocessing, complete sub-microsecond frame synchronization through CP autocorrelation detection and PBCH decoding, and dynamically correct the timing deviation by combining the FPGA hardware trigger and the delay prediction model; A system integration and verification module: configuring a multi-task concurrent control mechanism, supporting end-to-end synchronization error reduction processing and high-density stress testing, and achieving self-optimization through a temperature adaptive algorithm.

[0006] In a preferred embodiment, the CAT1 module drives multi-level task scheduling based on FreeRTOS, adopts a preemptive priority strategy, and asynchronous tasks are triggered through a circular buffer and a message queue to ensure non-blocking communication; The FPGA drive encapsulates the SPI / UART interface timing control logic, supports redundant switching between the primary and backup channels, and triggers the activation of the backup channel through a hardware interrupt when the primary channel fails. The context data of the current state machine is retained during the switching process; The hardware abstraction layer integrates a CRC check module to perform 16-bit polynomial checks on the transmitted data, and the upper limit of the automatic retransmission times for error frames is 3 times.

[0007] In a preferred embodiment, business data is encapsulated through the JSON protocol, and a state machine is defined to implement a closed-loop of instruction parsing and ACK / NACK feedback. The state machine includes five states: idle, instruction reception, data encapsulation, transmission ready, and error handling, and supports a nested timeout retransmission mechanism; The dynamic memory pool allocates transmission resources according to the business priority, monitors memory leaks in real time and triggers forced recycling. The memory allocation strategy adopts two-level management: high-priority tasks are allocated continuous physical memory blocks, and low-priority tasks use fragmented virtual memory pools; The protocol processing layer incorporates a traffic shaping module to limit burst traffic based on the token bucket algorithm, and the token generation rate is dynamically matched with the physical layer bandwidth.

[0008] In a preferred embodiment, Hamming window filtering uses a 128-point FFT to optimize spectral leakage. The window function coefficients are pre-loaded into the on-chip RAM of the FPGA through a look-up table method. The frequency offset compensation is based on the least squares method to fit the carrier offset, and the compensation value is iteratively calculated for each frame of the signal and the local oscillator is updated; PBCH decoding uses the soft decision Viterbi algorithm to improve the synchronization success rate in a low signal-to-noise ratio environment, and the path metric calculation adopts a weighted fusion of Euclidean distance and Hamming distance; The CP autocorrelation detection module uses a sliding window to calculate the correlation between the cyclic prefix and the data segment, and the peak detection threshold is dynamically adjusted according to the noise floor. The detection result is transmitted to the FPGA interrupt controller through DMA.

[0009] In a preferred embodiment, the delay prediction model includes the following: training historical delay data based on the LSTM network, the network structure includes 3 layers of hidden units, the input features include link RSSI, channel bandwidth, temperature drift, and historical delay sequence, and the output is the predicted value of the transmission path delay in the next cycle; The dynamic correction module adjusts the phase of the FPGA trigger pulse according to the prediction result, and triggers a system-level alarm and switches to the redundant channel when it exceeds the limit.

[0010] In a preferred embodiment, when the main channel fails, the backup channel preempts the bus control right through a hardware interrupt. The interrupt service program first saves the current DMA transfer status to a backup register and resumes the transfer after the switch is completed.

[0011] In a preferred embodiment, the working temperature of the FPGA is monitored in real time by an on-chip temperature sensor. The data is input into a temperature-delay mapping table after being filtered by a Kalman filter. The clock division coefficient is dynamically adjusted. The temperature drift compensation amount calculates the proportional coefficient and integral time through a PID controller and is adjusted according to the temperature-delay mapping table.

[0012] In a preferred embodiment, to simulate multi-node concurrent requests, the request interval time is generated using a Poisson distribution, the packet loss rate and synchronization error distribution are statistically analyzed, and the test data is generated by a hardware accelerator to reduce the CPU load. The verification of the system's self-recovery ability includes the resynchronization accuracy within a preset time after fault injection, without data loss or protocol stack crash.

[0013] In a preferred embodiment, the protocol retransmission times and timeout thresholds are dynamically adjusted through reinforcement learning, and the FIR filter coefficients are optimized based on a genetic algorithm.

[0014] The technical effects and advantages of a method for realizing 4G / 5G synchronization based on a CAT1 module according to the present invention: The present invention constructs a four-layer modular architecture. The hardware abstraction layer encapsulates the CAT1 module and the FPGA driver. Based on FreeRTOS, multi-level task scheduling is implemented. The protocol processing layer trims the TCP / IP protocol stack and optimizes the transmission mechanism. In the application layer, the state machine and JSON data are encapsulated to achieve software-hardware decoupling, reduce system complexity, design a hybrid synchronization signal processing flow, use Hamming window filtering and frequency offset compensation to improve signal quality, cooperate with FPGA hardware triggering and software dynamic correction to support fast transplantation across multiple platforms, reduce dynamic resource overhead by preallocating memory, enhance connection stability through a heartbeat keep-alive mechanism, integrate hardware interfaces and multi-task concurrent control to complete end-to-end function verification, and ensure reliability through high-density stress testing and on-site dynamic optimization, improve the maintainability of the system, reduce the complexity of the single board, and reduce the cost of the single board. Brief Description of the Drawings

[0015] Figure 1 It is a schematic diagram of a method for realizing 4G / 5G synchronization based on a CAT1 module according to the present invention.

[0016] Figure 2 It is a mind map of a method for realizing 4G / 5G synchronization based on a CAT1 module according to the present invention.

[0017] Figure 3This is a mind map of a method for realizing 4G and 5G synchronization based on a CAT1 module in the present invention. Detailed implementation mode

[0018] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0019] The present invention constructs a four-layer modular architecture. The hardware abstraction layer encapsulates the CAT1 module and the FPGA driver. Based on FreeRTOS, multi-level task scheduling is realized. The protocol processing layer trims the TCP / IP protocol stack and optimizes the transmission mechanism. In the application layer, the state machine and JSON data are encapsulated, and a hybrid synchronization signal processing flow is designed. Hamming window filtering and frequency offset compensation are used to improve the signal quality. Through the cooperation of FPGA hardware triggering and software dynamic correction, the hardware interface and multi-task concurrent control are integrated to complete the end-to-end function verification, and the reliability is ensured through high-density stress testing and on-site dynamic optimization, improving the maintainability of the system and reducing the complexity of the single board, and reducing the cost of the single board.

[0020] Embodiment, a method for realizing 4G and 5G synchronization based on a CAT1 module, as Figures 1 to 3 shown, including: ‌Four-layer modular architecture‌: It consists of a hardware abstraction layer, a real-time operating system layer, a protocol processing layer, and an application logic layer. The hardware abstraction layer encapsulates the CAT1 module driver and integrates the FPGA hardware triggering module. The protocol processing layer optimizes the TCP / IP protocol stack by using pre-allocated memory and heartbeat keep-alive mechanism; ‌Hybrid synchronization signal processing flow‌: Based on Hamming window filtering and frequency offset compensation, signal preprocessing is realized. Sub-microsecond frame synchronization is completed through CP autocorrelation detection and PBCH decoding. Combining FPGA hardware triggering and delay prediction model to dynamically correct the timing deviation; ‌System integration and verification module‌: Configure a multi-task concurrent control mechanism, support end-to-end synchronization error reduction processing and high-density stress testing, and realize self-optimization through a temperature adaptive algorithm.

[0021] The specific implementation is as follows: The software architecture of this system adopts a ‌four-layer modular design‌ to ensure function decoupling, scalability, and real-time performance. The four layers of modules include a hardware abstraction layer, a real-time operating system layer, a protocol processing layer, and an application logic layer.

[0022] The following functions are included in the hardware abstraction layer: CAT1 Module Driver: Implement AT command control based on the serial communication protocol (UART, baud rate 115200).

[0023] For example, query the signal strength by sending the AT+CSQ command, and parse the returned response string (such as "+CSQ: 20,99") to extract the RSRP value (20dBm).

[0024] Band Locking Function: Execute the band scanning command (such as AT+QSCAN=1,3,100), dynamically select the optimal band (such as N78) according to the signal strength, and lock the target band through the AT+QCFG command.

[0025] FPGA Register Driver: Read and write the internal registers of the FPGA through the SPI bus (mode 0, clock rate 10MHz).

[0026] For example, write the synchronization offset parameter (Sync Shift) to address 0x1004 to control the precise trigger timing of the Sync1 pulse.

[0027] The following functions are included in the real-time operating system layer: System Selection and Task Scheduling: Use the FreeRTOS kernel, and the task priorities are divided into three levels: Highest Priority Task: Triggered by a hardware interrupt, parse the IQ signal in real time and generate a synchronization pulse to ensure that the timing synchronization delay ≤ 5μs.

[0028] Medium Priority Task: Execute every 60 seconds, responsible for encapsulating device status data (such as signal strength, temperature) and uploading it to the cloud through the TCP protocol.

[0029] Low Priority Task: Run once every 10 minutes, monitor the system health status (such as memory occupancy, temperature), and trigger an exception alarm.

[0030] Interrupt Management Mechanism: The radio frequency reception interrupt is configured with the highest priority and directly triggers the highest priority task to avoid data processing delay.

[0031] It should be noted that the timer interrupt is used to periodically wake up the DataTxTask, and the precise scheduling is implemented using the soft timer module of FreeRTOS.

[0032] The protocol processing layer includes the following functions: Reduced Protocol Stack Design: Trim the standard TCP / IP protocol stack, remove unnecessary functions (such as IPv6, UDP broadcast), and retain the core protocols including ARP (address resolution), IPv4 (packet encapsulation), TCP (reliable transmission), and ICMP (network connectivity detection).

[0033] Static memory pre - allocation: Pre - define 10 packet buffers of fixed size (1536 bytes each) to avoid fragmentation problems caused by dynamic memory allocation.

[0034] Data transfer optimization: Heartbeat mechanism: Send a heartbeat packet (with a fixed identifier 0xAA55) every 30 seconds to maintain long - term connections and detect network interruptions.

[0035] Sliding window control: Set the TCP window size to 1460 bytes to balance throughput and transmission reliability.

[0036] The application logic layer includes the following functions: Core business logic implementation: Synchronization control state machine: Define four states (idle, detecting, locked, error), and dynamically switch according to the parsing result of IQ signals.

[0037] For example, when a matching wireless frame number is detected, the state migrates from "detecting" to "locked", and a synchronization pulse is generated.

[0038] Data encapsulation module: Convert device status parameters (such as RSRP, synchronization error, temperature) into JSON format, add a timestamp and device ID to form a standardized reporting data packet.

[0039] Remote instruction parsing: Support JSON - formatted remote control instructions (such as adjusting gain, switching synchronization mode), receive them through HTTP POST requests, and call the corresponding hardware control interface after signature verification.

[0040] The specific implementation details of the CAT1 module driver are as follows: When the CAT1 module driver performs multi - band dynamic switching, it first scans the bands and selects the process. After power - on, it executes the full - band scan instruction to obtain the available band list and the corresponding signal strength; Sort according to the signal strength, select the optimal band (such as N78), and send a band locking instruction (such as AT+QCFG="band",0x0000000000002000); If the locking fails (such as timeout or the signal is lower than the preset signal threshold), trigger a retry mechanism (up to 3 times), and report an "abnormal band" alarm after failure; Seamless switching design: During the band switching process, ensure that the service interruption time < 50ms through caching data to be sent and a fast re - connection mechanism; Data fragmentation and recombination: The sender splits JSON data exceeding 512 bytes into multiple fragments, adds a sequence number identifier (such as "seg:1 / 3") to each fragment, and reduces the single - time delay through multi - packet transmission; The receiving end reorganizes the data according to the sequence number and actively initiates a retransmission request after detecting the lost fragments.

[0041] Quality of Service Classification: The synchronization control instruction is marked as the highest priority (DSCP = 46) and is transmitted through a dedicated APN channel.

[0042] It should be noted that the dedicated APN is a network access point customized by the mobile operator for enterprises or specific application scenarios, used to build a closed data transmission channel independent of the public network, and its core function is to establish a logical connection between the device and the dedicated network.

[0043] The FPGA software logic includes timing parsing, pulse generation, interrupt nesting, and task scheduling. The specific functions are as follows: The specific steps of the timing parsing and pulse generation process are as follows: Input Data Processing: Receive IQ sampling data (32 bits / sampling point, including 16-bit I and 16-bit Q components) from the RF chip and store it in a double-buffered circular queue to avoid data overwrite; Trigger an interrupt to notify the RTOS layer to start the parsing task.

[0044] Key Algorithm Steps: Cyclic Prefix Detection: Calculate the autocorrelation of adjacent symbols, and when the correlation peak exceeds the preset threshold, it is determined as the CP starting point; Frame Synchronization and Time Slot Configuration Matching: Parse the master information block (MIB) in the physical broadcast channel, extract the system frame number, and match the pre-stored TDD time slot configuration table (such as the DSUDD structure defined in 3GPP 38.211); Synchronization Pulse Generation: According to the time slot configuration, configure the internal timer module of the FPGA to generate a Sync1 pulse (pulse width 10 μs) at the start time of the target subframe (DwPTS) and output it to the signal amplifier through the SPI bus. The specific steps of interrupt nesting and task scheduling are as follows: When the radio frequency reception interrupt service program only sets the "data ready" flag, the actual parsing task is executed by SyncTask in the RTOS context to avoid long-term occupation of interrupt resources.

[0045] Enable the DMA controller to achieve high-speed transmission of IQ data and release the CPU computing power for timing parsing.

[0046] Memory Access Acceleration: Allocate a dedicated SRAM area for the timing parsing task, store IQ data using continuous memory blocks, and reduce the latency caused by cache misses.

[0047] It should be noted that the dedicated SRAM area refers to the SRAM storage space independently partitioned in the chip or system, which has physical or logical access isolation.

[0048] The working processes of the signal amplifier and the synchronization error correction module are as follows: Signal preprocessing and noise reduction: Apply Hamming window functions to the real and imaginary parts of the IQ sampled data respectively through Hamming window filtering, with weighting coefficients of 0.54 and 0.46, to suppress spectral leakage and improve the detection accuracy of signal peaks; Noise floor estimation: Calculate the average value of the signal power spectral density, dynamically set the detection threshold (for example, threshold = noise floor + 6dB), and filter out interference signals in the low signal-to-noise ratio region; Frequency offset compensation: Analyze the spectrum of the IQ signal through fast Fourier transform, locate the main lobe peak position, and calculate the frequency offset value in combination with the sampling rate (30.72MHz) and the number of FFT points (1024). The formula is Δf = (peak position index × sampling rate) / FFT points; Phase rotation compensation: Perform reverse phase rotation on the IQ signal according to the frequency offset value to eliminate the influence of carrier frequency offset on the synchronization accuracy; Cyclic prefix detection and frame synchronization: Calculate the autocorrelation function of the IQ data of two consecutive OFDM symbols, with the sliding window length being the CP length (such as 72 sampling points). When the autocorrelation value exceeds the threshold, it is determined as the CP starting point; Multi-symbol averaging: Take the average of the CP detection results of consecutive n wireless frames to eliminate the random error of single detection; System frame number parsing: PBCH channel decoding: Extract the master information block (MIB) from the physical broadcast channel and parse the SFN (10-bit binary number) and TDD uplink and downlink configuration parameters (such as the DSUDD structure) therein; Time slot alignment: Calculate the absolute timestamp of the current wireless frame according to the SFN and the subframe number (0~9) to align the timing reference of the base station and the terminal.

[0049] The cooperation mechanism of hardware trigger and software correction is as follows: Hardware trigger unit: When the FPGA detects the CP starting point, it triggers a high-priority interrupt (response delay ≤ 1μs) through the GPIO pin to start the highest-priority task; Pulse timing generation: Configure the internal timer of the FPGA (accuracy 10ns) according to the CP position and SFN information to generate a Sync1 pulse (pulse width 10μs, rising edge aligned) at the starting moment of the DwPTS subframe; Software Dynamic Calibration: Based on historical synchronization error data (storing the last N offsets), construct a second-order regression model to predict the time delay compensation amount for the next cycle; Parameter Dynamic Adjustment: Convert the predicted time delay compensation amount into a Sync Shift parameter value and write it into the FPGA register (address 0x1004) through the SPI interface to correct the trigger timing of the Sync1 pulse in real time.

[0050] The redundant synchronization channel is designed as follows: Primary and Backup Channel Switching: Sync1 Primary Channel: By default, use the Sync1 pulse generated by the FPGA, and the synchronization error ≤ 0.8 μs; Sync2 Backup Channel: When Sync1 fails to respond continuously for 3 times or the error exceeds 2 μs, switch to the Sync2 pulse generated by the software timer (accuracy 1 ms) to ensure the basic synchronization function of the system; Status Synchronization Mechanism: When switching between the primary and backup channels, transfer the current SFN and time slot number through the shared memory area to avoid loss of synchronization status.

[0051] The anti-interference and fault tolerance mechanism is designed as follows: Filter Design: Implement a 128th-order finite impulse response (FIR) filter in the FPGA, with the passband range of 3300 - 3800 MHz and the stopband attenuation ≥ 40 dB, to suppress out-of-band interference from Wi-Fi (2.4 GHz / 5 GHz) and Bluetooth signals; Dynamic Filter Switching: Automatically enable or disable the filter according to the ambient noise power to balance the processing delay and anti-interference requirements; Narrowband Interference Cancellation: Identify narrowband interference (such as LTE adjacent frequency leakage) through FFT analysis and generate an anti-phase signal in the time domain for cancellation; The abnormal detection and self-recovery mechanism is as follows: Synchronization Loss Detection: Count the number of consecutive synchronization failures. If it exceeds the preset number threshold (such as 10 times), it is determined to be in a loss-locked state and trigger a system alarm; Cause Diagnosis: Record the diagnostic log according to the error type (such as excessive frequency offset, CP detection failure) to assist the operation and maintenance personnel in locating the problem.

[0052] The automatic recovery strategy is as follows: Soft Reset Mechanism: When loss-locked, reset the synchronization state machine and re-execute the frequency band scanning and CP detection processes.

[0053] Parameter Rollback: If the dynamic calibration causes the error to increase, automatically roll back to the previous stable parameter configuration.

[0054] It should be noted that the LSTM model is trained based on historical synchronization data to achieve online prediction and adaptive adjustment of the delay compensation amount at the edge device side, reducing the dependence on cloud computing.

[0055] The system integration and verification module includes the following mechanisms: System integration and collaborative working mechanism: Hardware interface definition: The CAT1 module and the main control MCU use a baud rate of 115,200, and the data frame format is 8 data bits, 1 stop bit, and no parity bit. A dedicated instruction set is defined (e.g., 0x01 for writing synchronization parameters and 0x02 for status query); SPI register mapping: The main control MCU accesses the FPGA registers through the SPI bus (mode 0, clock rate 10 MHz). The key registers include the synchronization pulse control register (address 0x1000) and the IQ data buffer address register (address 0x2000); Software data stream integration: The radio frequency reception interrupt signal simultaneously triggers the CP detection module of the FPGA and the highest priority task of the RTOS, and the data synchronization of the dual modules is achieved through semaphores; Cross-layer data transfer: The synchronization parameters (Sync Shift) generated by the application layer are written into the FPGA registers through the hardware abstraction layer (HAL) to form a full-link closed-loop control of "application → driver → hardware".

[0056] Multi-task concurrent processing mechanism: Resource mutual exclusion management: The shared resources (such as the IQ data buffer) are protected by mutex locks. The read and write operations of the buffer follow the "producer-consumer" model to avoid data competition; High-priority tasks can preempt the CPU resources of other low-priority tasks, and the maximum preemption duration is set to be less than 10 μs to prevent low-priority tasks from being unable to be processed; Real-time data pipeline: The acquisition of radio frequency data, CP detection, and synchronization pulse generation form a three-level pipeline, and each level of the pipeline is set with an independent buffer queue to ensure that the data throughput is ≥ 1.5 M Samples / s.

[0057] The functional test method is as follows: Unit test: CAT1 module communication test: Use a signal generator to simulate the base station signal to verify the frequency band switching; Synchronization accuracy test: Measure the rising edge deviation of the Sync1 pulse and the standard clock source through a high-precision oscilloscope, and count the average error and the maximum error; Integration test: Build a multi-node test environment (1 main node + 3 slave nodes) to verify the delay of the Sync1 pulse of the main node triggering the synchronization response of the slave nodes; Protocol stack stress test: Inject high-density data packets; for example, 1000 packets per second, and verify the packet loss rate of the TCP / IP protocol stack.

[0058] The performance metrics are evaluated as follows: Real-time metric: The time from the radio frequency interruption trigger to the start of the highest-priority task ≤ 5 μs (measured based on the timestamp of the highest-priority task); End-to-end transmission delay: The total delay from the acquisition of device status data to its reception in the cloud ≤ 300 ms.

[0059] The deployment and dynamic optimization steps are as follows: When deploying in the industrial field, add a hardware shielding cover and a software FIR filter (cutoff frequency 3.8 GHz) to suppress the broadband interference from devices such as motors and frequency converters; Dynamically adjust the CP detection threshold and adaptively improve the detection sensitivity according to the ambient noise power.

[0060] The temperature adaptability design is as follows: Install a built-in temperature sensor to monitor the temperature of the FPGA chip in real time. When the temperature ≥ 85 °C, automatically reduce the SPI clock rate to 5 MHz to avoid hardware overheating failure; Dynamic parameter optimization: Collect data such as historical synchronization error, signal strength, and ambient temperature, and dynamically optimize the Sync Shift parameter through a linear regression model to reduce the frequency of manual parameter adjustment.

[0061] It should be noted that the processing methods used for dynamically adjusting the CP detection threshold and dynamic parameter optimization are existing technical means and will not be elaborated here.

[0062] The above embodiments can be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product.

[0063] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application of the technical solution and the invention constraints. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0064] In addition, in each embodiment of the present application, the various functional modules can be integrated in one processing module, or each module can exist physically alone, or two or more modules can be integrated in one module.

[0065] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claimed rights.

[0066] Finally: The above are only the preferred embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for realizing 4G5G synchronization based on CAT1 module, characterized in that: include: ‌Four-layer modular architecture‌: It consists of hardware abstraction layer, real-time operating system layer, protocol processing layer and application logic layer. The hardware abstraction layer encapsulates the CAT1 module driver and integrates the FPGA hardware trigger module. The protocol processing layer uses pre-allocated memory and heartbeat keep-alive mechanism to optimize the TCP / IP protocol stack. ‌Hybrid synchronization signal processing flow‌: Signal preprocessing is achieved based on Hamming window filtering and frequency offset compensation, sub-microsecond frame synchronization is achieved through CP autocorrelation detection and PBCH decoding, and timing deviation is dynamically corrected by combining FPGA hardware triggering and delay prediction model; ‌System Integration and Verification Module‌: Configures a multi-task concurrent control mechanism, supports end-to-end synchronization error reduction processing and high-density stress testing, and achieves self-optimization through a temperature adaptive algorithm.

2. According to claim 1, a method for realizing 4G5G synchronization based on CAT1 module is characterized in that: The CAT1 module driver implements multi-level task scheduling based on FreeRTOS, adopts a preemptive priority strategy, and asynchronous tasks are triggered through a ring buffer and message queue to ensure non-blocking communication; The FPGA driver encapsulates the SPI / UART interface timing control logic, supports the redundant switching of the main and backup channels, and triggers the activation of the backup channel through hardware interrupts when the main channel fails. The switching process retains the current state machine context data; The hardware abstraction layer integrates a CRC check module to perform a 16-bit polynomial check on the transmitted data. The upper limit of the number of automatic retransmissions of error frames is 3 times.

3. According to claim 1, a method for realizing 4G5G synchronization based on CAT1 module is characterized in that: Encapsulate business data through JSON protocol, define state machine to implement command parsing and ACK / NACK feedback closed loop, the state machine includes five states: idle, command reception, data encapsulation, ready to send and error handling, and supports nested timeout retransmission mechanism; The dynamic memory pool allocates transmission resources according to business priority, monitors memory leaks in real time and triggers forced recycling. The memory allocation strategy adopts two-level management: high-priority tasks are allocated continuous physical memory blocks, and low-priority tasks use fragmented virtual memory pools; The protocol processing layer has a built-in traffic shaping module that limits burst traffic based on a token bucket algorithm, and the token generation rate is dynamically matched with the physical layer bandwidth.

4. According to claim 1, a method for realizing 4G5G synchronization based on CAT1 module is characterized in that: Hamming window filtering uses 128-point FFT to optimize spectrum leakage. The window function coefficients are preloaded into the FPGA on-chip RAM through a table lookup method. Frequency offset compensation is based on the least squares method to fit the carrier offset. The compensation value is iteratively calculated for each frame of signal and the local oscillator is updated. PBCH decoding uses the soft-decision Viterbi algorithm to improve the synchronization success rate in low signal-to-noise ratio environments, and the path metric calculation uses a weighted fusion of Euclidean distance and Hamming distance; The CP autocorrelation detection module uses a sliding window to calculate the correlation between the cyclic prefix and the data segment. The peak detection threshold is dynamically adjusted according to the noise floor, and the detection result is transmitted to the FPGA interrupt controller via DMA.

5. The method for realizing 4G5G synchronization based on CAT1 module according to claim 1, characterized in that: The delay prediction model includes the following: Based on the LSTM network training historical delay data, the network structure contains 3 layers of hidden units, the input features include link RSSI, channel bandwidth, temperature drift and historical delay sequence, and the output is the predicted value of the transmission path delay in the next cycle; The dynamic correction module adjusts the FPGA trigger pulse phase according to the prediction results, triggers a system-level alarm and switches to the redundant channel when the limit is exceeded.

6. The method for realizing 4G5G synchronization based on CAT1 module according to claim 1, characterized in that: When the main channel fails, the backup channel seizes the bus control through hardware interrupts. The interrupt service program saves the current DMA transfer status to the backup register first, and resumes the transfer after the switch is completed.

7. The method for realizing 4G5G synchronization based on CAT1 module according to claim 1, characterized in that: The FPGA operating temperature is monitored in real time through the on-chip temperature sensor, and the data is input into the temperature-delay mapping table after Kalman filtering; The clock division coefficient is adjusted dynamically, and the temperature drift compensation amount is calculated by the PID controller based on the proportional coefficient and the integral time and adjusted according to the temperature-delay mapping table.

8. The method for realizing 4G5G synchronization based on CAT1 module according to claim 1, characterized in that: Simulate multi-node concurrent requests, use Poisson distribution to generate request intervals, count packet loss rates and synchronization error distributions, and generate test data through hardware accelerators to reduce CPU load; Verification of the system's self-recovery capability includes restoring synchronization accuracy within a preset time after fault injection, without data loss or protocol stack crash.

9. The method for realizing 4G5G synchronization based on CAT1 module according to claim 1, characterized in that: The protocol retransmission times and timeout threshold are dynamically adjusted through reinforcement learning, and the FIR filter coefficients are optimized based on genetic algorithm.

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