PCIe exchange switch testing device and method

Abstract

The invention discloses a PCIe (Peripheral Component Interconnect Express) exchange switch testing device and a PCIe exchange switch testing method, and aims to overcome the defects of long testing time, incapability of comprehensively covering a testing scene and high testing cost in the prior art. The device comprises root complex equipment, executable equipment enumeration, storage space allocation and test process control. An upstream port of the to-be-tested PCIe exchange switch is connected with the root complex device, and a downstream port of the to-be-tested PCIe exchange switch can be in extensible connection with the endpoint device or in cascade connection with other PCIe exchange switches; the end point equipment supports EP-RC, EP-EP transaction routing and data return; the PCIe connector establishes a physical link. The method comprises the following steps: establishing a PCIe link, distributing a bus number and the like, sending test data by utilizing a DMA function, comparing data consistency, marking an abnormal port, resending a test transaction, and polling all ports to complete test coverage. According to the device and the method, the test efficiency can be improved, the cost can be reduced, multi-chip parallel test and abnormal port marking can be realized, and the device and the method are suitable for board-level function test and burn-in test of the PCIe exchange switch.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to a PCIe switch test device and method. Background Art

[0002] In the field of integrated circuit design, for the test of PCIe switches, the commonly used means currently mainly rely on a PC. Specifically, the PC accesses each port in turn to execute the test tasks. This method depends on the computing power of the PC and the test software, and can verify the basic functions of the PCIe switch. The PC tests each port of the switch one by one by sending and receiving PCIe transaction packets to check the accuracy of data transmission and the correctness of the protocol. In addition, in order to further verify the protocol compliance, special tools such as protocol analyzers are usually used to conduct more in-depth protocol tests on the PCIe switch. These tools can capture and analyze the data packets on the PCIe bus to help engineers discover potential problems.

[0003] However, the existing test means have multiple problems and deficiencies. The test time is long because the method of the PC accessing each port in turn is inefficient. Especially when facing a PCIe switch with multiple ports, the test process will become very time-consuming. This method cannot comprehensively cover the scenario of parallel communication of various transaction type PCIe transaction packets, resulting in possible omissions and inaccuracies in the test results. Purchasing special test boards, fixtures, and protocol analyzers and other equipment is not only costly but also complex to operate, and requires a large amount of manpower and time for setup and debugging. These problems seriously affect the test efficiency and accuracy, and bring a lot of inconvenience to production and R & D work.

[0004] Therefore, there is an urgent need for a new technical solution to solve the problems of long test time, inability to comprehensively cover the test scenario, and high test cost, so as to meet the market's demand for efficient, accurate, and economical PCIe switch test means. Summary of the Invention

[0005] The purpose of the present invention is to provide a PCIe switch test device and method to overcome the deficiencies of the prior art in long test time, inability to comprehensively cover the test scenario, and high test cost.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: In the first aspect, the present invention provides a PCIe switch test device, including: A root complex device, with a built-in CPU and test control software, configured to perform device enumeration, storage space allocation, and test process control, and support direct memory access function to achieve concurrent data transmission; The PCIe switch to be tested has its upstream port connected to the root complex device, and its downstream port is extended to connect to the endpoint device or cascade other PCIe switches; At least one endpoint device connected to the downstream port of the PCIe switch to be tested, with built-in DMA function to support EP-RC, EP-EP transaction routing and data return; PCIe connectors are used to establish physical links between the root complex, the switch under test, and the endpoint devices.

[0007] The root complex device and endpoint device are implemented based on FPGA or ASIC hardware and support reducing device enumeration time by solidifying configuration parameters.

[0008] The downstream port of the PCIe switch to be tested forms a tree topology network by cascading other switches to achieve multi-chip parallel testing.

[0009] The device can expand the test scale through tree or serial topology, support multi-port parallel testing and abnormal port marking.

[0010] The abnormal port marking automatically generates a fault report through the test control software of the root complex and records the physical location identification of the abnormal port.

[0011] On the other hand, the present invention provides a PCIe switch testing method, comprising the following steps: Establish a PCIe link between the root complex device and the PCIe switch and endpoint device to be tested, and complete the allocation of bus number, device number and storage space; The root complex device sends test data to the endpoint device through the DMA function, triggering the test data to be transmitted to the downstream endpoint device step by step through the port of the PCIe switch to be tested, and the downstream endpoint device transmits the received test data back to the root complex; The root complex device compares the consistency of the sent test data with the returned data. If they are inconsistent, the abnormal port is marked and the test transaction is resent to distinguish the fault type; Poll all ports of the PCIe switch to be tested, and repeat the test data sending, returning and comparing operations until the test coverage of all ports and transaction types is completed.

[0012] In the allocation of bus numbers, device numbers and storage space, when a cascaded switch to be tested is detected, the bus number allocation range is automatically expanded, and a virtual test path corresponding to the tree topology is generated.

[0013] The test data is multi-threaded concurrent transmission initiated by the DMA function, and the data packet contains a preset checksum and sequence number, covering the functional verification of the physical layer, data link layer and transaction layer.

[0014] When comparing the consistency of the transmitted test data and the feedback data, if an abnormal port is detected, the root complex triggers a retransmission mechanism to verify whether it is a transient error. If the abnormality still exists after retransmission, the faulty port is locked, and a log file containing the fault type, location, and timestamp is generated.

[0015] When repeatedly executing the operations of test data transmission, feedback, and comparison, the port test status, abnormal marking results, and link topology diagram are displayed in real time through a visualization interface, and a comprehensive report containing the test coverage rate, throughput, and bit error rate is generated.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: A PCIe switch test device realizes device enumeration, storage space allocation, and test process control through a root complex device with a built-in CPU and test control software, and supports the direct memory access function to achieve concurrent data transmission, thereby improving the test efficiency. At the same time, the root complex device and endpoint device in the device are implemented based on FPGA or ASIC hardware, and the device enumeration time can be reduced by solidifying configuration parameters, further improving the test speed. In addition, the downstream ports of the PCIe switch to be tested can form a tree topology network by cascading other switches to achieve multi-chip parallel testing and expand the test scale. The device also has the function of marking abnormal ports, and can automatically generate a fault report and record the physical location identifier of the abnormal port, which is convenient for quickly locating and solving problems.

[0017] A PCIe switch test method establishes PCIe links between the root complex device, the PCIe switch to be tested, and the endpoint device, and completes the allocation of bus numbers, device numbers, and storage spaces to ensure the accuracy and comprehensiveness of the test. The test data is transmitted through multi-threaded concurrency initiated by the DMA function, covering the function verification of the physical layer, data link layer, and transaction layer, improving the test efficiency and accuracy. The method also includes comparing the consistency of the transmitted test data and the feedback data. If an abnormal port is detected, the root complex triggers a retransmission mechanism to verify whether it is a transient error. If the abnormality still exists after retransmission, the faulty port is locked, and a log file containing the fault type, location, and timestamp is generated for subsequent fault analysis and processing. In addition, the port test status, abnormal marking results, and link topology diagram are displayed in real time through a visualization interface, and a comprehensive report containing the test coverage rate, throughput, and bit error rate is generated to provide users with detailed test data and analysis results. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a PCIe switch test device in an embodiment of the present invention.

[0019] Figure 2Schematic diagram of a PCIe switch test method in an embodiment of the present invention.

[0020] Figure 3 Principle block diagram of a PCIe switch test device in an embodiment of the present invention.

[0021] Figure 4 Implementation step diagram of a PCIe switch test method in an embodiment of the present invention.

[0022] Figure 5 Connection schematic diagram for testing multiple PCIe switches at one time in an embodiment of the present invention. Detailed implementation manners

[0023] In the field of integrated circuit design, for the testing of PCIe switches, the commonly used means at present are mainly based on a PC. That is, the PC accesses each port in turn to execute the test task. However, this method has multiple problems and deficiencies. It includes the long test time caused by the PC accessing each port in turn. Especially when facing a PCIe switch with multiple ports, the test process will become very time-consuming. In addition, this method cannot fully cover the scenario of parallel communication of PCIe transaction packets of multiple transaction types, resulting in possible omissions and inaccuracies in the test results. Purchasing special test boards, fixtures, protocol analyzers and other equipment not only has a high cost, but also is complex to operate, and requires a lot of manpower and time for setup and debugging. These problems seriously affect the efficiency and accuracy of the test, bringing a lot of inconvenience to production and R & D work.

[0024] Therefore, there is an urgent need for a new technical solution to solve problems such as long test time, inability to fully cover the test scenario, and high test cost, so as to meet the market's demand for efficient, accurate and economical PCIe switch test means. Therefore, how to overcome the deficiencies of the existing PCIe switch test technology in the field of integrated circuit design has become an urgent problem to be solved by those skilled in the art. The present invention proposes a PCIe switch function test device and method, which can be widely applied to the board-level function test and burn-in test of PCIe switches, solves problems such as difficult test and long time consumption caused by multiple ports of PCIe switches, and can build PCIe switch automation by means of existing PCIe root complex (RC) devices and endpoint (EP) devices.

[0025] Next, the technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0026] Refer to Figure 1 As shown, a PCIe switch test device provided in a specific embodiment of the present invention includes: A root complex device, with a built-in CPU and test control software, configured to perform device enumeration, storage space allocation, and test process control, and support direct memory access function to achieve concurrent data transfer; The PCIe switch to be tested, whose upstream port is connected to the root complex device, and the downstream port is extended to connect to endpoint devices or cascade other PCIe switches; At least one endpoint device, connected to the downstream port of the PCIe switch to be tested, with a built-in DMA function to support EP-RC, EP-EP transaction routing, and data return; A PCIe connector, used to establish a physical link between the root complex, the switch to be tested, and the endpoint device.

[0027] The root complex device and the endpoint device are implemented based on FPGA or ASIC hardware, and support reducing device enumeration time by solidifying configuration parameters.

[0028] The downstream ports of the PCIe switch to be tested form a tree topology network by cascading other switches to achieve multi-chip parallel testing.

[0029] The device expands the test scale through a tree or serial topology structure, supports multi-port parallel testing and abnormal port marking.

[0030] The abnormal port marking automatically generates a fault report through the test control software of the root complex and records the physical location identifier of the abnormal port.

[0031] Specifically, the root complex device sends RC-EP memory routing transactions to the endpoint device of port 1 based on enumeration. After receiving the transactions, the endpoint device of port 1 sends the received RC-EP memory transactions to the root complex device and the endpoint device of port 2 respectively, wherein an EP-RC memory routing transaction is sent to the root complex device, and an EP-EP memory routing transaction is sent to the endpoint device of port 2. After receiving the EP-EP memory routing transaction sent by the endpoint device of port 1, the endpoint device of port 2 performs the same operation as the endpoint device of port 0, and so on, polling each port of the PCIe switch to be tested. After the root complex sends the RC-EP memory routing transaction to the endpoint device of port 1, it will receive the EP-RC memory transactions sent by each endpoint device in the divided memory space in turn. The root complex device compares the EP-RC memory transactions returned by each endpoint device with the RC-EP memory transactions sent by itself. If the comparison is successful, the port function of the PCIe switch to be tested corresponding to the endpoint device is normal. If the comparison fails, the port function of the PCIe switch to be tested corresponding to the endpoint device is abnormal, and the root complex device continues to compare the EP-RC memory transaction of the EP corresponding to the port of the next PCIe switch to be tested. If the comparison is successful, the RC-EP routing abnormality of the current PCIe switch port to be tested is recorded. If the comparison still fails, the root complex device sends an RC-EP memory transaction to the endpoint device corresponding to the PCIe switch port to be tested, and compares the EP-RC transaction sent with the EP-RC transaction returned by the endpoint device. If successful, the EP-EP function of the previous PCIe switch port to be tested is marked as abnormal, and subsequent tests are continued. If it fails, the routing function of the current PCIe switch port is marked as abnormal, and the root complex device continues to send RC-EP memory routing transactions to the next PCIe switch port device to be tested, and so on, to complete the test of all ports of the PCIe switch to be tested. The root complex software can realize automatic and rapid testing of PCIe switches.

[0032] Reference Figure 2 A PCIe switch testing method provided in a specific embodiment of the present invention includes the following steps: Establish a PCIe link between the root complex device and the PCIe switch and endpoint device to be tested, and complete the allocation of bus number, device number and storage space; The root complex device sends test data to the endpoint device through the DMA function, triggering the test data to be transmitted to the downstream endpoint device step by step through the port of the PCIe switch to be tested, and the downstream endpoint device transmits the received test data back to the root complex; The root complex device compares the consistency between the transmitted test data and the returned data. If they are inconsistent, the abnormal port is marked, and the test transaction is resubmitted to distinguish the fault type. Poll all ports of the PCIe switch under test, and repeat the operations of sending, returning, and comparing the test data until the test coverage of all ports and transaction types is completed.

[0033] Specifically, an automated rapid test method for a PCIe switch provided by the present invention is as follows: Connect the root complex device, the PCIe switch under test, and several endpoint devices. All ports of the PCIe switch under test automatically initiate link training and establish a PCIe link. The root complex device reads the link status registers of itself and the PCIe switch under test. After determining that the link is successfully established, an enumeration operation is initiated to configure the bus numbers, device numbers, and function numbers of all PCIe devices downstream of the root complex, as well as to configure the base and limit registers of all downstream ports of the PCIe switch under test, and to configure the memory space of the endpoint devices corresponding to all downstream ports of the PCIe switch under test. When a cascaded PCIe switch under test is detected, the bus number allocation range is automatically extended, and a virtual test path corresponding to the tree topology structure is generated.

[0034] The root complex device sends a memory write operation (RC-EP) to the endpoint device (EP0) corresponding to the first port (port 1) of the PCIe switch under test through the DMA function, and writes the data into EP0. The test data is a multi-threaded concurrent transmission initiated through the DMA function, and the data packet contains a preset check code and sequence number, covering the functional verification of the physical layer, data link layer, and transaction layer. After receiving the data sent by the root complex device, EP0 initiates a memory write operation (EP-EP) through the DMA of EP0, and writes the data into the endpoint device (EP1) corresponding to the second port (port 2) of the PCIe switch under test; initiates a memory write operation (EP-RC) through the DMA of EP0, and writes the data into the memory space (EP-RC) corresponding to the root complex device. The root complex device compares the data written by EP0 with the data sent by the root complex to determine whether the routing function of port 2 of the PCIe switch under test is normal.

[0035] After receiving the data sent by EP0, EP1 initiates a memory write operation (EP-EP) through the DMA of EP1, and writes the data into the endpoint device (EP2) corresponding to the third port (port 3) of the PCIe switch under test; initiates a memory write operation (EP-RC) through the DMA of EP1, and writes the data into the memory space corresponding to the root complex device (EP-RC). The root complex device compares the data written by EP1 with the data sent by the root complex to determine whether the routing function of port 2 of the PCIe switch under test is normal. By analogy, after EP(n-2) receives the data sent by EP(n-3), it initiates a memory write operation (EP-EP) through the DMA of EP(n-2), and writes the data into the endpoint device (Epn-2) corresponding to the (n-1)th port (port n-1) of the PCIe switch under test; initiates a memory write operation (EP-RC) through the DMA of EP(n-2), and writes the data into the memory space corresponding to the root complex device (EP-RC). The root complex device compares the data written by EP(n-2) with the data sent by the root complex to determine whether the routing function of port n-1 of the PCIe switch under test is normal. After EP(n-1) receives the data of EP(n-2), it initiates a DMA memory write operation (EP-EP) through EPn, and writes the data into the memory space corresponding to the root complex device under test (EP-RC). The root complex device compares the data written by EP(n-1) with the data sent by the root complex to determine whether the routing function of port n of the PCIe switch under test is normal.

[0036] When the root complex device detects an error in data comparison, it records the port of the PCIe switch under test with the error, and continues to send a memory write transaction to the port of the PCIe switch under test, starting the next cycle. This mechanism ensures the comprehensiveness and accuracy of the test, and can effectively capture and record abnormal situations. The software of the root complex device can be paired with a visualization interface to observe the data test situation in real time. Through the visualization interface, users can intuitively see the port test status, abnormal marking results and link topology diagram. In addition, the system will generate a comprehensive report including test coverage, throughput and bit error rate, providing users with detailed test data and analysis results. In this way, the automated and rapid testing of the PCIe switch can be realized, improving the test efficiency and accuracy, and reducing the test cost.

[0037] In a specific embodiment of the present invention, a scenario using a 48-channel PCIe switch circuit as the switch circuit under test is also provided.

[0038] Refer to Figure 3As shown in the figure, it is the principle block diagram of the PCIe switch test device according to the embodiment of the present invention. The PCIe switch circuit to be tested has 48 channels, and the 48 channels are configured as 8 ports. Among them, port 0 is the upstream port with a link width of x8; ports 1 to 7 are downstream ports with link widths ranging from x8 to x4. The root complex device is an FPGA development board with attached software, and the endpoint devices are all FPGA boards integrated with DMA functions.

[0039] As Figure 3 shown, the root complex device is connected to the upstream port 0 of the PCIe switch to be tested through an x8 PCIe link. The endpoint device EP0 is connected to the downstream port 1 of the PCIe switch to be tested through an x8 PCIe link. The endpoint device EP1 is connected to the downstream port 2 of the PCIe switch to be tested through an x4 PCIe link. The endpoint device EP2 is connected to the downstream port 3 of the PCIe switch to be tested through an x4 PCIe link. The endpoint device EP3 is connected to the downstream port 4 of the PCIe switch to be tested through an x4 PCIe link. The endpoint device EP4 is connected to port 5 of the PCIe switch to be tested through an x8 PCIe link. The endpoint device EP5 is connected to port 6 of the PCIe switch to be tested through an x4 PCIe link. The endpoint device EP6 is connected to port 7 of the PCIe switch to be tested through an x4 PCIe link.

[0040] The root complex device delimits the transmission area space and assigns its own memory space to the corresponding EPs of each port. It assigns the space E0000000 - E000FFFF to EP0; assigns the space E0010000 - E001FFFF to EP1; assigns the space E0020000 - E002FFFF to EP2; assigns the space E0030000 - E003FFFF to EP3; assigns the space E0040000 - E004FFFF to EP4; assigns the space E0050000 - E005FFFF to EP5; assigns the space E0060000 - E006FFFF to EP6.

[0041] After the test starts, the 8 PCIe links corresponding to each port of the PCIe switch to be tested start link training. The root complex device determines whether the 8 PCIe links are successfully established, and assigns bus numbers, device numbers, function numbers, and memory spaces to the PCIe devices corresponding to the successfully established links.

[0042] Figure 4 The implementation steps of a method for testing a PCIe switch to be tested based on the PCIe switch test device according to the embodiment of the present invention include: Step 1: The root complex device determines that all 8 PCIe links below are successfully established, and assigns bus numbers, device numbers, function numbers, and memory spaces to the PCIe switch under test and the EP devices corresponding to all its ports, completing the enumeration process.

[0043] Step 2: The root complex device initiates a DMA write operation and writes the data in its own transmission area into the memory space (BAR) of EP0 through a PCIe RC-EP write transaction; after receiving the data written by the root complex, EP0 initiates a DMA write operation. First, it writes the data in its own BAR space into the range E0000000~E000FFFF allocated by the root complex device for EP0 through a PCIe EP-RC write transaction, and then writes the data in its own BAR space into the BAR space of EP1 through a PCIe EP-EP write transaction. The root complex device compares the data in the transmission area with the data in the range E0000000~E000FFFF written by EP0. If the comparison is successful, it indicates that the routing function of EP0's EP-RC is normal; if the comparison fails, the root complex device initiates a DMA read operation to read the data in EP0's BAR space for further comparison. If the comparison is correct, it indicates that the routing function of EP0's EP-RC is abnormal and records it; if the comparison fails, it indicates that the RC-EP routing function of the root complex is abnormal and records it, and the test is paused.

[0044] Step 3: After receiving the data written by EP0, EP1 initiates a DMA write operation. First, it writes the data in its own BAR space into the range E0010000~E001FFFF allocated by the root complex device for EP1 through a PCIe EP-RC write transaction, and then writes the data in its own BAR space into the BAR space of EP2 through a PCIe EP-EP write transaction. The root complex device compares the data in the transmission area with the data in the range E0010000~E001FFFF written by EP0. If the comparison is successful, it indicates that the routing function of EP1's EP-RC is normal and the EP-EP routing function of EP0 is normal; if the comparison fails, the root complex compares the data in the transmission area with the data in the range E0020000~E002FFFF. If the comparison is successful, it indicates that the EP-EP function of EP1 is normal, the EP-RC function of EP2 is normal, and the EP-RC function of EP1 is abnormal and records it; if the comparison fails, the root complex device initiates a DMA write operation to write the data in its own transmission area into the memory space (BAR) of EP1. After EP1 receives the data written by the root complex, it initiates a DMA write operation. First, it writes the data in its own BAR space into the range E0010000~E001FFFF allocated by the root complex device for EP1 through a PCIe EP-RC write transaction, and then writes the data in its own BAR space into the BAR space of EP2 through a PCIe EP-EP write transaction, and continues the above comparison. If successful, it indicates that the EP-EP function of EP0 is abnormal, otherwise continue the above comparison.

[0045] Steps 4 to 7: Thereafter, each EP is tested in sequence according to the instructions in Step 3.

[0046] Step 8: After EP6 receives the data written by EP5, it initiates a DMA write operation to write the data in its own BAR space to the range E0060000 to E006FFFF divided for EP1 by the PCIe EP-RC write transaction root complex device. The root complex device compares the data in the sending area with the data in the range E0060000 to E006FFFF written by EP6. If the comparison is successful, it indicates that the routing function of the EP-RC of EP5 and the EP-EP routing function of EP6 are normal; if the comparison fails, the root complex device initiates a root DMA write operation to EP6 and writes the data in its own sending area to the memory space (BAR) of EP6 through the PCIe RC-EP write transaction; if the comparison is successful, it indicates that the EP-EP transaction routing of EP5 is abnormal, and if the comparison fails, it indicates that the routing function of EP6 is abnormal.

[0047] The test is completed, and the root complex device records the test results.

[0048] It should be noted that the EP device corresponding to any downstream port can be replaced with another PCIe switch to be tested, such as Figure 5 shown. At this time, the test of two PCIe switches to be tested can be completed in one test. The test process includes: Connect the root complex device to the first PCIe switch to be tested (Switch A). The downstream port of Switch A is connected to the second PCIe switch to be tested (Switch B) through a PCIe connector. All ports of the PCIe switches A and B to be tested automatically start link training and establish a PCIe link. After the root complex device reads the link status registers of itself and the PCIe switches A and B to be tested and determines that the link is successfully established, it initiates an enumeration operation to configure the bus numbers, device numbers, and function numbers of all PCIe devices downstream of the root complex, as well as to configure the base point and limit registers of all downstream ports of the PCIe switches A and B to be tested, and to configure the memory spaces of the endpoint devices corresponding to all downstream ports of the PCIe switches A and B to be tested.

[0049] The root complex device sends a memory write operation (RC-EP) to the endpoint device (EP0) corresponding to the first port (Port 1) of the PCIe switch A to be tested through the DMA function and writes the data to EP0. The test data is a multi-threaded concurrent transmission initiated through the DMA function, and the data packet contains a preset check code and sequence number, covering the function verification of the physical layer, data link layer, and transaction layer.

[0050] After receiving the data sent by the root complex device, EP0 initiates a memory write operation (EP-EP) through the DMA of EP0, and writes the data to the endpoint device (EP1) corresponding to the second port (port 2) of the PCIe switch A under test; initiates a memory write operation (EP-RC) through the DMA of EP0, and writes the data to the memory space corresponding to the root complex device (EP-RC). The root complex device compares the data written by EP0 with the data sent by the root complex to determine whether the routing function of port 2 of the PCIe switch A under test is normal.

[0051] After receiving the data sent by EP0, EP1 initiates a memory write operation (EP-EP) through the DMA of EP1, and writes the data to the endpoint device (EP2) corresponding to the third port (port 3) of the PCIe switch A under test; initiates a memory write operation (EP-RC) through the DMA of EP1, and writes the data to the memory space corresponding to the root complex device (EP-RC). The root complex device compares the data written by EP1 with the data sent by the root complex to determine whether the routing function of port 2 of the PCIe switch A under test is normal.

[0052] And so on. After receiving the data sent by EP(n - 3), EP(n - 2) initiates a memory write operation (EP-EP) through the DMA of EP(n - 2), and writes the data to the endpoint device (Epn - 2) corresponding to the (n - 1)th port (port n - 1) of the PCIe switch A under test; initiates a memory write operation (EP-RC) through the DMA of EP(n - 2), and writes the data to the memory space corresponding to the root complex device (EP-RC). The root complex device compares the data written by EP(n - 2) with the data sent by the root complex to determine whether the routing function of port n - 1 of the PCIe switch A under test is normal.

[0053] After receiving the data of EP(n - 2), EP(n - 1) initiates a DMA memory write operation (EP-EP) through EPn, and writes the data to the corresponding memory space of the PCIe switch B under test (EP-RC). The root complex device compares the data written by EP(n - 1) with the data sent by the root complex to determine whether the routing function of the PCIe switch B under test is normal.

[0054] The root complex device compares the consistency between the sent test data and the returned data. If they are inconsistent, mark the abnormal port and resend the test transaction to distinguish the fault type. If an abnormal port is detected, trigger the retransmission mechanism through the root complex to verify whether it is a transient error. If the abnormality still exists after retransmission, lock the faulty port and generate a log file containing the fault type, location, and timestamp.

[0055] Poll all ports of the PCIe switch A and B to be tested, and repeat the operations of sending, transmitting back, and comparing test data until the test coverage of all ports and transaction types is completed. The port test status, abnormal marking results, and link topology diagram are displayed in real time through a visual interface, and a comprehensive report including test coverage, throughput, and bit error rate is generated.

[0056] Through the above steps, it is possible to complete the test of two PCIe switch circuits to be tested in one test, significantly improving the test efficiency and accuracy and reducing the test cost.

[0057] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions in the specification are only preferred examples of the present invention and are not used to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of the present invention claimed is defined by the appended claims and their equivalents.

Claims

1. A PCIe switch testing device, characterized in that: include: A root complex device with a built-in CPU and test control software configured to perform device enumeration, memory allocation, and test flow control, and to support direct memory access for concurrent data transfer; The PCIe switch to be tested has an upstream port connected to the root complex device, and a downstream port extended to connect to an endpoint device or cascade other PCIe switches; At least one endpoint device connected to the downstream port of the PCIe switch to be tested, with built-in DMA function to support EP-RC, EP-EP transaction routing and data return; The PCIe connector is used to establish a physical link between the root complex, the switch to be tested and the endpoint device.

2. A PCIe switch testing device according to claim 1, characterized in that: The root complex device and the endpoint device are implemented based on FPGA or ASIC hardware, and support reducing device enumeration time by solidifying configuration parameters.

3. A PCIe switch testing device according to claim 1, characterized in that: The downstream port of the PCIe switch to be tested forms a tree topology network by cascading other switches to achieve multi-chip parallel testing.

4. A PCIe switch testing device according to claim 1, characterized in that: The device expands the test scale through a tree or serial topology structure and supports multi-port parallel testing and abnormal port marking.

5. A PCIe switch testing device according to claim 4, characterized in that: The abnormal port mark automatically generates a fault report through the test control software of the root complex and records the physical location identifier of the abnormal port.

6. A PCIe switch testing method, characterized in that: The following steps are involved: Establish a PCIe link between the root complex device and the PCIe switch and endpoint device to be tested, and complete the allocation of bus number, device number and storage space; The root complex device sends test data to the endpoint device through the DMA function, triggering the test data to be transmitted to the downstream endpoint device step by step through the port of the PCIe switch to be tested, and the downstream endpoint device transmits the received test data back to the root complex; The root complex device compares the consistency of the sent test data with the returned data. If they are inconsistent, the abnormal port is marked and the test transaction is resent to distinguish the fault type; All ports of the PCIe switch to be tested are polled, and the test data sending, returning and comparing operations are repeatedly performed until the test coverage of all ports and transaction types is completed.

7. A PCIe switch testing method according to claim 6, characterized in that: In the allocation of the bus number, device number and storage space, when a cascaded switch to be tested is detected, the bus number allocation range is automatically expanded, and a virtual test path corresponding to the tree topology is generated.

8. A PCIe switch testing method according to claim 6, characterized in that: The test data is multi-threaded concurrent transmission initiated by the DMA function, and the data packet contains a preset check code and sequence number, covering the functional verification of the physical layer, data link layer and transaction layer.

9. A PCIe switch testing method according to claim 6, characterized in that: When comparing the consistency of the sent test data and the returned data, if an abnormal port is detected, the root complex triggers a retransmission mechanism to verify whether it is a transient error. If the abnormality still exists after retransmission, the faulty port is locked and a log file containing the fault type, location and timestamp is generated.

10. A PCIe switch testing method according to claim 6, characterized in that: When the test data sending, returning and comparing operations are repeatedly performed, the port test status, abnormal marking results and link topology diagram are displayed in real time through a visual interface, and a comprehensive report including test coverage, throughput and bit error rate is generated.

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