Receiving circuit and chip of LIN transceiver
By introducing a filter module, a detection control module and a comparison module into the reception circuit of the LIN transceiver, and using the detection control module to control the enable state of the comparison module, the problem of high power consumption of the LIN transceiver in the prior art is solved, and zero power consumption and normal communication functions are realized in the sleep state.
Patent Information
- Application Number
- CN202510496849.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-06-24
AI Technical Summary
In the prior art, the conventional structure of the LIN transceiver cannot meet the low power consumption demand. Especially in the field of automotive electronics, when the host domain control terminal equipment sleeps, the LIN transceiver is still in the working state, resulting in high power consumption.
By introducing a filter module, a detection control module and a comparison module into the reception circuit of the LIN transceiver, the detection control module enables the closing of the comparison module when the filtered signal is at a high level, thereby realizing the module's zero power consumption in the sleep state of the LIN transceiver.
It realizes that the detection control circuit and comparison circuit have no quiescent current in the LIN transceiver sleep state, greatly reducing system power consumption, and enables the comparison circuit module to be turned on when the filtered signal is low to perform normal communication.
Smart Images
Figure CN120200870A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit technologies, and particularly to a receiving circuit and a chip of a LIN transceiver. Background Art
[0002] Currently, the receiving circuit of a LIN (Local Interconnect Network) transceiver consists of three parts. As shown in Figure 1 , they are a voltage translation module or a voltage dividing circuit, a comparison module, and an output filtering module. The purpose of using a voltage translation module in the first part is to convert LIN with a high voltage threshold to a low voltage threshold and then provide it to a low voltage comparator for comparison; the purpose of using a voltage dividing circuit is to generate a reference voltage to be provided to the low voltage comparator for comparison with LIN; the second part, the comparison module, inputs the LIN signal level and outputs high and low levels of the low voltage threshold; the third part is a filtering module that filters out the noise and glitch signals of the comparator output signal to obtain a clean output signal.
[0003] A conventional structure can achieve the function of receiving LIN transceiver signals. However, in such a conventional structure, the power consumption of the LIN received signal remains high. Especially in the field of automotive electronics applications, when the host domain control terminal device is in a sleep state, the LIN transceiver is still in an operating state, which runs counter to the goal of the host going to sleep to improve the battery life.
[0004] On the other hand, in traditional technologies, in order to achieve low power consumption, external circuits need to be added as low power consumption conditions. The additional external circuits are not only of various types, greatly increasing the complexity of the circuit structure. This further increases the difficulty of design and manufacturing, and may also cause problems such as signal transmission delay and interference, affecting the overall performance and stability of the device. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to overcome the defect that the conventional structure of a LIN transceiver in the prior art cannot meet the low power consumption requirement, and to provide a receiving circuit and a chip of a LIN transceiver.
[0006] The present invention solves the above technical problem through the following technical solutions:
[0007] In a first aspect, a receiving circuit of a LIN transceiver is provided, which is characterized by comprising a filtering module, a detection control module, and a comparison module connected in sequence;
[0008] The filtering module is configured to receive the LIN signal, filter out the negative voltage signals in a preset negative voltage range in the LIN signal to obtain a filtered signal corresponding to the LIN signal, and send the filtered signal to the detection control module;
[0009] The detection and control module is configured to detect the filtered signal and output a corresponding control signal to the comparison module based on the comparison result between the filtered signal and a preset voltage threshold;
[0010] When the control signal is a low-level control signal, the comparison module is enabled to be turned off.
[0011] Optionally, it further includes a first power control module;
[0012] The first power control module is connected to the detection and control module, and the first power control module is configured to power on or off the detection and control module based on the circuit enable signal of the receiving circuit.
[0013] Optionally, it further includes a second power control module;
[0014] The second power control module is connected to the comparison module, and the second power control module is configured to power on or off the comparison module based on the control signal of the detection and control module;
[0015] The second power control module is further configured to provide a reference voltage to the comparison module;
[0016] The comparison module is further configured to output a comparison result based on the reference voltage and the filtered signal.
[0017] Optionally, the first power control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first diode, a first resistor, and a second resistor;
[0018] The gate of the first transistor is connected to the first end of the first resistor, the source of the first transistor is connected to the second end of the first resistor, and the drain of the first transistor is connected to the power supply voltage;
[0019] The gate of the second transistor is connected to the first end of the first resistor, the source of the second transistor is connected to the cathode of the first diode, and the drain of the second transistor is connected to the power supply terminal of the detection and control module;
[0020] The anode of the first diode is connected to the gate of the second transistor;
[0021] The gate of the third transistor is connected to the first circuit enable signal of the receiving circuit, the source of the third transistor is connected to the drain of the fourth transistor, and the drain of the third transistor is connected to the first end of the first resistor;
[0022] The gate of the fourth transistor is connected to the bias voltage; the source of the fourth transistor is grounded;
[0023] The gate of the fifth transistor is connected to the second circuit enable signal of the receiving circuit, the source of the fifth transistor is grounded, and the drain of the fifth transistor is connected to the first end of the second resistor;
[0024] The second end of the second resistor is connected to the drain of the second transistor;
[0025] Wherein, the first circuit enable signal is opposite to the second circuit enable signal.
[0026] Optionally, the detection control module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a second diode and a buffer;
[0027] The gate of the sixth transistor is connected to the first circuit enable signal of the receiving circuit, the source of the sixth transistor is connected to the drain of the seventh transistor, and the drain of the sixth transistor is connected to the bias current;
[0028] The gate of the seventh transistor is connected to the second circuit enable signal of the receiving circuit, and the source of the seventh transistor is grounded;
[0029] The gate of the eighth transistor is connected to the bias voltage, the source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the bias voltage;
[0030] The gate of the ninth transistor is connected to the gate of the tenth transistor, the source of the ninth transistor is connected to the first power control module, and the drain of the ninth transistor is connected to the drain of the twelfth transistor;
[0031] The source of the tenth transistor is connected to the first power control module, and the drain of the tenth transistor is connected to the anode of the second diode;
[0032] The gate of the eleventh transistor is connected to the filtering signal, the source of the eleventh transistor is connected to the cathode of the second diode, and the drain of the eleventh transistor is connected to the buffer;
[0033] The gate of the twelfth transistor is connected to the bias voltage, and the source of the twelfth transistor is grounded;
[0034] The gate of the thirteenth transistor is connected to the bias voltage, the source of the thirteenth transistor is grounded, and the drain of the thirteenth transistor is connected to the buffer;
[0035] The gate of the fourteenth transistor is connected to the power supply voltage, the source of the fourteenth transistor is connected to the buffer, and the drain of the fourteenth transistor is grounded;
[0036] Among them, the eighth transistor, the twelfth transistor, and the thirteenth transistor are current mirrors;
[0037] The buffer is used to output the control signal.
[0038] Optionally, the second power control module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a third diode, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;
[0039] The gate of the fifteenth transistor is connected to the first end of the third resistor, the source of the fifteenth transistor is connected to the second end of the third resistor, and the drain of the fifteenth transistor is connected to the power supply voltage;
[0040] The gate of the sixteenth transistor is connected to the first end of the third resistor, the source of the sixteenth transistor is connected to the cathode of the third diode, and the drain of the sixteenth transistor is connected to the power supply terminal of the comparison module;
[0041] The anode of the third diode is connected to the gate of the sixteenth transistor;
[0042] The gate of the seventeenth transistor is connected to the first control signal of the detection control module, the source of the seventeenth transistor is connected to the drain of the eighteenth transistor, and the drain of the seventeenth transistor is connected to the first end of the third resistor;
[0043] The gate of the eighteenth transistor is connected to the bias voltage; the source of the eighteenth transistor is grounded;
[0044] The gate of the nineteenth transistor is connected to the second control signal of the detection control module, the source of the nineteenth transistor is grounded, and the drain of the nineteenth transistor is connected to the first end of the sixth resistor;
[0045] The first end of the fourth resistor is connected to the drain of the sixteenth transistor, and the second end of the fourth resistor is connected to the comparison module;
[0046] The first end of the fifth resistor is connected to the second end of the fourth resistor, and the second end of the fifth resistor is connected to the first end of the sixth resistor;
[0047] Among them, the first control signal is opposite to the second control signal.
[0048] Optionally, the comparison module circuit includes a comparator, a twentieth transistor, a twenty-first transistor, and an inverter;
[0049] The gate of the twentieth transistor is connected to the first control signal of the detection control module, the source of the twentieth transistor is connected to the enable terminal of the comparator, and the drain of the twentieth transistor is connected to the bias current;
[0050] The gate of the twenty-first transistor is connected to the output terminal of the inverter, the source of the twenty-first transistor is grounded, and the drain of the fifteenth transistor is connected to the first end of the sixth resistor;
[0051] The reference voltage input terminal of the comparator is connected to the second power supply control module, the comparison voltage terminal of the comparator is connected to the filtered signal, the power supply terminal of the comparator is connected to the second power supply control module, the ground terminal of the comparator is grounded, and the output terminal of the comparator is connected to the input terminal of the inverter;
[0052] The comparator is enabled and turned on based on the control signal of the detection control module, and outputs a signal through the inverter.
[0053] Optionally, the first transistor, the second transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are PMOS transistors;
[0054] The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor, and the twenty-first transistor are NMOS transistors.
[0055] Optionally, the filtering module includes a seventh resistor, a first capacitor, and a fourth diode;
[0056] The first end of the seventh resistor is connected to the input terminal of the filtering module, and the second end of the seventh resistor is connected to the output terminal of the filtering module;
[0057] The first end of the first capacitor is connected to the second end of the third resistor, and the second end of the first capacitor is grounded;
[0058] The anode of the fourth diode is grounded, and the cathode of the fourth diode is connected to the second end of the seventh resistor.
[0059] In a second aspect, a chip is provided, including the receiving circuit of the LIN transceiver described in the first aspect.
[0060] On the basis of conforming to the common knowledge in the art, the above optional conditions can be combined arbitrarily to obtain various preferred examples of the present disclosure.
[0061] The positive and progressive effects of the present invention are as follows: through the detection control module, when the filtered signal is at a high level, the comparison module is enabled to be turned off, and there is no static current in the detection control circuit and the comparison circuit when they are enabled to be turned off, achieving zero power consumption of the module in the sleep state of the LIN transceiver, greatly reducing the system power consumption; when the filtered signal is at a low level, the comparison circuit module is enabled to be turned on for normal communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0062] Figure 1 It is a schematic circuit diagram of the receiving circuit of the LIN transceiver in the prior art;
[0063] Figure 2 It is a first schematic circuit diagram of the receiving circuit of the LIN transceiver provided by an exemplary embodiment of the present disclosure;
[0064] Figure 3 It is a second schematic circuit diagram of the receiving circuit of the LIN transceiver provided by an exemplary embodiment of the present disclosure;
[0065] Figure 4 It is a schematic circuit diagram of the first power control module and the detection control module in the receiving circuit of the LIN transceiver provided by an exemplary embodiment of the present disclosure;
[0066] Figure 5 It is a schematic circuit diagram of the second power control module and the comparison module in the receiving circuit of the LIN transceiver provided by an exemplary embodiment of the present disclosure;
[0067] Figure 6 It is a schematic circuit diagram of the filtering module in the receiving circuit of the LIN transceiver provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0068] The present invention will be further described below by way of embodiments, but the present invention is not limited to the scope of the described embodiments.
[0069] In the embodiments of the present disclosure, prefix words such as "first" and "second" are only used to distinguish different described objects, and have no limiting effect on the position, order, priority, quantity, content, etc. of the described objects. The use of ordinal words and other prefix words for distinguishing described objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. The description of the described objects refers to the description in the claims or the context of the embodiments, and should not constitute unnecessary limitations because of the use of such prefix words. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "a plurality" is two or more.
[0070] Embodiment 1
[0071] This embodiment provides a receiving circuit for a LIN transceiver, as follows Figure 2 shown, which includes a filtering module 100, a detection and control module 200, and a comparison module 300 connected in sequence;
[0072] The filtering module 100 is configured to receive the LIN signal, filter out the negative voltage signal in the preset negative voltage range in the LIN signal to obtain a filtered signal corresponding to the LIN signal, and send the filtered signal to the detection and control module 200;
[0073] Optionally, the input signal is filtered by the filtering module 100 to filter out the noise on the LIN bus. In actual applications, the LIN bus will be affected by external electromagnetic interference, and the interference signal usually appears as a low-voltage noise signal. By filtering out these low-voltage signals, the impact of interference on LIN communication can be effectively reduced, and the anti-interference ability of the system can be improved. For example, if the LIN signal is a -40V to 40V signal, filter out the negative voltage signal in the preset -40V~-0.7V negative voltage range and the noise in the positive voltage range in the LIN signal, and convert the voltage of the LIN signal into a noise-free signal with a voltage of -0.7~40V.
[0074] The detection and control module 200 is configured to detect the filtered signal, and based on the comparison result between the filtered signal and a preset voltage threshold, output a corresponding control signal to the comparison module 300;
[0075] Optionally, a detection and control circuit for high-voltage signals can be used. When the LIN_filter (LIN filtered signal) signal for detection is high, the detection and control circuit outputs a low-level CTRL (control) signal; when the LIN_filter signal is low, the detection and control circuit outputs a high-level CTRL signal, and the high-level CTRL signal is VDD (Voltage-Distributed-Differential, power supply voltage). The level of the CTRL signal output by the detection and control circuit can be used to control the on / off of other modules in the system through logical operations according to requirements to control the overall power consumption of the chip.
[0076] When the control signal is a low-level control signal, the comparison module 300 is disabled and turned off.
[0077] Optionally, based on the control signal obtained from the LIN filtered signal by the detection and control module 200, the comparison module 300 is enabled or disabled based on the corresponding enable signal. Among them, when the LIN_filter filtered signal on the bus is high, the detection and control circuit outputs a low-level CTRL signal. At this time, the comparison module 300 is disabled and turned off, realizing zero static power consumption of the comparison module 300.
[0078] In this solution, through the detection control module 200, when the filtered signal is at a high level, the comparison module 300 is enabled to be turned off. The detection control circuit and the comparison circuit have no static current when enabled to be turned off, achieving zero power consumption of the module in the sleep state of the LIN transceiver and greatly reducing the system power consumption. When the filtered signal is at a low level, the comparison circuit module is enabled to be turned on for normal communication.
[0079] As an implementable solution, as Figure 3 shown, it further includes a first power control module 400;
[0080] The first power control module 400 is connected to the detection control module 200 and is used to power on or off the detection control module 200 based on the circuit enable signal of the receiving circuit;
[0081] In this solution, the first power control module 400 of the receiving circuit supplies power to the detection control module 200. The first power control module 400 powers on or off the detection control module 200 according to the enable signal of the receiving circuit, achieving power supply on demand for the module. When the receiving circuit does not need to work, the relevant modules can be powered off in time, avoiding unnecessary energy consumption and improving the energy efficiency of the entire system.
[0082] As an implementable solution, it further includes a second power control module 500;
[0083] The second power control module 500 is connected to the comparison module 300. The second power control module 500 is used to power on or off the comparison module 300 based on the control signal of the detection control module 200;
[0084] The second power control module 500 is further used to provide a reference voltage to the comparison module 300;
[0085] The comparison module 300 is further used to output a comparison result based on the reference voltage and the filtered signal.
[0086] In this solution, the second power control module 500 powers on or off the comparison module 300 according to the control signal of the detection control module 200, achieving power supply on demand for the module. When the detection control module 200 issues a power-off signal, the comparison module can be powered off in time, avoiding unnecessary energy consumption and improving the energy efficiency of the entire system. In automotive electronic systems, especially in battery-powered application scenarios, such energy-saving measures can effectively extend the service life of the battery and reduce the inconvenience and cost caused by frequent charging or battery replacement.
[0087] As an implementable solution, as Figure 4As shown, the first power control module 400 includes a first transistor MP1, a second transistor MP2, a third transistor MN1, a fourth transistor MN2, a fifth transistor MN3, a first diode D1, a first resistor R1, and a second resistor R2;
[0088] The gate of the first transistor MP1 is connected to the first end of the first resistor R1, the source of the first transistor MP1 is connected to the second end of the first resistor R1, and the drain of the first transistor MP1 is connected to the power supply voltage;
[0089] The gate of the second transistor MP2 is connected to the first end of the first resistor R1, the source of the second transistor MP2 is connected to the cathode of the first diode D1, and the drain of the second transistor MP2 is respectively connected to the power supply terminal of the detection control module 200;
[0090] The anode of the first diode D1 is connected to the gate of the second transistor MP2;
[0091] The gate of the third transistor MN1 is connected to the first circuit enable signal of the receiving circuit, the source of the third transistor MN1 is connected to the drain of the fourth transistor MN2, and the drain of the third transistor MN1 is connected to the first end of the first resistor R1;
[0092] The gate of the fourth transistor MN2 is connected to the bias voltage vbias; the source of the fourth transistor MN2 is grounded;
[0093] The gate of the fifth transistor MN3 is connected to the second circuit enable signal of the receiving circuit, the source of the fifth transistor MN3 is grounded, and the drain of the fifth transistor MN3 is connected to the first end of the second resistor R2;
[0094] The second end of the second resistor F2 is connected to the drain of the second transistor MP2;
[0095] Wherein, the first circuit enable signal ENP (Enable Parallel Input) is opposite to the second circuit enable signal ENN (Enable Negative), and the first control signal CTRL is opposite to the second control signal CTRL_N.
[0096] In this solution, when the first circuit enable signal ENP is high, the third transistor MN1 is enabled to turn on, and the second circuit enable signal ENN enables the fifth transistor MN3 to turn off. The fourth transistor MN2 generates a current in the branch where the third transistor MN1 and the fourth transistor MN2 are located based on the bias voltage vbias, causing a current to flow through the first resistor R1. By reasonably setting the resistance value of the first resistor R1, a large enough voltage drop is obtained to turn on the first transistor MP1 and the second transistor MP2, and the source-drain voltage drop of the first transistor MP1 and the second transistor MP2 approaches zero, so that the voltage at point A1 in the figure is approximately equal to VBAT (Battery Voltage, power supply voltage), providing power supply for the detection control module 200.
[0097] When the first circuit enable signal ENP is low, the third transistor MN1 is enabled to turn off, and no current flows through the branch where the third transistor and the fourth transistor are located. Therefore, no voltage drop is generated across the first resistor R1, and the first transistor MP1 and the second transistor MP2 are turned off. At this time, the second circuit enable signal ENN enables the fifth transistor MN3 to turn on, and the voltage at point A1 is pulled down to a low level by the fifth transistor MN3 through the second resistor R2, turning off the power supply of the detection control module 200.
[0098] Among them, the first circuit enable signal ENP obtains the second circuit enable signal ENN through the corresponding inverter.
[0099] As an implementable solution, the detection control module 200 includes a sixth transistor MN5, a seventh transistor MN4, an eighth transistor MN6, a ninth transistor MP3, a tenth transistor MP4, an eleventh transistor MP5, a twelfth transistor MN7, a thirteenth transistor MN8, a fourteenth transistor MP6, a second diode D2, and a buffer BUF (Buffer);
[0100] The gate of the sixth transistor MN5 is connected to the first circuit enable signal ENP of the receiving circuit, the source of the sixth transistor MN5 is connected to the drain of the seventh transistor MN4, and the drain of the sixth transistor MN5 is connected to the bias current ibias;
[0101] The gate of the seventh transistor MN4 is connected to the second circuit enable signal ENN of the receiving circuit, and the source of the seventh transistor MN4 is grounded;
[0102] The gate of the eighth transistor MN6 is connected to the bias voltage vbias, the source of the eighth transistor MN6 is grounded, and the drain of the eighth transistor MN6 is connected to the bias voltage vbias;
[0103] The gate of the ninth transistor MP3 is connected to the gate of the tenth transistor MP4. The source of the ninth transistor MP3 is connected to the first power control module 400. The drain of the ninth transistor MP3 is connected to the drain of the twelfth transistor MN7.
[0104] The source of the tenth transistor MP4 is connected to the first power control module 400. The drain of the tenth transistor MP4 is connected to the anode of the second diode D2.
[0105] The gate of the eleventh transistor MP5 is connected to the filtering signal LIN_filter. The source of the eleventh transistor MP5 is connected to the cathode of the second diode D2. The drain of the eleventh transistor MP5 is connected to the buffer BUF.
[0106] The gate of the twelfth transistor MN7 is connected to the bias voltage vbias. The source of the twelfth transistor MN7 is grounded.
[0107] The gate of the thirteenth transistor MN8 is connected to the bias voltage vbias. The source of the thirteenth transistor MN8 is grounded. The drain of the thirteenth transistor MN8 is connected to the buffer.
[0108] The gate of the fourteenth transistor MP6 is connected to the power supply voltage VDD. The source of the fourteenth transistor MP6 is connected to the buffer BUF. The drain of the fourteenth transistor MP6 is grounded.
[0109] Among them, the eighth transistor MN5, the twelfth transistor MN7, and the thirteenth transistor MN8 are current mirrors.
[0110] The buffer BUF is used to output the control signal CTRL.
[0111] In this solution, when the first circuit enable signal ENP is high, the first power control module 400 supplies power to the air detection module. The first circuit enable signal ENP enables the sixth transistor MN5 to turn on, and the second circuit enable signal ENN enables the seventh transistor MN4 to turn off. The eighth transistor MN5, the eleventh transistor MN7, and the twelfth transistor MN8 are current mirrors to achieve normal operation. By setting the bias current ibias to the order of hundreds of nA, low-power operation of the detection control module 200 can be achieved.
[0112] When detecting the operation of the air module, when the filtered signal LIN_filter is at a high level, the voltage at the control signal output terminal CTRL is pulled down to a low level by the thirteenth transistor MN8; when the filtered signal LIN_filter is at a low level, the voltage at point B in the figure is pulled up by the tenth transistor MP4 and the eleventh transistor MP5, and the voltage value at point B is clamped near the sum of VDD and the threshold voltage Vthp6 of the fourteenth transistor MP6 by the fourteenth transistor MP6. After passing through the buffer BUFF, the CTRL signal outputs a high level (VDD). The high and low levels of the CTRL signal can perform digital logic operations to control the switches of other modules of the chip to reduce the power consumption of the high-voltage system.
[0113] As an implementable solution, the second power control module 500 includes a fifteenth transistor MP7, a sixteenth transistor MP8, a seventeenth transistor MN9, an eighteenth transistor MN10, a nineteenth transistor MN11, a third diode D3, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;
[0114] The gate of the fifteenth transistor MP7 is connected to the first end of the third resistor R3, the source of the fifteenth transistor MP7 is connected to the second end of the third resistor R3, and the drain of the fifteenth transistor MP7 is connected to the power supply voltage VBAT;
[0115] The gate of the sixteenth transistor MP8 is connected to the first end of the third resistor, the source of the sixteenth transistor MP8 is connected to the cathode of the third diode D3, and the drain of the sixteenth transistor MP8 is connected to the power supply terminal A2 of the comparison module 300;
[0116] The anode of the third diode D3 is connected to the gate of the sixteenth transistor MP8;
[0117] The gate of the seventeenth transistor MN9 is connected to the first control signal CTRL of the detection control module 200, the source of the seventeenth transistor MN9 is connected to the drain of the eighteenth transistor MN10, and the drain of the seventeenth transistor MN9 is connected to the first end of the third resistor D3;
[0118] The gate of the eighteenth transistor MN10 is connected to the bias voltage vbiass; the source of the eighteenth transistor MN10 is grounded;
[0119] The gate of the nineteenth transistor MN11 is connected to the second control signal CTRL_N of the detection control module 200, the source of the nineteenth transistor MN11 is grounded, and the drain of the nineteenth transistor MN11 is connected to the first end of the sixth resistor R6;
[0120] The first end of the fourth resistor R4 is connected to the drain of the sixteenth transistor MP8, and the second end of the fourth resistor R4 is connected to the comparison module 300;
[0121] The first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4, and the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6;
[0122] Among them, the first control signal is opposite to the second control signal.
[0123] In this solution, when the first control signal CTRL is high, the seventeenth transistor MN9 is enabled to turn on, the second control signal CTRL_N enables the nineteenth transistor MN13 to turn off, and the second power control module 500 supplies power to the comparison module 300.
[0124] When the first control signal CTRL is low, the seventeenth transistor MN9 is enabled to turn off, the second control signal CTRL_N enables the nineteenth transistor MN13 to turn on, and the power supply of the comparison module 300 is turned off.
[0125] The first control signal CTRL obtains the second control signal CTRL_N through the corresponding inverter.
[0126] The fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are used as voltage-dividing resistors. When the first control signal CTRL is low, the current flows through the fourth resistor R4. The first end of the fourth resistor R4 is connected to the drain of the sixteenth transistor MP8, and the second end of the fourth resistor R4 is connected to the reference voltage terminal of the comparator. After dividing the power supply voltage VBAT at the drain of the sixteenth transistor MP8, a reference voltage is output to the comparator; the first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is connected to the drain of the nineteenth transistor MN11. It is realized to provide an accurate reference voltage for the comparator.
[0127] As an implementable solution, the comparison module 300 circuit includes a comparator COMP (Comparator), a twentieth transistor MN12, a twenty-first transistor MN13, and an inverter INV;
[0128] The gate of the twentieth transistor MN12 is connected to the first control signal CTRL of the detection control module 200, the source of the twentieth transistor MN12 is connected to the enable terminal of the comparator COMP, and the drain of the twentieth transistor MN12 is connected to the bias current ibias;
[0129] The gate of the twenty-first transistor MN13 is connected to the output terminal of the inverter INV, the source of the twenty-first transistor MN13 is grounded, and the drain of the twenty-first transistor MN13 is connected to the first end of the sixth resistor R6;
[0130] The reference voltage input terminal of the comparator COMP is connected to the second power control module 500, the comparison voltage terminal of the comparator COMP is connected to the filtered signal LIN_filter, the power supply terminal of the comparator COMP is connected to the second power control module 500, the ground terminal of the comparator COMP is grounded, and the output terminal of the comparator COMP is connected to the input terminal of the inverter INV;
[0131] The comparator COMP is enabled and turned on based on the control signal CTRL of the detection control module 200, and outputs a signal through the inverter INV.
[0132] In this solution, when the first control signal CTRL is high, the seventeenth transistor MN9 is enabled and turned on, the second control signal CTRL_N enables the nineteenth transistor MN13 to be turned off, and the drain voltage of the sixteenth transistor MP8 is approximately equal to VBAT, that is, the supply voltage A2 of the comparison module 300 is approximately equal to VBAT, and the second power control module 500 supplies power to the comparison module 300.
[0133] At this time, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are connected in series to the ground, and the reference voltage of the comparator COMP is determined by the resistance values of the voltage-dividing resistors. The bias current ibias is set at a lower level to achieve low power consumption of the circuit.
[0134] When the level of the filtered signal LIN_filter is higher than the reference voltage, the output signal OUT of the comparator COMP is low, and after passing through the inverter INV, it is a high level (VDD). This high level turns on the twenty-first transistor MN13 and shorts the sixth resistor R6 to achieve the hysteresis of the comparator COMP; when the level of the filtered signal LIN_filte is lower than the reference voltage, the output signal OUT of the comparator COMP is at a low level, and this low level turns off the twenty-first transistor MN13.
[0135] When the first control signal CTRL is low, the seventeenth transistor MN9 is enabled and turned off, the second control signal CTRL_N enables the nineteenth transistor MN13 to be turned on, and the drain voltage of the sixteenth transistor MP8 passes through the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 and is pulled down to a low level by the nineteenth transistor MN11. At this time, the twentieth transistor MN12 is turned off based on the low-level signal of the first control signal CTRL, enabling the comparator COMP to be turned off, and achieving zero current and zero static power consumption of the comparison module 300.
[0136] As an implementable solution, the first transistor MP1, the second transistor MP2, the ninth transistor MP3, the tenth transistor MP4, the eleventh transistor MP5, the fourteenth transistor MP6, the fifteenth transistor MP7, and the sixteenth transistor MP8 are PMOS transistors;
[0137] The third transistor MN1, the fourth transistor MN2, the fifth transistor MN3, the sixth transistor MN4, the seventh transistor MN5, the eighth transistor MN6, the twelfth transistor MN7, the thirteenth transistor MN8, the seventeenth transistor MN9, the eighteenth transistor MN10, the nineteenth transistor MN11, the twentieth transistor MN12, and the twenty-first transistor MN13 are NMOS transistors.
[0138] In this solution, the characteristic that a PMOS transistor hardly consumes static current in the cut-off state is utilized to reduce the power consumption of the entire circuit. At the same time, the PMOS transistor has a relatively high noise margin in the circuit, which can resist the interference of external noise and ensure the stable operation of the circuit; the characteristic that an NMOS transistor has a high electron mobility is utilized to more effectively conduct current, reduce the power loss in the circuit, and achieve a faster switching speed.
[0139] As an implementable solution, as Figure 6 shown, the filtering module 100 includes a seventh resistor R7, a first capacitor C1, and a fourth diode D4;
[0140] The first end of the seventh resistor R7 is connected to the input end of the filtering module 100, and the second end of the seventh resistor R7 is connected to the output end of the filtering module 100;
[0141] The first end of the first capacitor C1 is connected to the second end of the seventh resistor R7, and the second end of the first capacitor C1 is grounded;
[0142] The anode of the fourth diode D4 is grounded, and the cathode of the fourth diode D4 is connected to the second end of the seventh resistor R7.
[0143] In this solution, the seventh resistor R7 and the first capacitor C1 form an RC circuit to filter the interference signal of the LIN signal; when the LIN signal is negative, the negative voltage signal lower than the preset voltage threshold is filtered by the fourth diode D4.
[0144] The receiving circuit of the LIN transceiver provided in this embodiment enables the comparison module to be turned off when the filtering signal is at a high level through the detection control module. There is no static current in the detection control circuit and the comparison circuit when they are enabled to be turned off, achieving zero power consumption of the module in the sleep state of the LIN transceiver and greatly reducing the system power consumption. When the filtering signal is at a low level, the comparison circuit module is enabled to be turned on for normal communication.
[0145] Embodiment 2
[0146] This embodiment provides a chip including the receiving circuit of the LIN transceiver in Embodiment 1.
[0147] The chip provided in this embodiment utilizes the receiving circuit of the LIN transceiver in the chip to enable the comparison module to be turned off when the filtering signal is at a high level. There is no static current in the detection control circuit and the comparison circuit when they are enabled to be turned off, achieving zero power consumption of the module in the sleep state of the LIN transceiver and greatly reducing the system power consumption, realizing low-power control of the chip. When the filtering signal is at a low level, the comparison circuit module is enabled to be turned on for normal communication to ensure the communication function of the chip.
[0148] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that this is only for illustration purposes. The protection scope of the present invention is defined by the appended claims. Without departing from the principles and essence of the present invention, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present invention.
Claims
1. A receiving circuit of a LIN transceiver, characterized in that: It includes a filtering module, a detection control module and a comparison module connected in sequence; The filtering module is used for receiving a LIN signal and filtering out a negative voltage signal in a preset negative voltage interval in the LIN signal to obtain a filtered signal corresponding to the LIN signal, and sending the filtered signal to the detection control module; The detection control module is used to detect the filtered signal and output a corresponding control signal to the comparison module based on a comparison result between the filtered signal and a preset voltage threshold; When the control signal is a low level control signal, the comparison module is enabled and turned off.
2. The receiving circuit of the LIN transceiver according to claim 1, characterized in that: Also included is a first power control module; The first power control module and the detection control module, the first power control module is used to power on or off the detection control module based on the circuit enable signal of the receiving circuit.
3. The receiving circuit of the LIN transceiver according to claim 2, characterized in that: Also included is a second power supply control module; The second power control module is connected to the comparison module, and the second power control module is used to power on or off the comparison module based on the control signal of the detection control module; The second power supply control module is also used to provide a reference voltage to the comparison module; The comparison module is further configured to output a comparison result based on the reference voltage and the filtered signal.
4. The receiving circuit of the LIN transceiver according to claim 3, characterized in that: The first power control module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first diode, a first resistor and a second resistor; The gate of the first transistor is connected to the first end of the first resistor, the source of the first transistor is connected to the second end of the first resistor, and the drain of the first transistor is connected to a power supply voltage; The gate of the second transistor is connected to the first end of the first resistor, the source of the second transistor is connected to the cathode of the first diode, and the drain of the second transistor is connected to the power supply end of the detection control module; An anode of the first diode is connected to a gate of the second transistor; The gate of the third transistor is connected to the first circuit enable signal of the receiving circuit, the source of the third transistor is connected to the drain of the fourth transistor, and the drain of the third transistor is connected to the first end of the first resistor; The gate of the fourth transistor is connected to the bias voltage; the source of the fourth transistor is grounded; The gate of the fifth transistor is connected to the second circuit enable signal of the receiving circuit, the source of the fifth transistor is grounded, and the drain of the fifth transistor is connected to the first end of the second resistor; The second end of the second resistor is connected to the drain of the second transistor; The first circuit enable signal is opposite to the second circuit enable signal.
5. The receiving circuit of the LIN transceiver according to claim 4, characterized in that: The detection control module includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a second diode and a buffer; The gate of the sixth transistor is connected to the first circuit enable signal of the receiving circuit, the source of the sixth transistor is connected to the drain of the seventh transistor, and the drain of the sixth transistor is connected to the bias current; The gate of the seventh transistor is connected to the second circuit enable signal of the receiving circuit, and the source of the seventh transistor is grounded; The gate of the eighth transistor is connected to the bias voltage, the source of the eighth transistor is grounded, and the drain of the eighth transistor is connected to the bias voltage; The gate of the ninth transistor is connected to the gate of the tenth transistor, the source of the ninth transistor is connected to the first power control module, and the drain of the ninth transistor is connected to the drain of the twelfth transistor; The source of the tenth transistor is connected to the first power control module, and the drain of the tenth transistor is connected to the anode of the second diode; The gate of the eleventh transistor is connected to the filter signal, the source of the eleventh transistor is connected to the cathode of the second diode, and the drain of the eleventh transistor is connected to the buffer; The gate of the twelfth transistor is connected to the bias voltage, and the source of the twelfth transistor is grounded; The gate of the thirteenth transistor is connected to the bias voltage, the source of the thirteenth transistor is grounded, and the drain of the thirteenth transistor is connected to the buffer; The gate of the fourteenth transistor is connected to the power supply voltage, the source of the fourteenth transistor is connected to the buffer, and the drain of the fourteenth transistor is grounded; wherein the eighth transistor, the twelfth transistor and the thirteenth transistor are current mirrors; The buffer is used to output the control signal.
6. The receiving circuit of the LIN transceiver according to claim 5, characterized in that: The second power control module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a third diode, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor; The gate of the fifteenth transistor is connected to the first end of the third resistor, the source of the fifteenth transistor is connected to the second end of the third resistor, and the drain of the fifteenth transistor is connected to a power supply voltage; The gate of the sixteenth transistor is connected to the first end of the third resistor, the source of the sixteenth transistor is connected to the cathode of the third diode, and the drain of the sixteenth transistor is connected to the power supply end of the comparison module; An anode of the third diode is connected to the gate of the sixteenth transistor; The gate of the seventeenth transistor is connected to the first control signal of the detection control module, the source of the seventeenth transistor is connected to the drain of the eighteenth transistor, and the drain of the seventeenth transistor is connected to the first end of the third resistor; The gate of the eighteenth transistor is connected to the bias voltage; the source of the eighteenth transistor is grounded; The gate of the nineteenth transistor is connected to the second control signal of the detection control module, the source of the nineteenth transistor is grounded, and the drain of the nineteenth transistor is connected to the first end of the sixth resistor; A first end of the fourth resistor is connected to the drain of the sixteenth transistor, and a second end of the fourth resistor is connected to the comparison module; The first end of the fifth resistor is connected to the second end of the fourth resistor, and the second end of the fifth resistor is connected to the first end of the sixth resistor; The first control signal is opposite to the second control signal.
7. The receiving circuit of the LIN transceiver according to claim 6, characterized in that: The comparison module circuit includes a comparator, a twentieth transistor, a twenty-first transistor and an inverter; The gate of the 20th transistor is connected to the first control signal of the detection control module, the source of the 20th transistor is connected to the enable terminal of the comparator, and the drain of the 20th transistor is connected to the bias current; The gate of the twenty-first transistor is connected to the output end of the inverter, the source of the twenty-first transistor is grounded, and the drain of the fifteenth transistor is connected to the first end of the sixth resistor; The reference voltage input terminal of the comparator is connected to the second power supply control module, the comparison voltage terminal of the comparator is connected to the filtered signal, the power supply terminal of the comparator is connected to the second power supply control module, the ground terminal of the comparator is grounded, and the output terminal of the comparator is connected to the input terminal of the inverter; The comparator is enabled to be turned on based on the control signal of the detection control module, and outputs a signal through the inverter.
8. The receiving circuit of the LIN transceiver according to claim 7, characterized in that: The first transistor, the second transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor are PMOS transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the twelfth transistor, the thirteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, the twentieth transistor and the twenty-first transistor are NMOS transistors.
9. The receiving circuit of the LIN transceiver according to any one of claims 1 to 8, characterized in that: The filtering module includes a seventh resistor, a first capacitor and a fourth diode; The first end of the seventh resistor is connected to the input end of the filter module, and the second end of the seventh resistor is connected to the output end of the filter module; The first end of the first capacitor is connected to the second end of the seventh resistor, and the second end of the first capacitor is grounded; An anode of the fourth diode is grounded, and a cathode of the fourth diode is connected to the second end of the seventh resistor.
10. A chip, characterized in that: A receiving circuit comprising the LIN transceiver according to any one of claims 1 to 9.