Synchronization method, synchronization device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a synchronization method, a synchronization device, electronic equipment and a storage medium. The synchronization method comprises the following steps: aiming at a thread bundle comprising a plurality of threads, distributing a synchronization channel for a first instruction; the first instruction and the second instruction are synchronized based on the synchronization channels, a dependency relationship exists between the first instruction and the second instruction, the thread bundle corresponds to a plurality of synchronization channel groups, each synchronization channel group comprises at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions. The synchronization method uses a synchronization channel mechanism based on an instruction type to realize synchronization of instructions in the thread bundle, effectively realizes decoupling of synchronization channels used by different types of instructions, and expands the number of synchronization channels, thereby improving the processing capability of the thread bundle for a workload, and improving the processing efficiency of the thread bundle. And challenges brought by continuously increasing workloads in the thread bundle can be effectively handled.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a synchronization method, a synchronization device, an electronic device, and a storage medium. Background Art

[0002] Operand dependence refers to the situation in computer architecture, especially in the context of instruction-level parallelism and pipelining, where the operands (i.e., input data) of an instruction depend on the execution results of previous instructions. The handling of operand dependence of instructions is one of the keys to the correct execution of a program, and has an important impact on program performance and compiler scheduling strategies. By optimizing the handling of operand dependence, the execution efficiency of the program can be improved, and it helps the compiler to formulate more effective instruction scheduling strategies, thereby maximizing the utilization of processor resources, reducing waiting time, and increasing throughput. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a synchronization method, including: allocating a synchronization channel for a first instruction for a warp including multiple threads; synchronizing the first instruction and a second instruction based on the synchronization channel, where there is a dependence relationship between the first instruction and the second instruction, the warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0004] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the allocating a synchronization channel for the first instruction includes: determining the synchronization channel group corresponding to the first instruction based on the type of the first instruction; allocating a synchronization channel in the synchronization channel group for the first instruction.

[0005] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier, and the allocating a synchronization channel in the synchronization channel group for the first instruction includes: allocating, according to the synchronization channel identifier, a synchronization channel in the synchronization channel group that corresponds to the synchronization channel identifier for the first instruction.

[0006] For example, in the synchronization method provided by at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter, and the synchronization counter is used for counting based on the instruction execution situation.

[0007] For example, in the synchronization method provided by at least one embodiment of the present disclosure, for a synchronization channel including a single synchronization counter, synchronizing the first instruction and the second instruction based on the synchronization channel includes: in response to issuing the first instruction, incrementing the count of the synchronization counter; in response to the completion of the task corresponding to the first instruction, decrementing the count of the synchronization counter; waiting for the synchronization counter to be cleared, and in response to the synchronization counter being cleared, allowing the second instruction to start execution.

[0008] For example, in the synchronization method provided by at least one embodiment of the present disclosure, for a synchronization channel including multiple synchronization counters, synchronizing the first instruction and the second instruction based on the synchronization channel includes: in response to issuing the first instruction, incrementing the count of the current synchronization counter; in response to the count of the current synchronization counter reaching a preset value, jumping to the next synchronization counter as the current synchronization counter for subsequent counting; in response to the completion of the task corresponding to the first instruction, decrementing the count of the corresponding synchronization counter; waiting for a preset number of synchronization counters to be cleared or waiting for all counted synchronization counters to be cleared, and in response to the clearing, allowing the second instruction to start execution.

[0009] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the instruction types corresponding to the same synchronization channel group are the same.

[0010] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the first instruction is a variable-length instruction.

[0011] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction, or a cache operation instruction.

[0012] For example, in the synchronization method provided by at least one embodiment of the present disclosure, the synchronization method is executed by a warp instruction scheduler.

[0013] At least one embodiment of the present disclosure provides a synchronization device, including: an allocation module configured to allocate a synchronization channel for a first instruction for a warp including multiple threads; a synchronization module configured to synchronize the first instruction and the second instruction based on the synchronization channel, where there is a dependency relationship between the first instruction and the second instruction, the warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0014] At least one embodiment of the present disclosure provides an electronic device, which includes: at least one processor; at least one memory storing one or more computer program modules; wherein, the one or more computer program modules are configured to be executed by the at least one processor for executing instructions for implementing the synchronization method according to any embodiment of the present disclosure.

[0015] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, on which computer-readable instructions are stored, wherein, when the computer-readable instructions are executed by at least one processor, the synchronization method according to any embodiment of the present disclosure is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0017] Figure 1A It is a schematic block diagram of a streaming multi-processor provided by at least one embodiment of the present disclosure.

[0018] Figure 1B It is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0019] Figure 1C It is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0020] Figure 1D It is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0021] Figure 2 It is an exemplary schematic diagram of a synchronization method provided by at least one embodiment of the present disclosure;

[0022] Figure 3 It is an exemplary schematic diagram of a synchronization method provided by at least one embodiment of the present disclosure;

[0023] Figure 4 It is a schematic block diagram of a synchronization device provided by at least one embodiment of the present disclosure;

[0024] Figure 5 It is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0025] Figure 6 It is a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

[0026] Figure 7 It is a schematic block diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and the like used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "including" or "comprising" and the like mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] The present disclosure will be described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known components (elements) may be omitted. When any component (element) of the embodiments of the present disclosure appears in more than one drawing, the component (element) is denoted by the same or similar reference numerals in each drawing.

[0030] Operand dependence refers to the situation in computer architecture, especially in the context of instruction-level parallelism and pipelining, where the operands (i.e., input data) of a certain instruction depend on the execution results of previous instructions. The handling of operand dependencies of instructions is one of the keys to the correct execution of a program, and has an important impact on program performance and compiler scheduling strategies. By optimizing the handling of operand dependencies, the execution efficiency of the program can be improved, and it helps the compiler to develop more effective instruction scheduling strategies, thereby maximizing the utilization of processor resources, reducing waiting time, and increasing throughput.

[0031] Instructions can be classified into fixed-length instructions and variable-length instructions according to the determinacy of the instruction completion time. For fixed-length instructions, such as arithmetic operation (addition, subtraction, multiplication, division, etc.) instructions, the number of execution cycles (Cycles) is determined. At compile time, it can be determined how many cycles each instruction needs to complete, which enables the compiler to effectively perform instruction scheduling. For example, if it is known that an addition instruction takes 3 cycles to complete and the result of this addition instruction is relied on by subsequent instructions, then the compiler can arrange for the subsequent instructions to start execution at least in the 4th cycle. For variable-length instructions, such as memory load (Load) instructions, their completion time is affected by various factors, including but not limited to bus contention, cache hit rate, main memory access latency, etc. Therefore, the actual completion time of such instructions cannot be accurately known at compile time. Due to this uncertainty, it is difficult for the compiler to directly schedule subsequent instructions with operand dependencies. With the increase in complex computing requirements, more and more scenarios involve the use of variable-length instructions, such as memory read and write operations, general matrix multiplication (GEMM) operations, transcendental function (such as square function, square root function, trigonometric function, etc.) calculations, cache operations, etc.

[0032] In the process of performing high-performance parallel computing using accelerators such as Graphics Processing Unit (GPU) or General-purpose Graphics Processing Unit (GPGPU), a large number of threads are utilized to achieve high concurrency. Multiple threads can be grouped into warps, and each warp includes a fixed number (or less than this fixed number) of threads. For example, 32 threads. These threads execute the same instructions in a single instruction multiple threads (SIMT) manner, only processing different data. In a warp, each thread can share some register resources with other threads, and at the same time, each thread also has its own independent register resources for loading or calculating different data. In each computing unit, the warps are scheduled and allocated so that multiple computing cores in the computing unit can run the warps. According to the number of computing cores in the computing unit, multiple warps in a thread block can execute simultaneously or time-share. There is no direct data interaction supported between different warps, but data exchange and synchronization can be achieved by using shared memory.

[0033] In the traditional GPU programming model, the core idea is to achieve high-throughput computing through a large number of concurrently executed threads and warps. When a warp is in a waiting state, other warps can continue to execute, thereby masking latency through thread scheduling and improving the running efficiency. In recent years, with the growth of the processing requirements of artificial intelligence (AI) and large models, such as when dealing with complex operations involving large-scale matrix multiplication, the tasks that a single warp needs to execute have become more complex and intensive, making it difficult to mask latency relying on a large number of warps as in the traditional solution. Therefore, the current GPU programming model tends to enable fewer warps. For example, assuming that a computing unit can theoretically support up to 16 warps to be active simultaneously, for the current GPU programming model, only 3 warps may be selected to be enabled. The adjustment of the above programming model significantly increases the workload of a single warp. Facing a large amount of workload, the increasing number of variable-length instructions, and the development of double buffering and triple buffering technologies, how to optimize the synchronization mechanism within the warp has become an issue that urgently needs attention currently.

[0034] At least one embodiment of the present disclosure provides a synchronization method, which includes: for a warp including multiple threads, allocating a synchronization channel for a first instruction; synchronizing the first instruction and a second instruction based on the synchronization channel, where there is a dependency relationship between the first instruction and the second instruction, the warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0035] The synchronization method provided by at least one embodiment of the present disclosure uses a synchronization channel mechanism based on instruction types to achieve the synchronization of instructions within a warp, effectively decouples the synchronization channels used by different types of instructions, expands the number of synchronization channels, thereby enhancing the processing ability of the warp for the workload, and can effectively cope with the challenges brought by the increasing workload in the warp.

[0036] For example, the synchronization method provided by at least one embodiment of the present disclosure can be applied to a processor, and the processor includes a graphics processor or a general-purpose graphics processor. Of course, the embodiments of the present disclosure are not limited thereto, and the processor can also be any other type of processor.

[0037] Figure 1ASchematic block diagram of a Streaming Multiprocessor (SM) provided by at least one embodiment of the present disclosure. Each streaming multiprocessor 10 can execute multiple warps simultaneously. The execution between different warps can be independent or sequential. In some examples, the synchronization method provided by at least one embodiment of the present disclosure can be applied to, for example, Figure 1A the streaming multiprocessor 10 shown.

[0038] As Figure 1A shown, the streaming multiprocessor 10 includes an instruction cache 11 (Instruction Cache) for storing multiple instructions of a kernel. The streaming multiprocessor 10 also includes a warp instruction scheduler 12 (Warp Instruction Scheduler) for extracting a series of instructions for each warp and storing them in the instruction cache 11, and obtaining the instructions to be executed from the instruction cache 11 for each warp according to the program counter. Each warp has an independent program counter (Program Counter, PC) register for recording the position of the instruction being executed (i.e., the instruction address). Whenever an instruction is fetched from the instruction cache for a warp, the corresponding program counter is incremented by one. The warp instruction scheduler 12 sends the instructions to the arithmetic logic unit 13 (Arithmetic Logical Unit, ALU), the special function unit 14 (Special Function Unit, SFU), or the load store unit 15 (Load Store Unit, LSU) for execution at an appropriate time point, and these instructions are defined in the instruction set architecture (Instruction Set Architecture, ISA) of a specific computing system.

[0039] The arithmetic logic unit 13 can perform various operations, such as addition and multiplication calculations of integers and floating-point numbers, comparison operations, Boolean operations, bit shifts, etc. During the execution, the arithmetic logic unit 13 can read data from a specified position (also known as the source address) of the general-purpose register 16 (General-Purpose Register, GPR) and write back the execution result to a specified position (also known as the destination address) of the general-purpose register 16. The special function unit 14 can implement various mathematical operations (such as reciprocal, square root, trigonometric functions, etc.). The load store unit 15 can execute load and store instructions and is responsible for handling memory load and store operations.

[0040] The streaming multi-processor 10 further includes a Barriers Register 17, which can be used to enable software to synchronize the execution between different warps, and a Resource-per-warp Register 18, which can be used to enable software to dynamically configure the space range of the general-purpose registers 16 that each warp can use during execution. It should be noted that Figure 1A The illustrated streaming multi-processor is only an example, and those of ordinary skill in the art can understand that the streaming multi-processor may further include more or fewer components. For example, the streaming multi-processor may further include components such as shared memory and a Level 1 Cache.

[0041] For example, the synchronization method provided by at least one embodiment of the present disclosure can be executed by Figure 1A the warp instruction scheduler 12 shown.

[0042] Figure 1B is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0043] For example, as Figure 1B shown, the synchronization method provided by at least one embodiment of the present disclosure includes the following steps S101 to S102.

[0044] Step S101: Allocate a synchronization channel for a first instruction for a warp including multiple threads.

[0045] For example, in step S101, the first instruction is executed by the threads within the warp. For example, the first instruction may be an instruction that requires synchronization, such as an instruction having an operand dependency with other instructions. For example, the instructions that require synchronization in the instruction stream of the warp can be identified according to the instruction type, and a synchronization channel can be allocated for it. For example, the synchronization channel may be located in the Figure 1A Barriers Register 17 shown.

[0046] For example, the first instruction may be a variable-length instruction, and the definition of the variable-length instruction has been introduced above and will not be elaborated here. For example, variable-length instructions include, but are not limited to, data transfer instructions, general matrix multiplication instructions, transcendental function instructions, or cache operation instructions, etc. For example, data transfer instructions may include load instructions and store instructions for reading and writing memory. For example, general matrix multiplication instructions include, but are not limited to, the load instructions and store instructions required for performing general matrix multiplication, and the calculation instructions for performing general matrix multiplication, such as Fused Multiply Add (FMA) instructions, etc. For example, transcendental function instructions may be instructions for calculating special functions such as square functions, root functions, and trigonometric functions. Transcendental function instructions can be executed by Figure 1AIt is executed by the special function unit 14 shown. For example, cache operation instructions may include Flush instructions, Ack instructions, Invalidate instructions, Fence instructions, etc. According to the actual situation, variable-length instructions may also include more instructions. The above are only some examples, and the embodiments of the present disclosure do not limit this.

[0047] Step S102: Synchronize the first instruction and the second instruction based on a synchronization channel, where there is a dependency relationship between the first instruction and the second instruction, and the warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0048] For example, in step S102, each warp has a corresponding multiple synchronization channel groups. The setting of the synchronization channel groups is to achieve synchronization within the warp. The GPU hardware can maintain multiple synchronization channel groups for each warp, and different synchronization channel groups may include different numbers of synchronization channels. Moreover, different synchronization channel groups correspond to different types of instructions, and the instruction types corresponding to the same synchronization channel group are the same.

[0049] For example, instructions can be divided into different types according to the functions of the instructions. In some examples, instruction types can be classified as data transfer instructions, general matrix multiplication instructions, transcendental function instructions, cache operation instructions, etc. In some examples, the above instruction types can also be further divided. For example, cache operation instructions can be divided into finer-grained instruction types, such as Flush instructions, Ack instructions, Invalidate instructions, Fence instructions, etc. The division method of instruction types can be set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0050] For example, the number of synchronization channels in the synchronization channel group corresponding to a certain type of instruction can be determined according to the usage frequency of the instruction. The number of synchronization channels in different synchronization channel groups can be determined according to the actual task requirements, and the embodiments of the present disclosure do not limit this.

[0051] For example, in step S102, there is an operand dependence relationship between the first instruction and the second instruction, that is, the operand of the second instruction depends on the execution result of the first instruction. The first instruction is also called the producer instruction, and the second instruction is also called the consumer instruction. The consumer instruction uses the data generated by the producer instruction to complete its operation. Based on the synchronization channel allocated for the first instruction, it can be determined when the task corresponding to the first instruction is completed, and the second instruction can be executed in a timely manner, thereby realizing the synchronization of the first instruction and the second instruction. For example, if the first instruction is a load instruction and 100 items of data need to be loaded, the same synchronization channel can be allocated for 100 load instructions. The second instruction is an arithmetic operation instruction that needs to perform operations based on these 100 items of data. Based on the synchronization channel allocated for the load instruction, it can be determined when these 100 items of data are loaded, and then the arithmetic operation instruction is executed to perform operations on them, thereby realizing the synchronization of the load instruction and the arithmetic operation instruction.

[0052] In some examples, both the first instruction and the second instruction can be variable-length instructions, and the operand of the second instruction depends on the execution result of the first instruction, and the operand of the third instruction depends on the execution result of the second instruction. At this time, different synchronization channels can be allocated for the first instruction and the second instruction respectively. Based on the synchronization channel allocated for the first instruction, the synchronization of the first instruction and the second instruction can be realized, and based on the synchronization channel allocated for the second instruction, the synchronization of the second instruction and the third instruction can be realized. By analogy, the synchronization of more instructions can also be realized, and the embodiments of the present disclosure do not limit this.

[0053] The synchronization method provided by at least one of the above embodiments of the present disclosure uses a synchronization channel mechanism based on instruction types to realize the synchronization of instructions within a warp, effectively realizing the decoupling of the synchronization channels used by different types of instructions, which will be specifically illustrated by the following examples.

[0054] For example, in some traditional solutions, a fixed number of synchronization channels (for example, M, where M is a positive integer) can be set for each warp. This solution makes different types of instructions need to compete for these M synchronization channels to achieve instruction synchronization. Suppose three synchronization channels are set for each warp, and different types of instructions will compete for these three synchronization channels. If the three synchronization channels have been occupied by three groups of data transfer instructions, then other data transfer instructions or other types of instructions (such as transcendental function instructions) need to wait for one of the data transfer instructions to complete the task and release the occupied synchronization channel before they can obtain the synchronization channel for subsequent processing.

[0055] In the synchronization method provided in the above embodiments of the present disclosure, different types of instructions use different synchronization channels. For example, the synchronization channel group corresponding to the data transfer instruction (referred to as the first synchronization channel group for short) includes three synchronization channels, and the synchronization channel group corresponding to the transcendental function instruction (referred to as the second synchronization channel group for short) includes one synchronization channel. At this time, if three groups of data transfer instructions respectively occupy the three synchronization channels of the first synchronization channel group, it will not have any impact on other types of instructions. For example, the transcendental function instruction will use the synchronization channel of the second synchronization channel group and does not need to wait for the synchronization channels of the first synchronization channel group to be released. Compared with the solution of setting a fixed number of synchronization channels for each warp, the synchronization method provided in the embodiments of the present disclosure effectively decouples the synchronization channels used by different types of instructions, expands the number of synchronization channels, thereby enhancing the processing ability of the warp for the workload, and can effectively cope with the challenges brought by the increasing workload in the warp.

[0056] Figure 1C It is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0057] For example, as Figure 1C shown, in the synchronization method provided by at least one embodiment of the present disclosure, an example of the above step S101 may include the following steps S201 to step S202.

[0058] Step S201: Determine the synchronization channel group corresponding to the first instruction based on the type of the first instruction.

[0059] Step S202: Allocate a synchronization channel in the synchronization channel group for the first instruction.

[0060] In the synchronization method provided by at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier. An example of the above step S202 may include the following step S2021.

[0061] Step S2021: Allocate the synchronization channel corresponding to the synchronization channel identifier in the synchronization channel group for the first instruction according to the synchronization channel identifier.

[0062] For example, an instruction usually includes information such as an opcode field and an operand field. In the embodiments of the present disclosure, the instruction also includes a synchronization channel identifier. For example, if the synchronization channel group corresponding to the first instruction includes P synchronization channels, the synchronization channel identifier will occupy P-bit encoding bits in the first instruction.

[0063] The width of the GPU instruction set is generally 32 bits, 64 bits, or 128 bits. This fixed width means that the number of bits available for each instruction is limited. Therefore, it is necessary to express the required logic as efficiently as possible within the limited number of bits. That is, the number of bits used for synchronizing channel identifiers in the instruction cannot be increased indefinitely. It is necessary to add more synchronization channels without introducing too many bits.

[0064] For example, in the aforementioned scheme of setting a fixed number of synchronization channels for each warp, a total of only P synchronization channels can be identified using the P-bit encoding bits in the instruction. If the number of synchronization channels needs to be expanded, then for each additional synchronization channel, one more bit needs to be added to the instruction to identify that synchronization channel.

[0065] In the above embodiments of the present disclosure, in one instruction, the instruction type can be determined according to the opcode field, and thus the corresponding synchronization channel group can be determined. And according to the synchronization channel identifier, the corresponding synchronization channel can be determined. Therefore, in the case of also using P-bit encoding bits as the synchronization channel identifier, the synchronization method provided by the embodiments of the present disclosure can provide at most G×P synchronization channels, where G is the number of synchronization channel groups corresponding to the current warp, effectively expanding the number of synchronization channels on the premise of avoiding occupying too many encoding bits in the instruction.

[0066] In the synchronization method provided by at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter. The synchronization counter is used, for example, to count based on the instruction execution situation. For example, different synchronization channels can include different numbers of synchronization counters. The number of synchronization counters can be one or more and can be set according to actual needs. For example, the number of synchronization counters can be determined according to factors such as the size of the workload, the granularity and rate of the data processed by the instruction. The embodiments of the present disclosure do not limit this.

[0067] For a synchronization channel including one synchronization counter, an example of the above step S102 may include the following steps S301 to S303.

[0068] Step S301: In response to issuing the first instruction, increment the count of the synchronization counter.

[0069] Step S302: In response to the completion of the task corresponding to the first instruction, decrement the count of the synchronization counter.

[0070] Step S303: Wait for the synchronization counter to be cleared, and in response to the synchronization counter being cleared, allow the second instruction to start execution.

[0071] For example, in steps S301 to S302, a synchronization counter is used to track how many issued instructions are waiting to be completed. In the initial state, the count value of the synchronization counter can be initialized to 0.

[0072] For example, multiple first instructions can be assigned to the same synchronization channel. Since each synchronization channel includes a synchronization counter in this example, it is equivalent to multiple instructions being assigned to the same synchronization counter. For these first instructions, each time a first instruction is issued, the count value of the synchronization counter is incremented by one, and each time a task corresponding to a first instruction is completed, the count value of the synchronization counter is decremented by one.

[0073] For example, in step S303, assume that the second instruction depends on the execution results of C first instructions (C is a positive integer). After the C first instructions have been issued, the synchronization counter is cleared, indicating that all tasks corresponding to the above C first instructions have been completed, and the second instruction that has a dependency relationship with the above C first instructions can be executed.

[0074] A specific example of the above steps S301 to S303 is given below.

[0075] For example, assume that the first instruction is a load instruction and the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to perform an operation based on 100 items of data returned by 100 load instructions. Then the same synchronization channel can be assigned to the 100 load instructions. Executing the above step S301, each time a load instruction is issued, the count value of the synchronization counter is incremented by one. For the above 100 issued load instructions, executing the above step S302, each time an item of data is loaded, the count value of the synchronization counter is decremented by one. Assume that the second instruction is an arithmetic operation instruction that needs to perform an operation based on the above 100 items of data. Executing the above step S303, wait for the synchronization counter to be cleared. When the synchronization counter is cleared, it indicates that all 100 items of data have been loaded, and then the arithmetic operation instruction can be executed to perform an operation on it, thereby realizing the synchronization of the load instruction and the arithmetic operation instruction.

[0076] Figure 1D It is a flowchart of a synchronization method provided by at least one embodiment of the present disclosure.

[0077] For example, as Figure 1D shown, for a synchronization channel including multiple synchronization counters, another example of the above step S102 may include the following steps S311 to S314.

[0078] Step S311: In response to issuing a first instruction, increment the count of the current synchronization counter.

[0079] Step S312: In response to the count of the current synchronization counter reaching a preset value, jump to the next synchronization counter as the current synchronization counter for subsequent counting.

[0080] Step S313: In response to the task corresponding to the first instruction being completed, decrement the count of the corresponding synchronization counter.

[0081] Step S314: Wait for a preset number of synchronization counters to be cleared or wait for all counted synchronization counters to be cleared, and in response to the clearing, allow the second instruction to start executing.

[0082] For example, in Step S311, the current synchronization counter refers to the synchronization counter currently in the process of counting. In the initial state, the current synchronization counter as the starting point can be any one of the synchronization counters in this synchronization channel and can be selected as needed. The synchronization counter is used to track how many issued instructions are waiting to be completed. In the initial state, the count values of all synchronization counters in the synchronization channel can be initialized to 0.

[0083] For example, multiple first instructions can be assigned to the same synchronization channel. For these first instructions, each time a first instruction is issued, the count value of the current synchronization counter is incremented by one.

[0084] For example, in Step S312, the next synchronization counter refers to the next synchronization counter that will perform the counting operation after the "current synchronization counter" described in Step S311, in a predetermined order (such as the storage order of the synchronization counters in the storage space). For example, the preset value can be, for example, 10, 20, 50, etc., and can be set according to actual needs, and the embodiments of the present disclosure do not limit this. For example, assume that the current synchronization channel includes synchronization counters C0 to C7. If the synchronization counter C0 is currently used for counting and the count of the synchronization counter C0 reaches the preset value, then jump to the next synchronization counter C1 and use the synchronization counter C1 as the current synchronization counter for subsequent counting. When the count of the synchronization counter C1 reaches the preset value, then jump to the next synchronization counter C2 and use the synchronization counter C2 as the current synchronization counter for subsequent counting, and so on until the counting stops.

[0085] For example, in step S312, a write pointer can be maintained, and the write pointer is used to determine which synchronization counter needs to increment its count. For example, when the count of the current synchronization counter reaches a preset value, the warp instruction scheduler can perform an INCREASE operation, and this operation can control the movement of the write pointer. For example, the jump from synchronization counter C0 to the next synchronization counter C1 in the above text can be understood as the write pointer moving from synchronization counter C0 to synchronization counter C1. It should be noted that in the examples of the present disclosure, it is not necessary to start counting from synchronization counter C0, and counting can also start from other synchronization counters. When the count of synchronization counter C7 reaches the preset value, the write pointer will move from synchronization counter C7 to synchronization counter C0, realizing the cyclic use of the synchronization counters.

[0086] For example, in step S313, the operation of decrementing the count of the synchronization counter can be implemented by hardware. When the task corresponding to the first instruction is completed, the count of the synchronization counter corresponding to the first instruction is decremented. The synchronization counter corresponding to the first instruction refers to the synchronization counter whose count is incremented when the first instruction is issued. This means that for the same first instruction, the increment and decrement of the synchronization counter value operate on the same synchronization counter.

[0087] For example, step S314 can be split into the following steps S314A and S314B, corresponding to two different situations respectively.

[0088] Step S314A: Wait for all the counted synchronization counters to be cleared, and in response to the clearing, allow the second instruction to start execution.

[0089] Step S314B: Wait for a preset number of synchronization counters to be cleared, and in response to the clearing, allow the second instruction to start execution.

[0090] For example, in step S314A, it is necessary to wait for all the counted synchronization counters to be cleared before allowing the second instruction to start execution. For example, if synchronization counters C0 to C7 are all involved in counting, it is necessary to wait for all of synchronization counters C0 to C7 to be cleared before allowing the second instruction to start execution. If synchronization counters C3 to C6 are involved in counting, it is necessary to wait for all of synchronization counters C3 to C6 to be cleared before allowing the second instruction to start execution, and so on.

[0091] For example, in step S314A, the warp instruction scheduler can perform a WAIT ALL operation, which maintains a read pointer. The position of the read pointer coincides with the final position of the write pointer. It is necessary to wait for the synchronization counters between the read pointer and the write pointer to be cleared before allowing the second instruction to start execution. This method improves reliability and can ensure that all the counted synchronization counters are cleared.

[0092] For example, in step S314B, it is only necessary to wait for a preset number of synchronization counters to be cleared to allow the second instruction to start execution. The preset number can be set according to actual needs, and the embodiments of the present disclosure do not limit this. For example, assuming that the preset number is 3 and the synchronization counters C0 to C7 are all involved in counting, it is necessary to wait for the synchronization counters C0 to C2 to be cleared before allowing the second instruction to start execution. For another example, assuming that the preset number is 2 and the synchronization counters C3 to C6 are involved in counting, it is necessary to wait for the synchronization counters C3 to C4 to be cleared before allowing the second instruction to start execution, and so on.

[0093] For example, in step S314B, the warp instruction scheduler can perform a WAIT LESSTHAN N operation. This operation maintains a read pointer and sets the read pointer position = the final position of the write pointer - N. It is necessary to wait for the synchronization counters between the read pointer and the write pointer to be cleared before starting to execute the second instruction. The WAIT LESSTHAN N operation provides a relatively flexible way, which can wait for only a part of the counted synchronization counters to be cleared without waiting for all the counted synchronization counters to be cleared. For example, the value of N in the WAIT LESSTHAN N operation can be equal to the number of synchronization counters involved in counting minus the preset number. For example, assuming that there are 5 synchronization counters involved in counting, when N = 0, the preset number is equal to 5, and it is necessary to wait for all 5 counted synchronization counters to be cleared; when N = 1, the preset number is equal to 4, and it is necessary to wait for the first 4 counted synchronization counters to be cleared; when N = 2, the preset number is equal to 3, and it is necessary to wait for the first 3 counted synchronization counters to be cleared, and so on.

[0094] Figure 2 It is an exemplary schematic diagram of a synchronization method provided by at least one embodiment of the present disclosure. Figure 2 A specific example of the above steps S311 to S314A is given.

[0095] Assume that the first instruction is a load instruction, the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to perform operations based on 70 items of data returned by 70 load instructions Ld0 to Ld70. Then the same synchronization channel can be allocated to the 70 load instructions.

[0096] For example, as Figure 2As shown, the synchronization channels allocated for the above 70 load instructions include synchronization counters C0 to C7, and the preset value of the synchronization counter is 20. In this example, the initial position of the write pointer is at synchronization counter C0, that is, the counting starts from synchronization counter C0. For each load instruction issued, the thread bundle instruction scheduler increments the count value of synchronization counter C0 by one until the count value of synchronization counter C0 reaches the preset value of 20. At this time, the thread bundle instruction scheduler performs the INCREASE operation, and the write pointer moves from synchronization counter C0 to synchronization counter C1, and synchronization counter C1 is used as the current synchronization counter for subsequent counting, and so on, until all 70 load instructions are issued. At this time, the write pointer should be at synchronization counter C3. And for the above 70 issued load instructions, for each data load completed, the count value of the synchronization counter corresponding to the load instruction is decremented by one.

[0097] For example, as Figure 2 shown, the thread bundle instruction scheduler performs the WAIT ALL operation, making the read pointer position coincide with the final position of the write pointer (i.e., at synchronization counter C3). To ensure data consistency, it is necessary to wait for all the synchronization counters between the read pointer and the write pointer to be cleared, that is, to wait for synchronization counters C4, C5, C6, C7, C0, C1, C2, C3 to be cleared. When all the above synchronization counters are cleared, it indicates that all 70 items of data have been loaded, and then arithmetic operation instructions can be executed to perform operations on them, thus realizing the synchronization of load instructions and arithmetic operation instructions.

[0098] Figure 3 It is an exemplary schematic diagram of a synchronization method provided by at least one embodiment of the present disclosure. Figure 3 A specific example of the above steps S311 to S314B is given.

[0099] Assume that the first instruction is a load instruction, the second instruction is an arithmetic operation instruction, and the arithmetic operation instruction needs to perform operations based on 70 items of data returned by 70 load instructions Ld0 to Ld70. Then the same synchronization channel can be allocated for the 70 load instructions.

[0100] For example, as Figure 3As shown, the synchronization channels allocated for the above 70 load instructions include synchronization counters C0 to C7, and the preset value of the synchronization counter is 20. In this example, the initial position of the write pointer is at synchronization counter C0, that is, the counting starts from synchronization counter C0. For each issued load instruction, the count value of synchronization counter C0 is incremented by one until the count value of synchronization counter C0 reaches the preset value of 20. At this time, the warp instruction scheduler executes the INCREASE operation, the write pointer moves from synchronization counter C0 to synchronization counter C1, and synchronization counter C1 is used as the current synchronization counter for subsequent counting, and so on, until 70 load instructions are all issued. At this time, the write pointer should be at synchronization counter C3. Moreover, for each of the 70 issued load instructions, once a data loading is completed, the count value of the synchronization counter corresponding to this load instruction is decremented by one.

[0101] For example, as Figure 3 shown, the warp instruction scheduler executes the WAIT LESSTHAN N operation. In this example, N = 2. Set the read pointer position = the final position of the write pointer - N, and wait for the synchronization counters between the read pointer (at synchronization counter C1) and the write pointer to be cleared, that is, wait for synchronization counters C4, C5, C6, C7, C0, and C1 to be all cleared. At this time, it indicates that 40 items of data corresponding to synchronization counters C0 and C1 have been loaded and arithmetic operation instructions can be executed to perform operations on these 40 items of data, and the loading of the remaining 30 items of data is also in progress simultaneously. Compared with the Figure 2 example, this method does not need to wait for both synchronization counters C2 and C3 to be cleared, which means that while processing the computing task, the loading work of the remaining 30 items of data can continue to be organized, thus realizing the pipelining operation of the loading task and the computing task. At the same time, the WAIT LESSTHAN N operation provides a programming method more suitable for loop iteration.

[0102] In the synchronization method provided by at least one of the above embodiments of the present disclosure, by setting multiple synchronization counters in a single synchronization channel, the data loading task and the computing task can be effectively organized in a pipelined form, and sufficient synchronization resources are provided, greatly improving the processing efficiency and resource utilization rate. This method not only optimizes the time matching between the computing task and the data loading task, but also enables a smooth task processing flow to be maintained under high load conditions, thereby enhancing the overall response ability and work efficiency.

[0103] It should be noted that in the embodiments of the present disclosure, the synchronization method may include more or fewer steps, and the execution order of each step is not limited, which can be determined according to actual needs.

[0104] Figure 4Schematic block diagram of a synchronization device provided by at least one embodiment of the present disclosure. For example, the synchronization device provided by at least one embodiment of the present disclosure may be Figure 1A the warp instruction scheduler 12 shown in Figure 1A or embedded in the warp instruction scheduler 12 shown in

[0105] For example, as shown in Figure 4 the synchronization device 400 provided by at least one embodiment of the present disclosure includes a distribution module 401 and a synchronization module 402.

[0106] For example, the distribution module 401 is configured to allocate a synchronization channel for a first instruction for a warp including multiple threads; for the relevant content of the distribution module 401, reference may be made to the relevant description of step S101 in the embodiment of the above synchronization method, which will not be elaborated here.

[0107] For example, the synchronization module 402 is configured to synchronize the first instruction and the second instruction based on the synchronization channel; for the relevant content of the synchronization module 402, reference may be made to the relevant description of step S102 in the embodiment of the above synchronization method, which will not be elaborated here.

[0108] For example, there is a dependency relationship between the first instruction and the second instruction, the warp corresponds to multiple synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

[0109] For example, in at least one embodiment of the present disclosure, the instruction types corresponding to the same synchronization channel group are the same.

[0110] For example, in at least one embodiment of the present disclosure, the distribution module 401 is further configured to: determine the synchronization channel group corresponding to the first instruction based on the type of the first instruction; allocate the synchronization channel in the synchronization channel group for the first instruction.

[0111] For example, in at least one embodiment of the present disclosure, the first instruction includes a synchronization channel identifier, and the distribution module 401 is further configured to: allocate the synchronization channel corresponding to the synchronization channel identifier in the synchronization channel group for the first instruction according to the synchronization channel identifier.

[0112] For example, in at least one embodiment of the present disclosure, each synchronization channel includes at least one synchronization counter, and the synchronization counter is used to count based on the instruction execution situation.

[0113] For example, in at least one embodiment of the present disclosure, for a synchronization channel including a single synchronization counter, the synchronization module 402 is further configured to: increment the count of the synchronization counter in response to issuing a first instruction; decrement the count of the synchronization counter in response to the completion of the task corresponding to the first instruction; wait for the synchronization counter to be cleared, and in response to the synchronization counter being cleared, allow the second instruction to start execution.

[0114] For example, in at least one embodiment of the present disclosure, for a synchronization channel including multiple synchronization counters, the synchronization module 402 is further configured to: increment the count of the current synchronization counter in response to issuing a first instruction; jump to the next synchronization counter as the current synchronization counter for subsequent counting in response to the count of the current synchronization counter reaching a preset value; decrement the count of the corresponding synchronization counter in response to the completion of the task corresponding to the first instruction; wait for a preset number of synchronization counters to be cleared or wait for all the counted synchronization counters to be cleared, and in response to being cleared, allow the second instruction to start execution.

[0115] For example, in at least one embodiment of the present disclosure, the first instruction is a variable-length instruction.

[0116] For example, in at least one embodiment of the present disclosure, the first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction, or a cache operation instruction.

[0117] It should be noted that the above various modules and units can be implemented by software, hardware, firmware, or any combination thereof. For example, the allocation module and the synchronization module can be implemented as an allocation circuit and a synchronization circuit respectively, and the embodiments of the present disclosure do not limit their specific implementation manners.

[0118] It should be understood that the synchronization device 400 provided in at least one embodiment of the present disclosure can be used to implement the foregoing synchronization method, and can also achieve technical effects similar to those of the foregoing synchronization method, which will not be elaborated herein.

[0119] It should be noted that in the embodiments of the present disclosure, the synchronization device 400 may include more or fewer modules or units, and the connection relationships between the various modules or units are not limited and can be determined according to actual needs. The specific composition manners of the various modules or units are not limited and can be composed of analog devices according to circuit principles, or composed of digital chips, or in other applicable manners.

[0120] Figure 5 It is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.

[0121] For example, as Figure 5As shown, the electronic device 500 includes at least one processor 501 and at least one memory 502. The at least one memory 502 includes one or more computer program modules. The one or more computer program modules are stored in the memory 502 and are configured to be executed by the at least one processor 501. The one or more computer program modules include instructions for performing the above synchronization method. When executed by the at least one processor 501, one or more steps of the synchronization method provided in at least one embodiment of the present disclosure can be executed. The memory 502 and the processor 501 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0122] For example, the processor 501 can be a central processing unit (CPU), a digital signal processor (DSP), an image processor (GPU), a general-purpose graphics processing unit (GPGPU), an artificial intelligence (AI) accelerator, or other forms of processing units with data processing capabilities and / or program execution capabilities, such as a field-programmable gate array (FPGA), etc.; for example, the central processing unit (CPU) can be of the X86, ARM, RISC-V architecture, etc. The processor 501 can be a general-purpose processor or a dedicated processor, and can control other components in the electronic device 500 to perform desired functions.

[0123] For example, the memory 502 can include any combination of one or more computer program products. The computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0124] Figure 6 Schematic block diagram of another electronic device provided in at least one embodiment of the present disclosure.

[0125] The electronic device in at least one embodiment of the present disclosure can include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), vehicle terminals (such as in-vehicle navigation terminals), wearable electronic devices, etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The shown electronic device is merely an example and should not impose any limitations on the functions and usage scope of the embodiments of the present disclosure.

[0126] The electronic device includes at least one processor and a memory. The processor herein may be referred to as the processing device 601 described below, and the memory may include at least one of the read-only memory (ROM), random access memory (RAM), and the storage device 608 described below. The memory is used to store programs for executing the methods described in the above various method embodiments; the processor is configured to execute the programs stored in the memory. The processor may be a central processing unit (CPU) or other form of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0127] As Figure 6 shown, the electronic device 600 may include a processing device 601 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to the program stored in the ROM 602 or the program loaded from the storage device 608 into the RAM 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The input / output (I / O) interface is also connected to the bus 604.

[0128] Generally, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a display, a speaker, a vibrator, etc.; a storage device 608 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or wiredly to exchange data. Although Figure 6 the electronic device 600 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices. Instead, more or fewer devices may be implemented or had.

[0129] Specifically, according to at least one embodiment of the present disclosure, the process described above with reference to the flowchart may be implemented as a computer software program. For example, at least one embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program codes for executing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from the network through the communication device 609, or installed from the storage device 608, or installed from the ROM 602. When the computer program is executed by the processing device 601, the above functions defined in the method of at least one embodiment of the present disclosure are executed.

[0130] It should be noted that the computer-readable medium described above can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In at least one embodiment of the present disclosure, the computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In at least one embodiment of the present disclosure, the computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium can also be any computer-readable medium other than the computer-readable storage medium, and the computer-readable signal medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, radio frequency (RF), etc., or any suitable combination of the above.

[0131] The above computer-readable medium can be included in the above electronic device 600; or it can exist separately and not be assembled into the electronic device 600.

[0132] Figure 7 Schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0133] For example, as Figure 7 shown, computer-readable instructions 701 are stored on the non-transitory computer-readable storage medium 700, and when the computer-readable instructions 701 are executed by at least one processor, one or more steps of the above synchronization method are executed.

[0134] For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, and may also be other applicable storage media. For example, the readable storage medium may also be the Figure 5 memory 502 in

[0135] Although the present disclosure has been described in detail with general descriptions and specific embodiments above, based on the embodiments of the present disclosure, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present disclosure fall within the scope of protection required by the present disclosure.

[0136] The following points also need to be noted regarding the present disclosure:

[0137] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0138] (2) For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0139] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0140] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A synchronization method, comprising: For a warp including a plurality of threads, allocating a synchronization channel for a first instruction; Synchronizing the first instruction and the second instruction based on the synchronization channel, There is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to a plurality of synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

2. The synchronization method according to claim 1, wherein: The allocating a synchronization channel for the first instruction includes: Determine a synchronization channel group corresponding to the first instruction based on the type of the first instruction; A synchronization channel in the synchronization channel group is allocated to the first instruction.

3. The synchronization method according to claim 2, wherein: The first instruction includes a synchronization channel identifier, The allocating a synchronization channel in the synchronization channel group to the first instruction includes: According to the synchronization channel identifier, a synchronization channel in the synchronization channel group corresponding to the synchronization channel identifier is allocated to the first instruction.

4. The synchronization method according to claim 1, wherein: Each synchronization channel includes at least one synchronization counter, and the synchronization counter is used to count based on instruction execution status.

5. The synchronization method according to claim 4, wherein: For a synchronous channel that includes a synchronous counter, The synchronizing the first instruction and the second instruction based on the synchronization channel includes: In response to issuing the first instruction, increasing the count of the synchronization counter; In response to completion of the task corresponding to the first instruction, reducing the count of the synchronization counter; Waiting for the synchronization counter to be cleared, and, in response to the synchronization counter being cleared, allowing the second instruction to begin execution.

6. The synchronization method according to claim 4, wherein: For a synchronous channel consisting of multiple synchronous counters, The synchronizing the first instruction and the second instruction based on the synchronization channel includes: In response to issuing the first instruction, increasing the count of the current synchronization counter; In response to the count of the current synchronization counter reaching a preset value, jump to the next synchronization counter as the current synchronization counter for subsequent counting; In response to the task corresponding to the first instruction being completed, reducing the count of the corresponding synchronization counter; Waiting for a preset number of synchronization counters to be cleared or waiting for all counted synchronization counters to be cleared, and, in response to being cleared, allowing the second instruction to start execution.

7. The synchronization method according to claim 1, wherein: The instruction types corresponding to the same synchronous channel group are the same.

8. The synchronization method according to claim 1, wherein: The first instruction is a variable-length instruction.

9. The synchronization method according to claim 1, wherein: The first instruction includes a data transfer instruction, a general matrix multiplication instruction, a transcendental function instruction or a cache operation instruction.

10. The synchronization method according to claim 1, wherein: The synchronization method is executed by a thread warp instruction scheduler.

11. A synchronization device, comprising: An allocation module configured to allocate a synchronization channel to a first instruction for a thread warp including a plurality of threads; a synchronization module, configured to synchronize the first instruction and the second instruction based on the synchronization channel, There is a dependency relationship between the first instruction and the second instruction, the thread warp corresponds to a plurality of synchronization channel groups, each synchronization channel group includes at least one synchronization channel, and different synchronization channel groups correspond to different types of instructions.

12. An electronic device comprising: at least one processor; at least one memory storing one or more computer program modules; The one or more computer program modules are configured to be executed by the at least one processor to execute instructions of the synchronization method according to any one of claims 1-10.

13. A non-transitory computer-readable storage medium having computer-readable instructions stored thereon, wherein: When the computer-readable instructions are executed by at least one processor, the synchronization method according to any one of claims 1 to 10 is performed.

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