Retimer chip firmware loading system, method and device and server

Abstract

The invention provides a retimer chip firmware loading system, method and device and a server, and relates to the technical field of computers. The system comprises a server management chip, a retimer chip and at least two external storage chips, wherein the retimer chip is respectively connected with the processor, the external storage chips and peripheral component interconnect express (PCIe) equipment connected to the processor, and the at least two external storage chips are used for storing firmware corresponding to different PCIe configurations; the server management chip is respectively connected with the PCIe equipment and the external storage chips, and the server management chip is used for setting the address of a target external storage chip matched with the configuration of the PCIe equipment in the at least two external storage chips as the firmware loading address of the retimer chip according to the configuration of the PCIe equipment. The method and the device are used for achieving the effect of reducing the hardware redundancy of the server system.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a retimer chip firmware loading system, method, device, and server. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that can achieve high-speed data transmission between a processor and various functional boards in a server system. As the PCIe signal rate used in servers is getting higher and higher, server models are becoming more and more complex. Especially with the large-scale application of AI (Artificial Intelligence) servers, the PCIe traces are getting longer, resulting in serious signal attenuation during signal transmission and affecting signal transmission efficiency.

[0003] In related technologies, a retimer chip is used to reduce attenuation during signal transmission and improve the signal transmission distance and signal integrity. Among them, the configuration of the retimer chip needs to be the same as that of the PCIe device. Therefore, as the number of PCIe devices increases, in order to meet the different configuration requirements of PCIe devices, the number of retimer chips in the server system also increases accordingly, resulting in a relatively high redundancy in the server system hardware and increasing the system hardware management cost. Summary of the Invention

[0004] Embodiments of this application provide a retimer chip firmware loading system, method, device, and server, so as to achieve the effect of realizing the reuse of retimer chips and reducing the hardware redundancy of the server system.

[0005] In a first aspect, embodiments of this application provide a retimer chip firmware loading system, including: a server management chip, a retimer chip, and at least two external storage chips;

[0006] Among them, the retimer chip is respectively connected to a processor, an external storage chip, and a Peripheral Component Interconnect Express (PCIe) device connected to the processor. At least two external storage chips are used to store firmware corresponding to different PCIe configurations;

[0007] The server management chip is respectively connected to the PCIe device and the external storage chip. The server management chip is used to set the address of the target external storage chip that matches the configuration of the PCIe device among at least two external storage chips as the firmware loading address of the retimer chip according to the configuration of the PCIe device.

[0008] In a possible implementation, the integrated circuit bus I2C pin of the server management chip is connected to the PCIe device, and the general-purpose input / output GPIO pin of the server management chip is connected to the address pin of the external storage chip.

[0009] In a possible implementation, a field-replaceable unit FRU chip is deployed in the PCIe device, and the FRU chip is used to store the device identifier of the PCIe device;

[0010] The server management chip reads the device identifier from the FRU chip and obtains the configuration of the PCIe device according to the device identifier.

[0011] In a possible implementation, the server management chip is further used to set the addresses of other external storage chips to addresses other than the firmware loading address of the retimer chip.

[0012] In a possible implementation, the external storage chip is an electrically erasable programmable read-only memory EEPROM.

[0013] In a second aspect, an embodiment of the present application provides a method for loading the firmware of a retimer chip, which is applied to the retimer chip firmware loading system in the first aspect and / or various possible implementation manners of the first aspect above. The method for loading the firmware of the retimer chip includes:

[0014] Obtain the configuration of a peripheral component interconnect express bus PCIe device connected to the processor of the server;

[0015] According to the configuration, determine a target external storage chip that matches the configuration of the PCIe device among at least two external storage chips included in the retimer chip firmware loading system;

[0016] Set the address of the target external storage chip as the firmware loading address of the retimer chip.

[0017] In a possible implementation, obtaining the configuration of the PCIe device connected to the processor of the server includes:

[0018] Read the device identifier of the PCIe device from the FRU chip deployed in the PCIe device;

[0019] Based on the corresponding relationship between the stored device identifier and the configuration, obtain the configuration of the PCIe device according to the device identifier of the PCIe device.

[0020] In a possible implementation, it further includes:

[0021] Set the addresses of other external storage chips among at least two external storage chips to addresses other than the firmware loading address of the retimer chip.

[0022] In a third aspect, an embodiment of the present application provides a retimer chip firmware loading device, which is applied to the retimer chip firmware loading system in the first aspect and / or various possible implementation manners of the first aspect above. The retimer chip firmware loading device includes:

[0023] An obtaining module, configured to obtain the configuration of a peripheral component interconnect express (PCIe) device connected to the processor of the server;

[0024] A determining module, configured to determine a target external storage chip that matches the configuration of the PCIe device from at least two external storage chips included in the retimer chip firmware loading system according to the configuration;

[0025] A setting module, configured to set the address of the target external storage chip as the firmware loading address of the retimer chip.

[0026] In a fourth aspect, an embodiment of the present application provides a server, including: a processor and the retimer chip firmware loading system in the first aspect and / or various possible implementation manners of the first aspect above.

[0027] The retimer chip firmware loading system, method, device, and server provided by the embodiments of the present application connect one retimer chip to at least two external storage chips, store firmware corresponding to different PCIe configurations in at least two external storage chips, identify the PCIe device by the server management chip and obtain the PCIe configuration of the PCIe device, set the address of the external storage chip according to the PCIe configuration of the PCIe device, and enable the retimer chip to automatically load the firmware corresponding to the PCIe configuration of the PCIe device, realizing the reuse of the retimer chip and achieving the effect of reducing the hardware redundancy of the server system. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application and used together with the specification to explain the principles of the present application.

[0029] Figure 1 It is a schematic diagram of the scenario of retimer chip firmware loading provided by an embodiment of the present application;

[0030] Figure 2 It is a schematic structural diagram of the retimer chip firmware loading system provided by the present application;

[0031] Figure 3 It is a schematic flowchart of the retimer chip firmware loading method provided by the present application;

[0032] Figure 4 It is a schematic structural diagram of the retimer chip firmware loading device provided by the present application;

[0033] Figure 5 The structural schematic diagram of the server provided by the embodiment of the present application.

[0034] Through the above-mentioned drawings, the clear embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and text descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed implementation manners

[0035] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present application. On the contrary, they are merely examples of the devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] First, the nouns involved in the present application are explained:

[0037] Processor: It refers to the central processing unit (CPU) in the server system. It is an important part of the server and is responsible for executing various computing tasks.

[0038] PCIe: It is a high-speed serial computer expansion bus standard. PCIe uses a bidirectional connection method and can perform transceiver operations at the same time. The path between devices is called a link, which consists of one or more receive-transmit pairs. Such a pair of receive and transmit is called a lane. The protocol stipulates that a link can have 1, 2, 4, 8, 12, 16, or 32 lanes, that is, the link bandwidth is usually expressed in the forms of x1, x2, x4, x8, x16, x32, etc.

[0039] PCIe device: It refers to a device in the server system that is connected to the processor through the PCIe bus, such as a graphics card or a network card.

[0040] Retimer chip: The main function of the retimer chip is to recover and re-time high-speed signals to ensure the integrity and accuracy of the signals during transmission.

[0041] Server management chip: It refers to an integrated circuit chip built into the server motherboard. It is a core component of the server hardware and is responsible for processing and managing various computing tasks and data transmissions of the server.

[0042] Firmware: refers to software embedded in hardware devices. It is located between the hardware and application software and is responsible for controlling the basic functions and operating logic of the hardware. Specifically, firmware is a program written into the device memory, which provides the control logic and interface of the hardware so that the hardware can work in a predetermined manner. The difference between firmware and application software lies in their fixedness and low-level nature. Firmware is a program solidified in the hardware and is responsible for the most basic and low-level system functions, while application software can be installed and updated on the user side.

[0043] Figure 1 Schematic diagram of the scenario for loading the retimer chip firmware provided in this application. The processor is connected to the PCIe device through the PCIe bus. In order to avoid signal attenuation caused by too long wiring, the processor first sends the signal to the retimer chip through the PCIe bus. The retimer chip reshapes the signal and sends it to the PCIe device through the PCIe bus. In order to ensure the consistency of the data sent by the processor and the data received by the PCIe device, the PCIe configuration of the processor, the retimer chip and the PCIe device needs to be consistent. The PCIe configuration of the retimer chip is implemented by loading firmware. The firmware contains information related to the PCIe configuration. Usually, the firmware is stored in the memory. When the retimer chip is powered on, the firmware is automatically loaded from the memory to complete the PCIe configuration.

[0044] In related technologies, such as Figure 1 As shown in the figure, when the processor communicates with different PCIe devices, different configurations are often used. For example, PCIe device 1 uses a x16 configuration, and PCIe2 uses a x4x4x4x4 configuration. The retimer chip can only load one firmware to implement one PCIe configuration. In this way, when the processor is connected to PCIe devices with different configurations, different retimer chip paths need to be used, that is, multiple retimer chips need to be set up in the system. These retimer chips are the same in hardware structure, but the loaded firmware is different, such as Figure 1 As shown in , retimer chip 1 loads firmware A, wherein firmware A includes information related to the x16 configuration, and retimer chip 2 loads firmware B, wherein firmware B includes information related to the x4x4x4x4 configuration. As the number of PCIe device configuration types involved in the server system increases, the number of retimer chips also increases accordingly, resulting in redundancy in the server system hardware.

[0045] In summary, the related technology has a technical problem that the server system hardware has a high degree of redundancy, resulting in high system hardware management costs.

[0046] In this regard, the retimer chip firmware loading system, method, device, and server provided by the embodiments of the present application are configured such that a retimer chip is connected to at least two external storage chips. Firmware corresponding to different PCIe configurations is stored in the at least two external storage chips. The server management chip identifies the PCIe device and obtains the PCIe configuration of the PCIe device. According to the PCIe configuration of the PCIe device, the address of the external storage chip is set, enabling the retimer chip to automatically load the firmware corresponding to the PCIe configuration of the PCIe device, achieving the reuse of the retimer chip and reducing the hardware redundancy of the server system.

[0047] The following uses specific embodiments to elaborate in detail on the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems. These several specific embodiments can be combined with each other, and concepts or processes that are the same or similar may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0048] Figure 2 It is a schematic structural diagram of the retimer chip firmware loading system provided by the embodiments of the present application. As Figure 2 shown, the retimer chip firmware loading system 20 includes: a server management chip 201, a retimer chip 202, and at least two external storage chips 203.

[0049] Among them, the retimer chip 202 is respectively connected to the processor, the external storage chip 203, and a peripheral component interconnect express bus (PCIe) device connected to the processor. The at least two external storage chips 203 are used to store firmware corresponding to different PCIe configurations.

[0050] The server management chip 201 is respectively connected to the PCIe device and the external storage chip 203. The server management chip 201 is configured to set the address of the target external storage chip 203 that matches the configuration of the PCIe device among the at least two external storage chips 203 as the firmware loading address of the retimer chip 202 according to the configuration of the PCIe device.

[0051] In Figure 2 the retimer chip firmware loading system 20 shown, the retimer chip 202 is connected to the processor and the PCIe device through the PCIe bus. The processor sends a signal to the retimer chip 202 through the PCIe bus. The retimer chip 202 reshapes and restores the signal and then sends it to the PCIe device through the PCIe bus with the same PCIe configuration, avoiding signal attenuation caused by too long a trace between the processor and the PCIe device.

[0052] During this communication process, the PCIe configurations of the retimer chip 202, the processor, and the PCIe are the same. Among them, the retimer chip 202 performs PCIe configuration in the following manner: After the retimer chip 202 is powered on and reset, it reads the firmware from a preset firmware read address. The firmware read address corresponds to the address where the external memory 203 stores the firmware. The firmware stores information related to PCIe configuration. The retimer chip 202 automatically reads and loads the firmware to achieve PCIe configuration. It should be noted that usually, the firmware read address in the retimer chip 202 is not modifiable, while the address of the external storage chip 203 is modifiable.

[0053] In the retimer chip firmware loading system 20 provided by the embodiments of the present application, at least two external storage chips 203 are connected to one retimer chip 202. Each external storage chip 203 stores firmware corresponding to different PCIe configurations. When it is determined which PCIe configuration the retimer chip 202 needs, as long as the address of the external storage chip 203 storing the corresponding firmware is set as the firmware read address of the retimer chip 202, after the retimer chip 202 is powered on and reset, it will automatically read and load the firmware from this external storage chip 203 to achieve the corresponding PCIe configuration.

[0054] Specifically, configuring the address for the external storage chip 203 is achieved by the server management chip 201. In one implementation, the server management chip 201 locally stores the correspondence between the PCIe device identifier, the PCIe configuration, and the external storage chips. It can determine the PCIe configuration based on the PCIe device identifier of the PCIe device connected to the retimer chip 202, and then determine which external storage chip's address should be set to the same address as the firmware loading address of the retimer chip 202.

[0055] The retimer chip firmware loading system provided by the embodiments of the present application sets at least two external storage chips for storing firmware related to different PCIe configurations, and uses the server management chip to set the address of the external storage chip storing the corresponding firmware as the firmware loading address of the retimer chip according to the PCIe configuration required by the retimer chip, enabling the retimer chip to achieve at least two PCIe configurations, realizing the reuse of the retimer chip, reducing the number of retimer chips used in hardware, reducing the hardware redundancy of the server system, and improving the management efficiency of the server system.

[0056] In a possible implementation, the I2C pin of the server management chip is connected to the PCIe device, and the GPIO pin of the server management chip is connected to the address pin of the external storage chip.

[0057] I2C is a widely used serial communication protocol, which is mainly used for short-distance data transmission between chips. I2C uses two lines for communication, namely the Serial Data Line (SDA) and the Serial Clock Line (SCL). This simple bus structure makes I2C very suitable for efficient interconnection control between microcontrollers and peripherals, or between multiple microcontrollers. Through I2C, simple, efficient, and low-cost communication between the server management chip and PCIe devices can be achieved.

[0058] As an important peripheral interface in the server management chip, GPIO has the characteristics of high flexibility, diverse functions, high speed, rich interrupt functions, diverse electrical characteristics, and wide compatibility. Connecting the GPIO pins of the server management chip to the address pins of the external storage chip enables the server management chip to flexibly and efficiently configure the address of the external storage chip through GPIO.

[0059] The retimer chip firmware loading system provided by the embodiments of this application connects the I2C pins of the server management chip to the PCIe device, which can achieve fast reading of PCIe device information by the server management chip. Connecting the GPIO pins of the server management chip to the address pins of the external storage chip can achieve flexible configuration of the address of the external storage chip by the server management chip. Overall, the information transfer process of the retimer firmware loading system is efficient, flexible, and low-cost.

[0060] In a possible implementation, an FRU chip is deployed in the PCIe device. The FRU chip is used to store the device identifier of the PCIe device. The server management chip reads the device identifier from the FRU chip and obtains the configuration of the PCIe device according to the device identifier.

[0061] An FRU chip with storage function is deployed in the PCIe device. By writing different data into it, different configuration information of the PCIe device is represented. For example, writing "01" to the first register address of the FRU chip represents Configuration 1, indicating that the current configuration of the PCIe device is Configuration 1, and Configuration 1 corresponds to a PCIe configuration. Writing "10" to the first register address of the FRU chip represents Configuration 2. The server management chip reads the data in the FRU chip through the I2C protocol, recognizes "01" as Configuration 1, and recognizes "10" as Configuration 2. Configuration 2 corresponds to a PCIe configuration different from Configuration 1.

[0062] The retimer chip firmware loading system provided by the embodiments of this application deploys a FRU chip with storage function in a PCIe device to distinguish different PCIe devices, so that the server management chip can determine which firmware with PCIe configuration should be loaded for the retimer chip according to the PCIe device connected to the current retimer chip, and then configure the address of the external storage chip, so as to achieve the consistency of the PCIe configuration between the retimer chip and the PCIe device.

[0063] In a possible implementation manner, the server management chip is further configured to set the addresses of other external storage chips to addresses other than the firmware loading address of the retimer chip.

[0064] It can be understood that if the addresses of multiple external storage chips are the firmware loading addresses of the retimer chip, then when the retimer chip automatically loads the firmware from the firmware loading address during power-on, an address conflict will occur, which will cause the firmware loading to fail or load the wrong firmware. Therefore, by setting the external storage chip storing the firmware with a different PCIe configuration from the retimer chip to an address other than the firmware loading address, the smooth progress of firmware loading can be ensured.

[0065] Exemplarily, the firmware loading address of the retimer chip in the retimer chip firmware loading system is address A. Two external storage chips are set in the system. External storage chip 1 stores the firmware related to the PCIe x16 configuration, and external storage chip 2 stores the firmware related to the PCIe 4x4x4x4 configuration. When the server chip determines that the PCIe configuration of the current PCIe device is x16, the address of external storage chip 1 is set to address A, and the address of external storage chip 2 is set to address B, where address B is an address different from address A.

[0066] In another example, the firmware loading address signal of the retimer chip is A2 = high, A1 = high, A0 = high. Two external storage chips are set in the system. External storage chip 1 stores the firmware related to the PCIe x16 configuration, and external storage chip 2 stores the firmware related to the PCIe 4x4x4x4 configuration. When the server chip determines that the PCIe configuration of the current PCIe device is x16, the address signal of external storage chip 1 is set to A2 = high, A1 = high, A0 = high, and the address signal of external storage chip 2 is set to A2 = low, A1 = low, A0 = low. When the server chip determines that the PCIe configuration of the current PCIe device is 4x4x4x4, the address signal of external storage chip 1 is set to A2 = low, A1 = low, A0 = low, and the address signal of external storage chip 2 is set to A2 = high, A1 = high, A0 = high.

[0067] In the firmware loading system of the retimer chip provided by the embodiment of the present application, the server management chip is further configured to set the addresses of other external storage chips to addresses other than the firmware loading address of the retimer chip, avoiding firmware loading conflicts and ensuring the accuracy of firmware loading.

[0068] In a possible implementation manner, the external storage chip is an EEPROM.

[0069] EEPROM has the following characteristics: non-volatile, EEPROM can retain the stored data after power-off, and even if the device is turned off or restarted, the data stored in EEPROM will not be lost; electrically erasable and programmable, EEPROM can modify its content through electronic signals without removing or replacing the chip, which enables EEPROM to self-contain data and is very useful as a storage device in microcontrollers, computer firmware, and other embedded systems; EEPROM allows single-byte modification without erasing the entire chip, which provides greater flexibility than other types of ROM, such as EPROM; EEPROM has a limit on the number of erase / write cycles, usually 100,000 to 1,000,000 times, depending on the specific product and manufacturer; diverse interface types, common interfaces of EEPROM include I2C, SPI, and parallel interfaces, which makes them easy to integrate into various electronic systems.

[0070] In the firmware loading system of the retimer chip provided by the embodiment of the present application, using EEPROM as the external storage chip makes the system simple, flexible, and easy to use.

[0071] In an implementation manner, the external storage chip can be a flash chip.

[0072] The embodiment of the present application provides a method for loading the firmware of a retimer chip, which is applied to the server management chip in the firmware loading system of the retimer chip as described in the above embodiment. Figure 3 It is a schematic flowchart of the firmware loading method for the retimer provided by the embodiment of the present application. As Figure 3 shown, the method for loading the firmware of the retimer chip includes:

[0073] S301. Obtain the configuration of the Peripheral Component Interconnect Express (PCIe) device connected to the processor of the server.

[0074] S302. According to the configuration, determine the target external storage chip that matches the configuration of the PCIe device among at least two external storage chips included in the firmware loading system of the retimer chip.

[0075] Specifically, the server manager chip determines the target external storage chip that matches the configuration of the PCIe device through the correspondence between the configuration stored locally and the external storage chips.

[0076] S303. Set the address of the target external storage chip as the firmware loading address of the retimer chip.

[0077] After the retimer chip is powered on and reset, it reads the firmware from the preset firmware loading address. The firmware stores information related to PCIe configuration. The retimer chip automatically reads and loads the firmware to implement PCIe configuration.

[0078] The retimer chip loading method provided by the embodiments of this application obtains the configuration of the Peripheral Component Interconnect Express (PCIe) device connected to the processor of the server, and sets the address of the external memory corresponding to the configuration according to the configuration. The retimer chip automatically loads the firmware from the external memory, realizing the reuse and automatic configuration of the retimer chip.

[0079] In a possible implementation, obtaining the configuration of the PCIe device connected to the processor of the server includes:

[0080] Read the device identifier of the PCIe device from the FRU chip deployed in the PCIe device; based on the corresponding relationship between the stored device identifier and the configuration, obtain the configuration of the PCIe device according to the device identifier of the PCIe device.

[0081] In the FRU chip with storage function deployed in the PCIe device, the PCIe device configuration information is stored. For example, reading "01" at the first register address of the FRU chip indicates that the current configuration of the PCIe device is Configuration 1, and Configuration 1 corresponds to a PCIe configuration. Reading "10" at the first register address of the FRU chip indicates that the current configuration of the PCIe device is Configuration 2, and Configuration 2 corresponds to a PCIe configuration different from Configuration 1.

[0082] The retimer chip firmware loading method provided by the embodiments of this application reads the device identifier in the FRU chip of the PCIe device to distinguish different PCIe devices and their configurations, enabling the server management chip to determine which PCIe configuration firmware should be loaded for the retimer chip according to the PCIe device connected to the current retimer chip, and then configuring the address of the external storage chip to achieve the consistency of the PCIe configuration between the retimer chip and the PCIe device.

[0083] In a possible implementation, it further includes:

[0084] Set the addresses of other external storage chips among at least two external storage chips as addresses other than the firmware loading address of the retimer chip.

[0085] It can be understood that if the addresses of multiple external storage chips are the firmware loading addresses of the retimer chip, when the retimer chip automatically loads the firmware from the firmware loading address during power-on, an address conflict will occur, which may lead to unsuccessful firmware loading or loading of incorrect firmware. Therefore, by setting the external storage chip storing firmware with a different PCIe configuration from the retimer chip to an address other than the firmware loading address, the smooth progress of firmware loading can be ensured.

[0086] The retimer chip firmware loading method provided by the embodiment of the present application sets the addresses of other external storage chips to addresses other than the firmware loading address of the retimer chip, avoiding firmware loading conflicts and ensuring the accuracy of firmware loading.

[0087] Figure 4 It is a schematic structural diagram of the retimer chip firmware loading device provided by the present application, as Figure 4 shown, the retimer chip firmware loading device 40 provided in this embodiment includes:

[0088] An acquisition module 401, configured to acquire the configuration of a peripheral component interconnect express bus (PCIe) device connected to the processor of the server;

[0089] A determination module 402, configured to determine a target external storage chip that matches the configuration of the PCIe device from at least two external storage chips included in the retimer chip firmware loading system according to the configuration;

[0090] A setting module 403, configured to set the address of the target external storage chip as the firmware loading address of the retimer chip.

[0091] In a possible implementation manner, the acquisition module 401 is specifically configured to:

[0092] Read the device identifier of the PCIe device from the FRU chip deployed in the PCIe device;

[0093] Based on the corresponding relationship between the stored device identifier and the configuration, obtain the configuration of the PCIe device according to the device identifier of the PCIe device.

[0094] In a possible implementation manner, the setting module 403 is further configured to:

[0095] Set the addresses of other external storage chips among the at least two external storage chips to addresses other than the firmware loading address of the retimer chip.

[0096] The retimer chip firmware loading device provided in this embodiment can execute the method provided by the above method embodiment, and its implementation principle and technical effect are similar, which will not be elaborated here in this embodiment.

[0097] Figure 5 The following is a schematic diagram of the server structure provided by the embodiment of the present application. As shown in the figure, the server 50 provided by the embodiment of the present application includes: a processor 501, and a retimer chip firmware loading system 502 in various possible implementation manners as described in the above embodiments.

[0098] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments; and the foregoing storage medium includes: various media that can store program codes such as read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs.

[0099] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily think of other implementation manners of the present invention. The present invention is intended to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include common general knowledge or conventional technical means in the technical field not disclosed in the present invention. It is not limited to the precise structure described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A retimer chip firmware loading system, characterized in that: include: a server management chip, a retimer chip, and at least two external storage chips; wherein the retimer chip is respectively connected to the processor, the external memory chip, and a peripheral component interconnect express bus PCIe device connected to the processor, and the at least two external memory chips are used to store firmware corresponding to different PCIe configurations; The server management chip is connected to the PCIe device and the external storage chip respectively. The server management chip is used to set the address of the target external storage chip among the at least two external storage chips that matches the configuration of the PCIe device as the firmware loading address of the retimer chip according to the configuration of the PCIe device.

2. The retimer chip firmware loading system according to claim 1, characterized in that: The integrated circuit bus I2C pin of the server management chip is connected to the PCIe device, and the general purpose input and output GPIO pin of the server management chip is connected to the address pin of the external storage chip.

3. The retimer chip firmware loading system according to claim 1 or 2, characterized in that: A field replaceable unit FRU chip is deployed in the PCIe device, and the FRU chip is used to store a device identification of the PCIe device; The server management chip reads the device identification from the FRU chip, and obtains the configuration of the PCIe device according to the device identification.

4. The retimer chip firmware loading system according to claim 1 or 2, characterized in that: The server management chip is further used to set the addresses of other external storage chips to addresses other than the firmware loading address of the retimer chip.

5. The retimer chip firmware loading system according to claim 1 or 2, characterized in that: The external storage chip is an electrically erasable programmable read-only memory (EEPROM).

6. A method for loading firmware of a retimer chip, characterized in that: A server management chip applied to a retimer chip firmware loading system according to any one of claims 1 to 5, wherein the retimer chip firmware loading method comprises: Obtaining a configuration of a peripheral component interconnect express bus PCIe device connected to a processor of the server; According to the configuration, determining a target external memory chip that matches the configuration of the PCIe device among at least two external memory chips included in the retimer chip firmware loading system; The address of the target external storage chip is set as the firmware loading address of the retimer chip.

7. The method for loading firmware of a retimer chip according to claim 6, characterized in that: The obtaining of the configuration of the PCIe device connected to the processor of the server includes: Reading a device identification of the PCIe device from a FRU chip deployed in the PCIe device; Based on the stored correspondence between the device identification and the configuration, the configuration of the PCIe device is obtained according to the device identification of the PCIe device.

8. The method for loading firmware of a retimer chip according to claim 6 or 7, characterized in that: Also includes: The addresses of other external memory chips of the at least two external memory chips are set to addresses other than the firmware loading address of the retimer chip.

9. A retimer chip firmware loading device, characterized in that: Applicable to the retimer chip firmware loading system according to any one of claims 1 to 4, the retimer chip firmware loading device comprising: An acquisition module, used to acquire a configuration of a peripheral component interconnect express bus PCIe device connected to a processor of the server; a determination module, configured to determine, according to the configuration, a target external storage chip that matches the configuration of the PCIe device among at least two external storage chips included in the retimer chip firmware loading system; A setting module is used to set the address of the target external storage chip as the firmware loading address of the retimer chip.

10. A server, characterized in that: include: A processor and a retimer chip firmware loading system as claimed in any one of claims 1 to 4.

Images