An output limiting device

Abstract

The application discloses an output limiting device applied to a switching power supply, comprising an error amplifier, an output resistor, an amplifier and a current biasing module; the input end of the error amplifier is connected with the switching power supply, a reference voltage and the current biasing module, and the reference voltage is used for limiting the output voltage of the switching power supply within a preset range; the output end of the error amplifier is connected with the first end of the output resistor; the input end of the amplifier is connected with the reference voltage and the current biasing module; the output end of the amplifier is connected with the second end of the output resistor and the input end of the amplifier; and the current biasing module is connected with the reference voltage. The output limiting voltage of the application is related to the reference voltage and the output resistor. Since the resistors have good matching on the same chip and the accuracy of the reference voltage is high, the limiting voltage is less affected by process fluctuation, more accurate limiting control can be realized, and the influence of the size deviation of the traditional MOS tube on the limiting voltage is avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an output limiting device. Background Technology

[0002] With the rapid development of fields such as artificial intelligence, the Internet of Things, and aerospace, the number of portable smart terminals and communication devices is constantly increasing. All these devices require efficient and lightweight power supplies, making switching power supplies (DC-DC) the mainstream power supply. Highly stable and efficient switching power supply converters are crucial for maintaining the normal operation of devices over extended periods, ensuring their safety. Limiting the output voltage swing of the error amplifier is essential to prevent excessively large output swings, which could lead to decreased switching power supply efficiency, inductor damage, and ultimately, system malfunctions. Therefore, an output swing limiting device is urgently needed to precisely limit the voltage swing.

[0003] However, the traditional output clamping method using diode connection of MOSFETs can lead to deviations in MOSFET dimensions during actual production. This can significantly affect the output limiting process, resulting in low accuracy of the limiting voltage. Summary of the Invention

[0004] In order to overcome the shortcomings of the prior art, the purpose of this invention is to provide an output limiting device whose output limiting voltage is not affected by the size of the MOS transistor, so that the output limiting voltage is less affected by process fluctuations, thereby improving the accuracy of the limiting voltage.

[0005] To solve the above-mentioned technical problems, the present invention is implemented according to the following solution:

[0006] An output limiting device is provided for use in switching power supplies, including an error amplifier, an output resistor, an amplifier, and a current bias module;

[0007] The input terminal of the error amplifier is connected to the switching power supply, the reference voltage, and the current bias module. The reference voltage is used to limit the output voltage of the switching power supply within a preset range. The output terminal of the error amplifier is connected to the first terminal of the output resistor. The input terminal of the amplifier is connected to the reference voltage and the current bias module. The output terminal of the amplifier is connected to the second terminal of the output resistor and the input terminal of the amplifier. The current bias module is connected to the reference voltage.

[0008] Compared with the prior art, the beneficial effects of the output limiting device of the present invention are as follows: by using a limiting device composed of an error amplifier, an output resistor, and an amplifier, the output limiting voltage is related to the reference voltage and the output resistor. Since the resistor has good matching on the same chip and the reference voltage has high accuracy, the limiting voltage is less affected by process fluctuations, and more accurate limiting control can be achieved, avoiding the influence of traditional MOS transistor size deviation on the limiting voltage.

[0009] Optionally, the error amplifier includes an input differential pair module, a current distribution module, and a current mirror module;

[0010] The input differential pair module is connected to the power supply and the current bias module, and the power supply is used to provide operating power; the current distribution module is connected to the switching power supply, the reference voltage, the input differential pair module, and the current mirror module; the current mirror module is connected to the output resistor and the power supply.

[0011] Optionally, the input differential pair module includes a first MOS transistor and a second MOS transistor;

[0012] The power supply is connected to the source of the first MOSFET and the source of the second MOSFET; the drain of the first MOSFET is connected to the current bias module, the gate of the first MOSFET, and the gate of the second MOSFET; the drain of the second MOSFET is connected to the current distribution module.

[0013] Optionally, the current distribution module includes a third MOSFET and a fourth MOSFET;

[0014] The drain of the second MOSFET is connected to the source of the third MOSFET and the source of the fourth MOSFET; the switching power supply is connected to the gate of the third MOSFET; the gate of the fourth MOSFET is connected to the reference voltage; and the current mirror module is connected to the drain of the third MOSFET and the drain of the fourth MOSFET.

[0015] Optionally, the current mirror module includes a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET;

[0016] The drain of the fifth MOS transistor is connected to the drain of the third MOS transistor, the gate of the fifth MOS transistor, and the gate of the eighth MOS transistor; the drain of the sixth MOS transistor is connected to the drain of the fourth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor.

[0017] The drain of the seventh MOS transistor is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor, and the gate of the tenth MOS transistor; the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor and the output resistor.

[0018] The sources of the fifth MOSFET, the sixth MOSFET, the seventh MOSFET, and the eighth MOSFET share a common ground; the power supply is connected to the sources of the ninth MOSFET and the tenth MOSFET.

[0019] Optionally, the amplifier includes an input module and a distribution module;

[0020] The input module is connected to the power supply, the current bias module, and the distribution module; the distribution module is connected to the reference voltage and the output resistor.

[0021] Optionally, the input module includes an eleventh MOSFET and a twelfth MOSFET;

[0022] The power supply is connected to the source of the eleventh MOS transistor and the source of the twelfth MOS transistor; the drain of the eleventh MOS transistor is connected to the current bias module, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor; the drain of the twelfth MOS transistor is connected to the distribution module.

[0023] Optionally, the distribution module includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, and a sixteenth MOSFET;

[0024] The drain of the twelfth MOS transistor is connected to the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor;

[0025] The gate of the thirteenth MOS transistor is connected to the reference voltage; the drain of the thirteenth MOS transistor is connected to the drain of the fifteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor.

[0026] The gate of the fourteenth MOS transistor is connected to the drain of the fourteenth MOS transistor, the drain of the sixteenth MOS transistor, and the output resistor;

[0027] The source of the fifteenth MOS transistor and the source of the sixteenth MOS transistor share a common ground.

[0028] Optionally, the current bias module includes an amplification unit and a current feedback unit;

[0029] The amplification unit is connected to the reference voltage and the current feedback unit; the current feedback unit is connected to the error amplifier and the amplifier.

[0030] Optionally, the current feedback unit includes a seventeenth MOSFET, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, and a reference resistor;

[0031] The amplification unit is connected to the drain of the seventeenth MOS transistor, the gate of the seventeenth MOS transistor, the gate of the eighteenth MOS transistor, and the reference resistor;

[0032] The drain of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor, the gate of the nineteenth MOS transistor, the gate of the twentieth MOS transistor, and the gate of the twenty-first MOS transistor.

[0033] The drain of the twentieth MOS transistor is connected to the error amplifier; the drain of the twenty-first MOS transistor is connected to the amplifier.

[0034] The source of the seventeenth MOS transistor and the source of the eighteenth MOS transistor are grounded; the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor and the reference resistor are grounded. Attached Figure Description

[0035] Figure 1 This is a structural block diagram of the output limiting device of the present invention;

[0036] Figure 2 This is a circuit diagram of the error amplifier of the present invention;

[0037] Figure 3 This is a circuit diagram of the amplifier of the present invention;

[0038] Figure 4 This is a circuit diagram of the current bias module of the present invention.

[0039] The attached diagram shows the following labels: 1. Error amplifier; 101. Input differential pair module; 102. Current distribution module; 103. Current mirror module; 2. Output resistor; 3. Amplifier; 301. Input module; 302. Distribution module; 4. Current bias module; 401. Amplification unit; 402. Current feedback unit. Detailed Implementation

[0040] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0041] In the following description, when referring to the accompanying drawings, unless otherwise indicated, equal numbers in different drawings represent equal or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0042] See Figure 1 As shown, this invention provides an output limiting device applied to a switching power supply, including an error amplifier 1, an output resistor 2, an amplifier 3, and a current bias module 4; the input terminal of the error amplifier 1 is connected to the switching power supply and the reference voltage V. REF The current bias module 4 is connected, specifically by connecting the input terminal of error amplifier 1 to the output terminal of the switching power supply, with a reference voltage V. REF Used to limit the output voltage V of a switching power supply P Within the preset range, that is, for the output voltage V of the switching power supply P Clamping to achieve control over the output voltage V of the switching power supply P The amplitude is limited; the output terminal of the error amplifier 1 is connected to the first terminal of the output resistor 2; the input terminal of the amplifier 3 is connected to the reference voltage and current bias module 4; the output terminal of the amplifier 3 is connected to the second terminal of the output resistor 2 and the input terminal of the amplifier 3; the current bias module 4 is connected to the reference voltage.

[0043] In one embodiment of the present invention, the output terminal of the error amplifier 1 serves as the output terminal of the output limiting device, which is used to output the switching power supply output voltage V. P The clamped limiting voltage V out .

[0044] See Figure 2 As shown, the error amplifier 1 includes an input differential pair module 101, a current distribution module 102, and a current mirror module 103. The input differential pair module 101 is connected to the power supply AVDD and the current bias module 4. The power supply AVDD is used to provide the working power. The current distribution module 102 is connected to the switching power supply, the reference voltage, the input differential pair module 101, and the current mirror module 103. The current mirror module 103 is connected to the output resistor 2 and the power supply AVDD (AVSS is the negative terminal of the power supply, which can be regarded as ground).

[0045] The input differential pair module 101 includes a first MOSFET M1 and a second MOSFET M2; the power supply AVDD is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2; the drain of the first MOSFET M1 is connected to the current bias module 4, the gate of the first MOSFET M1, and the gate of the second MOSFET M2; and the drain of the second MOSFET M2 is connected to the current distribution module 102.

[0046] The current distribution module 102 includes a third MOSFET M3 and a fourth MOSFET M4; the drain of the second MOSFET M2 is connected to the source of the third MOSFET M3 and the source of the fourth MOSFET M4; the switching power supply is connected to the gate of the third MOSFET M3, specifically to the output voltage V of the switching power supply. P The gate of the third MOSFET M3 is connected to the gate of the fourth MOSFET M4; the gate of the fourth MOSFET M4 is connected to the reference voltage V. REF Connections: The current mirror module 103 is connected to the drain of the third MOSFET M3 and the drain of the fourth MOSFET M4.

[0047] The current mirror module 103 includes a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a tenth MOSFET M10; the drain of the fifth MOSFET M5 is connected to the drain of the third MOSFET M3, the gate of the fifth MOSFET M5, and the gate of the eighth MOSFET M8; the drain of the sixth MOSFET M6 is connected to the drain of the fourth MOSFET M4, the gate of the sixth MOSFET M6, and the gate of the seventh MOSFET M7.

[0048] The drain of the seventh MOSFET M7 is connected to the drain of the ninth MOSFET M9, the gate of the ninth MOSFET M9, and the gate of the tenth MOSFET M10; the drain of the eighth MOSFET M8 is connected to the drain of the tenth MOSFET M10 and the output resistor 2.

[0049] The sources of the fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, and the eighth MOSFET M8 share a common ground (connected to the negative terminal AVSS of the power supply); the power supply AVDD is connected to the source of the ninth MOSFET M9 and the source of the tenth MOSFET M10.

[0050] Reference voltage V REF The output voltage V is a fixed value that does not change. When the output limiting device is operating in a stable state, its output voltage is... P Equal to the reference voltage V REF The current of the second MOSFET M2 is evenly distributed to the third MOSFET M3 and the fourth MOSFET M4.

[0051] Assuming the current output of current bias module 4 is 2*I, that is, the current flowing through the first MOSFET M1 is 2*I, and the second MOSFET M2 mirrors the first MOSFET M1 with a mirror ratio of 1, that is, the current flowing through the second MOSFET M2 is equal to the current flowing through the first MOSFET M1. Therefore, the current flowing through the second MOSFET M2 is also 2*I. Since the current of the second MOSFET M2 is evenly distributed to the third MOSFET M3 and the fourth MOSFET M4, the current flowing through the third MOSFET M3 is I, and the current flowing through the fourth MOSFET M4 is I.

[0052] The fifth MOSFET M5 and the sixth MOSFET M6 are connected in series with the third MOSFET M3 and the fourth MOSFET M4, respectively. Therefore, the current flowing through the third MOSFET M3 and the current flowing through the fourth MOSFET M4 are also I.

[0053] The seventh MOSFET M7 is mirrored by the sixth MOSFET M6, with a mirror ratio of 1, meaning the current flowing through the seventh MOSFET M7 is equal to the current flowing through the sixth MOSFET M6. The eighth MOSFET M8 is mirrored by the fifth MOSFET M5, with a mirror ratio of 1, meaning the current flowing through the eighth MOSFET M8 is equal to the current flowing through the fifth MOSFET M5. Therefore, the current flowing through the seventh MOSFET M7 and the current flowing through the eighth MOSFET M8 are also I.

[0054] The ninth MOSFET M9 is connected in series with the seventh MOSFET M7, so the current flowing through the ninth MOSFET M9 is also I; the tenth MOSFET M10 is mirrored with the ninth MOSFET M9, and the mirror ratio is 1, that is, the current flowing through the tenth MOSFET M10 is equal to the current flowing through the ninth MOSFET M9, so the current flowing through the tenth MOSFET M10 is also I.

[0055] At this moment, the current flowing through the tenth MOSFET M10 is equal to the current flowing through the eighth MOSFET M8, therefore no current flows through output resistor 2. Furthermore, because the negative input terminal of amplifier 3 is connected to its output terminal, and its positive input terminal is connected to the reference voltage V... REF The connection is such that amplifier 3 forms negative feedback. Based on the principle of virtual short terminals, the output terminal A1_OUT of amplifier 3 can be obtained as a function of the reference voltage V. REF The output voltage V of error amplifier 1 is equal at this time. OUT For V REF That is, at this time, the limiting voltage output by the output limiting device is equal to the reference voltage V. REF They are equal, that is, the limiting voltage is V at this time. REF .

[0056] When the output voltage V of the switching power supply PWhen the current increases, the current flowing through the third MOSFET M3 will decrease. The maximum current change of the third MOSFET M3 is ΔI, and the reduced current will all flow to the fourth MOSFET M4. When the limit is reached, that is, when the current flowing through the third MOSFET M3 is 0, the entire current 2*I of the second MOSFET M2 will flow through the fourth MOSFET M4.

[0057] The fifth MOSFET M5 is connected in series with the third MOSFET M3, so the current flowing through the fifth MOSFET M5 is 0; the sixth MOSFET M6 is connected in series with the fourth MOSFET M4, so the current flowing through the sixth MOSFET M6 is 2*I.

[0058] The eighth MOSFET M8 is mirrored by the fifth MOSFET M5, with a mirror ratio of 1. This means that the current flowing through the eighth MOSFET M8 is equal to the current flowing through the fifth MOSFET M5, so the current flowing through the eighth MOSFET M8 is also 0. The seventh MOSFET M7 is mirrored by the sixth MOSFET M6, with a mirror ratio of 1. This means that the current flowing through the seventh MOSFET M7 is equal to the current flowing through the sixth MOSFET M6, so the current flowing through the seventh MOSFET M7 is 2*I.

[0059] The seventh MOSFET M7 is connected in series with the ninth MOSFET M9, so the current flowing through the ninth MOSFET M9 is also 2*I; the tenth MOSFET M10 is mirrored with the ninth MOSFET M9, and the mirror ratio is 1, that is, the current flowing through the tenth MOSFET M10 is equal to the current flowing through the ninth MOSFET M9, so the current flowing through the tenth MOSFET M10 is 2*I.

[0060] At this time, the current flowing through the eighth MOSFET M8 is 0, and the current flowing through the tenth MOSFET M10 is 2*I. Therefore, the current flowing through output resistor 2 is 2*I. Assume the resistance of output resistor 2 is... Then the voltage flowing through output resistor 2 is That is, at this time the output voltage V of error amplifier 1 OUT for That is, the expression for the limiting voltage output by the output limiting device at this time is:

[0061]

[0062] in, For limiting voltage, As the reference voltage, This is the output current of current bias module 4. This is the resistance value of output resistor 2.

[0063] When the output voltage V of the switching power supply PWhen the current decreases, the current flowing through the third MOSFET M3 will increase. The maximum current change of the third MOSFET M3 is ΔI, and the increased current is diverted from the fourth MOSFET M4. When the limit is reached, that is, when the current flowing through the fourth MOSFET M4 is 0, the entire current 2*I of the second MOSFET M2 will flow through the third MOSFET M3.

[0064] The fifth MOSFET M5 is connected in series with the third MOSFET M3, so the current flowing through the fifth MOSFET M5 is 2*I; the sixth MOSFET M6 is connected in series with the fourth MOSFET M4, so the current flowing through the sixth MOSFET M6 is 0.

[0065] The eighth MOSFET M8 is mirrored by the fifth MOSFET M5, with a mirror ratio of 1. This means that the current flowing through the eighth MOSFET M8 is equal to the current flowing through the fifth MOSFET M5, so the current flowing through the eighth MOSFET M8 is also 2*I. The seventh MOSFET M7 is mirrored by the sixth MOSFET M6, with a mirror ratio of 1. This means that the current flowing through the seventh MOSFET M7 is equal to the current flowing through the sixth MOSFET M6, so the current flowing through the seventh MOSFET M7 is 0.

[0066] The seventh MOSFET M7 is connected in series with the ninth MOSFET M9, so the current flowing through the ninth MOSFET M9 is also 0; the tenth MOSFET M10 is mirrored with the ninth MOSFET M9, and the mirror ratio is 1, that is, the current flowing through the tenth MOSFET M10 is equal to the current flowing through the ninth MOSFET M9, so the current flowing through the tenth MOSFET M10 is 0.

[0067] At this time, the current flowing through the eighth MOSFET M8 is 2*I, and the current flowing through the tenth MOSFET M10 is 0. Therefore, the current flowing through output resistor 2 is -2*I. Assume the resistance of output resistor 2 is... Then the voltage flowing through output resistor 2 is That is, at this time the output voltage V of error amplifier 1 OUT for That is, the expression for the limiting voltage output by the output limiting device at this time is:

[0068]

[0069] in, For limiting voltage, As the reference voltage, This is the output current of current bias module 4. This is the resistance value of output resistor 2.

[0070] As can be seen from the above analysis, when the output current of the current bias module 4 remains constant, the maximum value of the limiting voltage output by the output limiting device is: The minimum value is Therefore, it can be seen that the limiting voltage is only related to the reference voltage and the output resistance 2, and is not related to the process parameters of the MOSFET.

[0071] See Figure 3 As shown, amplifier 3 includes an input module 301 and a distribution module 302; the input module 301 is connected to the power supply AVDD (AVSS is the negative terminal of the power supply, which can be considered as ground), the current bias module 4, and the distribution module 302; the distribution module 302 is connected to the reference voltage V. REF Connect the output resistor 2.

[0072] The input module 301 includes an eleventh MOSFET M11 and a twelfth MOSFET M12; the power supply AVDD is connected to the source of the eleventh MOSFET M11 and the source of the twelfth MOSFET M12; the drain of the eleventh MOSFET M11 is connected to the current bias module 4, the gate of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12; and the drain of the twelfth MOSFET M12 is connected to the distribution module 302.

[0073] Distribution module 302 includes a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, and a sixteenth MOSFET M16; the drain of the twelfth MOSFET M12 is connected to the source of the thirteenth MOSFET M13 and the source of the fourteenth MOSFET M14; the gate of the thirteenth MOSFET M13 is connected to the reference voltage V. REF Connections: The drain of the thirteenth MOSFET M13 is connected to the drain of the fifteenth MOSFET M15, the gate of the fifteenth MOSFET M15, and the gate of the sixteenth MOSFET M16; the gate of the fourteenth MOSFET M14 is connected to the drain of the fourteenth MOSFET M14, the drain of the sixteenth MOSFET M16, and the output resistor 2; the source of the fifteenth MOSFET M15 and the source of the sixteenth MOSFET M16 share a common ground (connected to the negative terminal AVSS of the power supply).

[0074] See Figure 4 As shown, the current bias module 4 includes an amplification unit 401 and a current feedback unit 402; the amplification unit 401 is connected to the reference voltage V. REF The current feedback unit 402 is connected; the current feedback unit 402 is connected to the error amplifier 1 and the amplifier 3.

[0075] The current feedback unit 402 includes the seventeenth MOSFET M17, the eighteenth MOSFET M18, the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, and a reference resistor R. bias Amplification unit 401 and the drain of the seventeenth MOSFET M17, the gate of the seventeenth MOSFET M17, the gate of the eighteenth MOSFET M18, and the reference resistor R. biasConnections: The drain of the eighteenth MOSFET M18 is connected to the drain and gate of the nineteenth MOSFET M19, the gate of the twentieth MOSFET M20, and the gate of the twenty-first MOSFET M21; the drain of the twentieth MOSFET M20 is connected to error amplifier 1; the drain of the twenty-first MOSFET M21 is connected to amplifier 3; the source of the seventeenth MOSFET M17 and the source of the eighteenth MOSFET M18 are grounded; the nineteenth MOSFET M19, the twentieth MOSFET M20, the twenty-first MOSFET M21, and the reference resistor R are connected. bias Common land.

[0076] Amplification unit 401 is specifically amplifier 3. Assuming the current EA_IBP output to error amplifier 1 and the current A1_IBP output to amplifier 3 are both I, since the positive input terminal of amplification unit 401 is connected to its output terminal and its negative input terminal is connected to the reference voltage, negative feedback is formed. Based on the principle of negative feedback, the expression for the current I output from current bias module 4 to error amplifier 1 and amplifier 3 can be obtained as V. REF / R bias Substituting the expression for current I into the expression for limiting voltage, we can obtain the maximum value of limiting voltage:

[0077]

[0078] in, This is the maximum value of the limiting voltage. As the reference voltage, The value of output resistor 2. The value of the reference resistor.

[0079] The minimum value of the limiting voltage is:

[0080]

[0081] in, This is the maximum value of the limiting voltage. As the reference voltage, The value of output resistor 2. The value of the reference resistor.

[0082] Therefore, the limiting voltage and the reference voltage are... The resistance value of output resistor 2 The resistance value of the reference resistor Regarding, reference voltage It can be done very accurately, the resistance value of output resistor 2 and the resistance value of the reference resistor The ratio exists, and the resistance value of output resistor 2 can be displayed on the layout. and the resistance value of the reference resistor The ratio between them is very accurate, so the output limiting device proposed in this invention can accurately limit the output voltage of the switching power supply.

[0083] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An output limiting device, applied to a switching power supply, characterized in that, Includes an error amplifier, output resistor, amplifier, and current bias module; The input terminal of the error amplifier is connected to the switching power supply, the reference voltage, and the current bias module. The reference voltage is used to limit the output voltage of the switching power supply within a preset range. The output terminal of the error amplifier is connected to the first terminal of the output resistor. The input terminal of the amplifier is connected to the reference voltage and the current bias module. The output terminal of the amplifier is connected to the second terminal of the output resistor and the input terminal of the amplifier. The current biasing module is connected to the reference voltage; The error amplifier includes an input differential pair module, a current distribution module, and a current mirror module; The input differential pair module is connected to the power supply and the current bias module, and the power supply is used to provide operating power; the current distribution module is connected to the switching power supply, the reference voltage, the input differential pair module, and the current mirror module; the current mirror module is connected to the output resistor and the power supply. The amplifier includes an input module and a distribution module; the input module is connected to the power supply, the current bias module, and the distribution module. The distribution module is connected to the reference voltage and the output resistor; The current bias module includes an amplification unit and a current feedback unit; the amplification unit is connected to the reference voltage and the current feedback unit; the current feedback unit is connected to the error amplifier and the amplifier.

2. The output limiting device according to claim 1, characterized in that, The input differential pair module includes a first MOS transistor and a second MOS transistor; The power supply is connected to the source of the first MOSFET and the source of the second MOSFET; the drain of the first MOSFET is connected to the current bias module, the gate of the first MOSFET, and the gate of the second MOSFET; the drain of the second MOSFET is connected to the current distribution module.

3. The output limiting device according to claim 2, characterized in that, The current distribution module includes a third MOSFET and a fourth MOSFET; The drain of the second MOSFET is connected to the source of the third MOSFET and the source of the fourth MOSFET; the switching power supply is connected to the gate of the third MOSFET; the gate of the fourth MOSFET is connected to the reference voltage; and the current mirror module is connected to the drain of the third MOSFET and the drain of the fourth MOSFET.

4. The output limiting device according to claim 3, characterized in that, The current mirror module includes a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, and a tenth MOSFET; The drain of the fifth MOS transistor is connected to the drain of the third MOS transistor, the gate of the fifth MOS transistor, and the gate of the eighth MOS transistor; the drain of the sixth MOS transistor is connected to the drain of the fourth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor. The drain of the seventh MOS transistor is connected to the drain of the ninth MOS transistor, the gate of the ninth MOS transistor, and the gate of the tenth MOS transistor; the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor and the output resistor. The sources of the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor share a common ground. The power supply is connected to the source of the ninth MOS transistor and the source of the tenth MOS transistor.

5. The output limiting device according to claim 1, characterized in that, The input module includes an eleventh MOSFET and a twelfth MOSFET; The power supply is connected to the source of the eleventh MOS transistor and the source of the twelfth MOS transistor; the drain of the eleventh MOS transistor is connected to the current bias module, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor; the drain of the twelfth MOS transistor is connected to the distribution module.

6. The output limiting device according to claim 5, characterized in that, The distribution module includes a thirteenth MOSFET, a fourteenth MOSFET, a fifteenth MOSFET, and a sixteenth MOSFET; The drain of the twelfth MOS transistor is connected to the source of the thirteenth MOS transistor and the source of the fourteenth MOS transistor; The gate of the thirteenth MOS transistor is connected to the reference voltage; the drain of the thirteenth MOS transistor is connected to the drain of the fifteenth MOS transistor, the gate of the fifteenth MOS transistor, and the gate of the sixteenth MOS transistor. The gate of the fourteenth MOS transistor is connected to the drain of the fourteenth MOS transistor, the drain of the sixteenth MOS transistor, and the output resistor; The source of the fifteenth MOS transistor and the source of the sixteenth MOS transistor share a common ground.

7. The output limiting device according to claim 1, characterized in that, The current feedback unit includes a seventeenth MOSFET, an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, and a reference resistor; The amplification unit is connected to the drain of the seventeenth MOS transistor, the gate of the seventeenth MOS transistor, the gate of the eighteenth MOS transistor, and the reference resistor; The drain of the eighteenth MOS transistor is connected to the drain of the nineteenth MOS transistor, the gate of the nineteenth MOS transistor, the gate of the twentieth MOS transistor, and the gate of the twenty-first MOS transistor. The drain of the twentieth MOS transistor is connected to the error amplifier; the drain of the twenty-first MOS transistor is connected to the amplifier. The source of the seventeenth MOS transistor and the source of the eighteenth MOS transistor are grounded; the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor and the reference resistor are grounded.

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