Incremental ADC (Analog to Digital Converter) for weak current detection

Abstract

The invention relates to the field of integrated circuit design, in particular to an incremental ADC (Analog to Digital Converter) for weak current detection, which comprises a resettable Sigma-Delta modulator, a resettable accumulator and a control clock, wherein the resettable Sigma-Delta modulator comprises an extremely low frequency low distortion filter, a quantizer and a current feedback DAC (Digital-to-Analog Converter); the extremely-low-frequency low-distortion filter is composed of a first-stage low-pass filter, a second-stage integrator, a first reset switch and a second reset switch. The resettable accumulator has a reset function and is used for accumulating output results of the quantizer; the control clock comprises a reset signal rst and a clock signal CLK; according to the invention, an extremely-low-frequency low-distortion filter structure is used in the resettable Sigma-Delta modulator, so that the problem of performance bottleneck caused by introduction of a pseudo resistor in sub-picoampere-level weak current detection of a traditional second-order incremental ADC is solved, and the dynamic range, the anti-noise capability and the linearity of a system are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and particularly to an incremental ADC for weak current detection. Background Art

[0002] Weak current detection technology plays a crucial role in modern technology and is widely used in fields such as biosensing, electrochemical analysis, and high-sensitivity molecular sensing. In weak current detection applications, the analog-to-digital converter (ADC), as a key component in the sensor system, is responsible for converting the analog electrical signal output by the sensor into a digital signal for precise processing by the backend digital system. The incremental ADC (Incremental ADC) has become the preferred solution for weak current detection due to its low output noise, high linearity, low power consumption, and support for multiplexing in multi-sensor systems. The incremental ADC samples and integrates the input signal within a fixed period and converts it into a digital code. The output digital code depends only on the analog input within this period and is independent of the analog input outside the period. The first-order incremental ADC requires 2 N quantization cycle numbers to achieve the quantization accuracy of N Bit. Figure 1 FIG. 12 is a schematic structural diagram of a first-order incremental ADC, including a resetable Sigma-Delta modulator 100 and a resetable accumulator 102. The resetable Sigma-Delta modulator consists of a filter, a comparator, a DAC, and a reset switch. The resetable Sigma-Delta modulator uses noise shaping technology to shift the quantization noise to the high-frequency region, reducing the noise interference in the low-frequency signal bandwidth. The resetable accumulator is used to accumulate the output results of the comparator in the resetable Sigma-Delta modulator. The reset operations of the Sigma-Delta modulator and the accumulator are controlled by the reset signal Reset and are reset at the beginning of each conversion cycle.

[0003] Based on the first-order incremental ADC, the second-order incremental ADC achieves better noise shaping and error correction by adding a second-stage integrator in the filter, significantly improving the measurement accuracy and dynamic range. There are different types of Sigma-Delta modulators in the second-order incremental ADC, which have an important impact on the performance and application scenarios of the second-order incremental ADC. Sigma-Delta modulators can be divided into continuous-time Sigma-Delta modulators (CTSD) and discrete-time Sigma-Delta modulators (DTSD). CTSD does not require a pre-anti-aliasing filter, simplifies the system design, and has lower power consumption, making it more suitable for battery-powered portable devices or medical detection scenarios. Based on the different types of the above Sigma-Delta modulators, the second-order incremental ADC can be correspondingly divided into second-order continuous-time incremental ADC and second-order discrete-time incremental ADC. Figure 2 Figure Figure 2 is a schematic diagram of the structure of a second-order continuous-time incremental ADC, which consists of a resetable second-order Sigma-Delta modulator 110 and a resetable accumulator 112. Among them, the resetable second-order Sigma-Delta modulator includes a filter composed of two-stage integrators, a quantizer, a DAC, a feedforward path, and a reset switch. At the beginning of a cycle, the reset switch is closed to reset the two-stage integrator and the accumulator; the first-stage integrator integrates the input signal, and the second-stage integrator further integrates the output signal of the first integrator, enhancing the noise shaping effect; the feedforward path directly sends the output of the first-stage integrator to the quantizer, which can effectively suppress the influence of low-frequency noise, reduce signal distortion, and achieve noise shaping by pushing the noise to the high-frequency band; the quantizer converts the output of the second-stage integrator into a digital signal; the DAC converts the output of the quantizer into an analog signal and feeds it back to the input end of the filter; the resetable accumulator accumulates the output results of the quantizer. This structure gives the second-order continuous-time incremental ADC unique advantages in weak current detection, and its enhanced noise shaping and error correction capabilities can effectively suppress detection noise and improve measurement accuracy. At the same time, the continuous-time characteristic enables the second-order continuous-time incremental ADC not to require a pre-anti-aliasing filter, which not only simplifies the system hardware design, reduces power consumption, but also avoids the additional noise introduced by the filter.

[0004] Although second-order continuous-time incremental ADCs have many advantages in weak current detection, they still face a series of performance limitations when detecting sub-picoampere (sub-pA) level weak currents. Since the amplitude of sub-pA level weak current signals is extremely small, the quantizer requires sufficient voltage changes for effective detection. Therefore, high-value feedback resistors (GΩ level) or extremely small capacitors (fF level) need to be used for signal amplification. In addition, weak current detection usually requires strict power consumption control, so the clock frequency must be reduced to achieve the low-power design goal. The reduction of the clock frequency leads to an increase in the time required for the integrator to complete integration, thus requiring a larger time constant. Since the time constant is proportional to the RC product, high-value resistors are needed to obtain a larger time constant. However, in actual chip design, high-value resistors occupy a large chip area, thus limiting the system integration and performance optimization. To solve this problem, in the case of sub-pA level weak currents, a pseudo-resistor replacement scheme based on MOS transistors is often adopted. By biasing the MOS transistor in the weak inversion region, an equivalent impedance of GΩ level can be easily achieved, saving more than 90% of the area compared with traditional polysilicon resistors.

[0005] In the scenario of using a second-order incremental ADC for weak current detection, the use of a pseudo-resistor based on MOS transistors effectively solves problems such as the large area occupied by high-value resistors, but its non-linear characteristics pose significant challenges to system performance. Figure 3 Shows the structure of the filter in a second-order incremental ADC's resettable Sigma-Delta modulator, where pseudo-resistors R1 and R2 are used to replace high-value resistors, which can meet the requirements of sub-pA level weak current detection. However, the non-linearity of pseudo-resistors R1 and R2 is difficult to cancel out and will affect the entire system. Specifically, assuming the output voltage of the integrator is Vout1, due to the virtual short characteristic (V+ = V-) of the operational amplifier, the voltage difference across pseudo-resistor R1 is Vout1. Similarly, assuming the output voltage of the low-pass filter is Vout2, then the voltage difference across pseudo-resistor R2 is Vout2. The output of the entire filter is Vout(s), and the expression is as follows:

[0006]

[0007] where Iin(s) is the current signal to be measured, and s is the complex frequency in the Laplace transform.

[0008] Since the resistance values of the pseudo-resistors R1 and R2 exhibit a non-linear relationship with the voltage difference across them, and the voltage differences across the pseudo-resistors R1 and R2 are different, their non-linearities are inconsistent. As a result, the value of R1 / R2 in the denominator of the formula will change, deviating from the design expectation, which in turn affects the noise shaping effect of the filter and directly weakens the noise suppression ability of the system, having a negative impact on the detection accuracy of weak currents. In addition, the linear operating range of the pseudo-resistor composed of a single MOS transistor is narrow, being approximately linear only when the voltage difference across it is ±70 mV. Beyond this range, the non-linearity deteriorates sharply. Due to the limitation of the linear operating range of the pseudo-resistor R2, the output swing of the low-pass filter is restricted, which not only affects the dynamic range of the subsequent multi-bit quantizer but also has a negative impact on the noise performance of the entire system. Summary of the Invention

[0009] The purpose of the present invention is to provide an incremental ADC for weak current detection to solve the problems raised in the above-mentioned background technology.

[0010] To solve the above technical problems, the present invention provides the following technical solutions:

[0011] An incremental ADC for weak current detection includes a resetable Sigma-Delta modulator, a resetable accumulator, and a control clock. The resetable Sigma-Delta modulator includes an extremely low-frequency low-distortion filter, a quantizer, and a current feedback DAC.

[0012] A further improvement of the present invention is that the filter structure of the traditional second-order resetable Sigma-Delta modulator usually consists of a first-stage integrator and a second-stage low-pass filter. By adjusting the structure and order of the two-stage integration in the filter, the first stage is changed to a low-pass filter, and the second stage is changed to an integrator, thereby forming an extremely low-frequency low-distortion filter structure, as specifically shown in Figure 4 shown.

[0013] This adjustment effectively weakens the influence of the pseudo-resistor non-linearity on weak current detection. Specifically, in the traditional filter structure, since the voltages across the two pseudo-resistors are quite different, their non-linearities are inconsistent and difficult to be effectively canceled, which will affect the performance of the entire system. However, in the adjusted filter structure, the feedback resistor of the first-stage low-pass filter and the input resistor between the first-stage low-pass filter and the second-stage integrator both use non-linear pseudo-resistors. Due to the virtual short characteristic of the operational amplifier, the voltage differences across these two pseudo-resistors are the same, both being the output voltage V1 of the first-stage low-pass filter. The output of the entire filter is Vout2(s), and the expression is

[0014]

[0015] Wherein, I in s is the current signal to be measured, and s is the complex frequency in the Laplace transform.

[0016] The voltage differences across the pseudo-resistors R1 and R2 are the same, so their non-linearity is consistent. Then, the ratio R2 / R1 in the denominator of the formula V out2 s will not change. At the same time, adjusting the structure and order of the two-stage integration in the filter does not change the output function of the filter and does not affect the noise shaping effect.

[0017] A further improvement of the present invention is that: by adjusting the structure and order of the two-stage integration in the filter, the output swing of the second-stage integrator in the filter is no longer restricted by the linear working range of the pseudo-resistor. The output swing of the second-stage integrator can be increased by reducing the feedback capacitance of the second-stage integrator, thereby solving the problem of insufficient output voltage swing of the filter in the original structure.

[0018] A further improvement of the present invention is that: the resettable Sigma-Delta modulator uses a second-order continuous-time Sigma-Delta modulator structure. In the resettable Sigma-Delta modulator, the ultra-low-frequency low-distortion filter includes a first-stage low-pass filter, a second-stage integrator, a first reset switch, and a second reset switch. The first-stage low-pass filter is respectively connected to the input end of the second-stage integrator and the output end of the current feedback DAC; wherein, the feedback path of the first-stage low-pass filter is composed of a parallel connection of a feedback capacitor C1, a pseudo-resistor R1, and a first reset switch S1. The pseudo-resistor R1 based on MOS transistors is used to replace the traditional feedback resistor, solving the problem that high-value resistors occupy a large chip area and affect the integration degree. The first-stage low-pass filter sums the input weak current signal and the feedback current signal output by the current feedback DAC, and then integrates and amplifies the summed analog signal. The first reset switch is used to perform a reset operation on the first-stage low-pass filter and is controlled by the reset signal rst.

[0019] A further improvement of the present invention is that: the output end of the second-stage integrator is connected to the input end of the quantizer. The second-stage integrator adopts an RC integrator structure. The pseudo-resistor R2 based on MOS transistors is used to replace the traditional resistor. The feedback path is composed of a parallel connection of a capacitor C2 and a second reset switch S2, and is used to integrate the analog signal output by the first-stage integrator and input the output signal into the quantizer. The second reset switch is used to perform a reset operation on the second-stage integrator and is controlled by the reset signal rst.

[0020] The quantizer is used to compare the analog signal output by the second-stage integrator and convert the comparison result into a digital signal. The quantizer adopts a SAR quantization structure, which consists of a binary-weighted capacitor array and a comparator. At the beginning of the quantization process, the capacitor array is pre-charged to the reference voltage. When the input analog signal arrives, the input signal is compared with the voltage on the capacitor array through the comparator. According to the comparison result, the capacitors in the capacitor array are switched according to the binary search algorithm to re-distribute the initial charge on the capacitors. Compared with other quantization structures, the power consumption is significantly reduced.

[0021] The current feedback DAC converts the digital signal output by the quantizer back into a current signal and feeds the current signal back to the first-stage low-pass filter. Through feedback, the modulator can continuously adjust the quantization error and push it to the high-frequency region.

[0022] The resettable accumulator has a reset function, which is controlled by the reset clock signal rst and is used to accumulate the output results of the quantizer.

[0023] The control clock includes the reset signal rst and the clock signal CLK; the reset signal rst is used to control the first reset switch, the second reset switch, and the accumulator reset; the clock signal CLK is used to control the quantizer and the resettable accumulator. The frequency of the clock signal CLK is M times the frequency of the reset signal rst.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0025] By adjusting the structure and order of the filters in the resettable Sigma-Delta modulator, the present invention uses the form of a pseudo-resistor in parallel with a feedback capacitor in the first-stage low-pass filter, and uses an RC integrator structure in the second-stage integrator. The feedback resistor of the first-stage low-pass filter and the input resistor between the first-stage low-pass filter and the second-stage integrator are both non-linear pseudo-resistors. After adjustment, the voltage differences at both ends of the two pseudo-resistors are the same, and their non-linearity is consistent, which can cancel each other out, effectively weakening the influence of introducing pseudo-resistors on the detection of weak currents. At the same time, by reducing the value of the feedback capacitor C2 of the second-stage integrator, the output swing of the second-stage integrator is increased, and the signal voltage swing before inputting to the quantizer is increased as much as possible, improving the dynamic range of the system and further expanding the linear range of the circuit. The quantizer adopts a low-power SAR structure, further reducing the power consumption of the entire system while maintaining high-precision quantization performance. Description of the Drawings

[0026] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the drawings:

[0027] Figure 1 is the structural block diagram of a first-order incremental ADC system;

[0028] Figure 2 is the structural block diagram of a second-order continuous-time incremental ADC system;

[0029] Figure 3 is the filter structure diagram in a traditional resettable Sigma-Delta modulator;

[0030] Figure 4 is the structural schematic diagram of the extremely low-frequency and low-distortion filter of the present invention;

[0031] Figure 5 is the structural schematic diagram of an incremental ADC for weak current detection according to the present invention;

[0032] Figure 6 is the implementation structural diagram of the pseudo-resistor of the present invention. Specific Embodiments

[0033] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] Please refer to Figures 5 - 6 , the technical solutions provided by the present invention are as follows:

[0035] Embodiment 1:

[0036] The present invention provides an incremental ADC for weak current detection to solve problems such as performance degradation caused by the non-linearity of the pseudo-resistor used in the traditional second-order incremental ADC during weak current detection.

[0037] Combined with Figure 5 , an incremental ADC for weak current detection includes a resettable Sigma-Delta modulator, a resettable accumulator, and a control clock. The resettable Sigma-Delta modulator is connected to the resettable accumulator; wherein, the resettable Sigma-Delta modulator includes an extremely low-frequency and low-distortion filter, a quantizer, and a current feedback DAC. The extremely low-frequency and low-distortion filter has a current input terminal and a voltage output terminal. The extremely low-frequency and low-distortion filter is connected to the quantizer and the current feedback DAC; the quantizer is connected to the resettable accumulator and the current feedback DAC. The extremely low-frequency and low-distortion filter is composed of a first-stage low-pass filter, a second-stage integrator, a first reset switch, and a second reset switch. The control clock includes a reset signal rst and a clock signal CLK.

[0038] Combined with Figure 5 , the first - stage low - pass filter includes a feedback capacitor C1, a pseudo - resistor R1, an operational amplifier A1, and a first reset switch S1. The pseudo - resistor R1 is composed of MOS transistors. The feedback capacitor C1, the pseudo - resistor R1, and the first reset switch S1 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier A1. The inverting input terminal of the first - stage low - pass filter is connected to the output terminal of the current - feedback DAC. The non - inverting input terminal of the first - stage low - pass filter is grounded. The first reset switch S1 is used to reset the first - stage low - pass filter and is controlled by the reset signal rst. The first - stage low - pass filter performs a summation operation on the input weak current signal and the feedback current signal output by the current - feedback DAC to obtain a summation analog signal, integrates the summation analog signal, and inputs it to the second - stage integrator.

[0039] Combined with Figure 5 , the second - stage integrator includes a feedback capacitor C2, a pseudo - resistor R2, an operational amplifier A2, and a second reset switch S2. The pseudo - resistor R2 is composed of MOS transistors. The feedback capacitor C2 and the second reset switch S2 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier A2. The pseudo - resistor R2 connects the output terminal of the first - stage low - pass filter and the inverting input terminal of the operational amplifier A2. The non - inverting input terminal of the second - stage integrator is grounded. The output terminal of the second - stage integrator is connected to the input terminal of the quantizer. The second reset switch S2 is used to reset the second - stage integrator and is controlled by the reset signal rst. The second - stage integrator integrates and noise - shapes the analog signal output by the first - stage low - pass filter and outputs the signal to the quantizer.

[0040] Combined with Figure 5 , the quantizer is connected to the output terminal of the second - stage integrator, the input terminal of the resettable accumulator, and the input terminal of the current - feedback DAC. The quantizer adopts a SAR quantization structure to achieve multi - bit quantization. The quantizer is used to compare the analog signal output by the second - stage integrator and convert the comparison result into a digital signal and transmit it to the resettable accumulator.

[0041] Combined with Figure 5 , the current - feedback DAC is connected to the input terminal of the first - stage low - pass filter and the output terminal of the quantizer. The current - feedback DAC has a voltage input terminal and a current output terminal. The digital signal output by the quantizer is input to the input terminal of the current - feedback DAC, converted into an analog signal, and output as a feedback current through the current - feedback DAC output terminal to the first - stage low - pass filter for integration, which can push the quantization error to high frequencies.

[0042] Combined with Figure 5, the resettable accumulator has a reset function and is controlled by the reset signal rst. The resettable accumulator is connected to the output terminal of the quantizer and is used to accumulate the output of the comparator; the resettable accumulator is used to accumulate the 1 or 0 output by the comparator in each sampling period. Each time the output of the comparator is 1, the accumulator is incremented by 1; when the comparator output is 0, the accumulator remains unchanged. After one sampling period, the value of the accumulator is the digital representation of the input signal.

[0043] Combined with Figure 5 , the control clock includes the reset signal rst and the clock signal CLK. The reset signal rst is used to control the first reset switch, the second reset switch, and the accumulator reset. The clock signal CLK is used to control the quantizer and the resettable accumulator.

[0044] Combined with Figure 6 , the pseudo-resistors R1 and R2 are composed of equivalent resistor units based on MOS transistors, and the equivalent resistor units are composed of at least one of the following structures:

[0045] (a) MOS-Bipolar pseudo-resistor structure, where the gate and drain of the MOS transistor are connected, including single-transistor structure, cascaded structure, or complementary symmetric structure; when a voltage is applied between ports A and B, this structure can be equivalent to a resistor. When VAB < 0, the MOS transistor is equivalent to a diode-connected MOS transistor; when VAB > 0, it is equivalent to a diode-connected bipolar transistor. For the pseudo-resistor with a single-transistor structure, by reasonably selecting the parameters of the MOS transistor (such as the aspect ratio, etc.), its equivalent resistance value can be determined. In the cascaded structure, multiple single-transistor pseudo-resistors are connected in sequence, which can increase the equivalent resistance value; the complementary symmetric structure uses symmetric connection of different types of MOS transistors (such as NMOS and PMOS) to meet the requirements of specific circuits for resistor performance.

[0046] (b) Tunable pseudo-resistor structure, the gate of the MOS transistor is connected to the tunable voltage Vtune, and the resistance value of its equivalent resistor unit is controlled by the gate voltage Vtune, and the pseudo-resistor resistance value can be dynamically adjusted.

[0047] The working process of this embodiment is as follows: At the beginning of each conversion cycle, the first reset switch and the second reset switch are closed to reset the output of the very low frequency and low distortion filter in the resetable Sigma-Delta modulator to zero; the accumulator performs a reset operation simultaneously. After the first reset switch and the second reset switch are disconnected, the integration, quantization, and output of the weak current signal output by the biosensor, etc. are started. After the first-stage low-pass filter amplifies, integrates, and filters the input current signal, the output signal is transmitted to the second-stage integrator for integration. The signal output by the second-stage integrator enters the quantizer for quantization to generate a binary code stream, which is converted into a current signal by the current feedback DAC, and the feedback current signal is transmitted to the first-stage low-pass filter to reduce the quantization error and push the error to the high-frequency region. The above integration, quantization, and feedback processes are repeated multiple times within one conversion cycle. The accumulator accumulates the results of each integration and quantization to obtain the final output.

[0048] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An incremental ADC for weak current detection, characterized by: The incremental ADC comprises: a resettable Sigma-Delta modulator, a resettable accumulator and a control clock; The resettable Sigma-Delta modulator includes a very low frequency low distortion filter, a quantizer and a current feedback DAC; The extremely low frequency low distortion filter has a current input terminal and a voltage output terminal; The output end of the very low frequency low distortion filter is connected to the input end of the quantizer; the output end of the quantizer is connected to the input end of the resettable accumulator and the current feedback DAC; the output end of the current feedback DAC is connected to the input end of the very low frequency low distortion filter; The extremely low frequency low distortion filter comprises a first-stage low-pass filter, a second-stage integrator, a first reset switch and a second reset switch; wherein the first reset switch is used to reset the first-stage low-pass filter; and the second reset switch is used to reset the second-stage integrator. The resettable accumulator has a reset function and is used to accumulate the output results of the quantizer; The control clock includes a reset signal rst and a clock signal CLK; The reset signal rst is used to control the first reset switch, the second reset switch and the accumulator to reset; the clock signal CLK is used to control the quantizer and the resettable accumulator.

2. An incremental ADC for weak current detection as claimed in claim 1, characterized in that: The first-stage low-pass filter includes: a feedback resistor R1, an operational amplifier and a feedback capacitor C1; The feedback resistor is implemented by a pseudo resistor based on a MOS transistor, wherein the operational amplifier has two input terminals and one output terminal; the pseudo resistor R1 and the feedback capacitor C1 are connected in parallel to the inverting input terminal and the output terminal of the operational amplifier.

3. An incremental ADC for weak current detection as claimed in claim 1, characterized in that: The second stage integrator comprises: an input resistor R2, an operational amplifier and a feedback capacitor C2; The input resistor is implemented by a pseudo resistor based on a MOS transistor, wherein the operational amplifier has two input terminals and one output terminal; the pseudo resistor R2 is connected in series to the inverting input terminal of the operational amplifier, and the feedback capacitor C2 is connected in parallel to the inverting input terminal and the output terminal of the operational amplifier.

4. The incremental ADC for weak current detection as claimed in claim 1, characterized in that: The quantizer has an input terminal and an output terminal; the quantizer uses a multi-bit quantizer with a SAR structure.

5. The incremental ADC for weak current detection as claimed in claim 1, characterized in that: The current feedback DAC has a voltage input terminal and a current output terminal, and the output terminal outputs in the form of current, converting the digital signal into an analog signal and outputting it to an extremely low frequency low distortion filter to compensate for the quantization error.

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