Coding method, decoding method and device

Abstract

The invention discloses a coding method, a decoding method and a device, which are used for supporting an IEEE (Institute of Electrical and Electronic Engineers) 802.11 ax next generation Wi-Fi (Wireless Fidelity) protocol (such as 802.11 be, Wi-Fi7 or EHT), or an IEEE 802.11 be next generation Wi-Fi protocol (such as 802.11 bn, Wi-Fi 8 or UHR), or Wi-Fi AI (Wireless Fidelity), or MMW (Millimeter Wave), or UWB (Ultra Wideband) or perception and the like. After acquiring an information bit sequence, the first communication device performs LDPC encoding on the information bit sequence based on a check matrix to obtain an encoded sequence, and outputs the sequence. The length of the sequence is N1, N1 is n times of 1944, and n is an integer greater than or equal to 2. Z of the check matrix can be equal to 81. And after obtaining the to-be-decoded information, the second communication device performs LDPC decoding in combination with the check matrix to obtain an information bit sequence. The method can improve the decoding performance.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to an encoding method, a decoding method, and a device. Background Art

[0002] Wireless local area network (WLAN) transmission standards such as Institute of Electrical and Electronics Engineers (IEEE) 802.11n / ac / ax / be mainly focus on improving the user experience in large bandwidth scenarios (such as 60 gigahertz (GHz)), including enhancing the average user throughput and the energy usage efficiency of battery-powered devices. Large bandwidth scenarios require supporting high-speed and reliable transmission of data, video, and other services on limited frequency and power resources, so high-reliability and high-efficiency channel coding and decoding schemes are needed.

[0003] In the field of channel coding, concatenated codes (such as Turbo codes) and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods, and they both have performance close to the Shannon limit. Compared with concatenated codes, LDPC codes can have the following advantages: good error performance can be obtained without a deep interleaver; better frame error rate performance; significantly reduced error floors; decoding is not based on a trellis; parallel decoding is supported, and the decoding delay is small, etc. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE 802.11n / ac / ax.

[0004] How to further improve the decoding performance of LDPC codes urgently needs to be solved. Summary of the Invention

[0005] Embodiments of this application provide an encoding method, a decoding method, and a device, which can support LDPC codes with longer code lengths and improve the decoding performance.

[0006] In a first aspect, embodiments of this application provide an encoding method, which is applied to a first communication device. The first communication device includes a Wi-Fi device, or a chip or functional module placed in a Wi-Fi device, etc. The method includes:

[0007] Obtain an information bit sequence; perform low-density parity-check (LDPC) encoding on the information bit sequence based on a parity-check matrix to obtain an encoded sequence. The length of the encoded sequence is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2. The expansion factor Z of the parity-check matrix is 81; output the encoded sequence.

[0008] In the embodiments of the present application, the parity-check matrix can be applicable to an information bit sequence with a code length that is n times 1944, where n is an integer greater than or equal to 2, thereby improving the transmission reliability of the system and the decoding performance. Generally speaking, the longer the applicable code length, the better the reliability of the parity-check matrix and the better the decoding performance.

[0009] In a second aspect, an embodiment of the present application provides a decoding method, which is applied to a second communication device. The second communication device includes a Wi-Fi device, or a chip or functional module placed in the Wi-Fi device, etc. The method includes:

[0010] Obtain information to be decoded, where the length of the information to be decoded is N1, and N1 is n times 1944, where n is an integer greater than or equal to 2; perform low-density parity-check (LDPC) decoding on the information to be decoded based on the parity-check matrix to obtain an information bit sequence, where the expansion factor Z of the parity-check matrix is 81.

[0011] Combined with the first aspect or the second aspect, in a possible implementation, the parity-check matrix is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and y-th column of the matrix prototype of the basic parity-check matrix. The code length N0 corresponding to the basic parity-check matrix is less than or equal to 1944, the code rate corresponding to the basic parity-check matrix is the same as the code rate corresponding to the parity-check matrix, and the element in the x-th row and j-th column is greater than or equal to 0, where both x and y are positive integers.

[0012] Combined with the first aspect or the second aspect, in a possible implementation, that the parity-check matrix is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and y-th column of the matrix prototype of the basic parity-check matrix includes: the matrix prototype of the parity-check matrix is determined based on the matrix prototype of the basic parity-check matrix and an expansion indication matrix. The size of the expansion indication matrix is the same as the size of the matrix prototype of the basic parity-check matrix. The element in the x-th row and y-th column of the expansion indication matrix is used to indicate that the square matrix at the corresponding position in the matrix prototype of the parity-check matrix is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and y-th column of the matrix prototype of the basic parity-check matrix.

[0013] Combined with the first aspect or the second aspect, in a possible implementation, the first column and the second column of the matrix in the matrix prototype of the parity-check matrix corresponding to the parity-check bits are obtained by performing positive diagonal expansion or anti-diagonal expansion on both the first element and the last element in the first column of the matrix corresponding to the parity-check bits in the matrix prototype of the basic parity-check matrix.

[0014] Generally speaking, in the matrix prototype of the basic parity-check matrix, the first column in the matrix corresponding to the parity bits has a "1-0-1" structure, that is, the first row and the last row of this first column from top to bottom are both 1, and the remaining rows are all 0. Therefore, in the embodiments of the present application, the expansion methods of the first element (such as 1) and the last element (such as 1) in the first column of the matrix corresponding to the parity bits in the matrix prototype of the basic parity-check matrix can be the same. Through the same expansion method, the elements at the corresponding positions in the first column and the second column of the matrix corresponding to the parity bits in the matrix prototype of the parity-check matrix can be obtained, so as to maintain that the matrix corresponding to the parity bits can still maintain a similar structure (such as the first element or the second element in the first column being 1, and the last element or the penultimate element in the first column being 1), which can ensure the fast and efficient encoding algorithm of the LDPC code.

[0015] Combined with the first aspect or the second aspect, in a possible implementation manner, the elements in the matrix corresponding to the parity bits in the matrix prototype of the parity-check matrix except the first column and the second column are: obtained by performing a positive diagonal expansion on all the elements 0 except the first column in the matrix corresponding to the parity bits in the matrix prototype of the basic parity-check matrix.

[0016] In the embodiments of the present application, the expansion method of the other elements except the first column in the matrix corresponding to the parity bits in the matrix prototype of the basic parity-check matrix is a positive diagonal expansion. The parity-check matrix obtained through the above expansion method can not only ensure fast and efficient encoding, but also reduce the implementation complexity due to the same expansion method.

[0017] Exemplarily, the code length corresponding to the matrix prototype of the basic parity-check matrix is 1944 bits. By using the LDPC codes with different code rates and a code length of 1944 bits in the WLAN system as the basic matrix for expansion, the parity-check matrices with a code length of 3888 bits corresponding to the respective code rates are obtained. Thus, the encoding and decoding architectures of the original WLAN LDPC codes can be reused as much as possible, so that the new LDPC long code has as little modification as possible to the LDPC encoding module and the decoding module, reducing the implementation complexity.

[0018] Combined with the first aspect or the second aspect, in a possible implementation manner, the matrix corresponding to the information bits in the matrix prototype of the parity-check matrix is: obtained by performing a positive diagonal expansion or an anti-diagonal expansion on the element in the x-th row and the y-th column in the matrix corresponding to the information bits in the matrix prototype of the basic parity-check matrix.

[0019] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is the following matrix 1:

[0020]

[0021] Among them, -1 represents the all-zero matrix of Z*Z, 0 represents the identity matrix of Z*Z, and elements greater than 0 represent the cyclic permutation matrix CPM of the identity matrix of Z*Z.

[0022] The "1" in matrix 1 or the "2" in matrix 2 shown in the embodiments of this application are used to distinguish different matrices and facilitate subsequent reference.

[0023] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 1 is:

[0024]

[0025] Among them, -1 indicates that the element at the corresponding position in the matrix prototype of the parity-check matrix is obtained by expanding the element j1 in the matrix prototype of the basic parity-check matrix into a 2*2 all-zero matrix; 0 indicates that the element at the corresponding position in the matrix prototype of the parity-check matrix is obtained by positive diagonal expansion of the element j2 in the matrix prototype of the basic parity-check matrix; 1 indicates that the element at the corresponding position in the matrix prototype of the parity-check matrix is obtained by anti-diagonal expansion of the element j3 in the matrix prototype of the basic parity-check matrix. The explanations for each element in the matrix prototype are equally applicable to matrices 2 to 14 shown below, and will not be repeated hereinafter.

[0026] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is the following matrix 2:

[0027]

[0028] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 2 is:

[0029]

[0030] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is the following matrix 3:

[0031]

[0032] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 3 is:

[0033]

[0034] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is the following matrix 4:

[0035]

[0036] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 4 is:

[0037]

[0038] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is the following matrix 5:

[0039]

[0040] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 5 is:

[0041]

[0042] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is the following matrix 6:

[0043]

[0044] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 6 is:

[0045]

[0046] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 7:

[0047]

[0048] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 7 is:

[0049]

[0050] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 8:

[0051]

[0052] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 8 is:

[0053]

[0054] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 9:

[0055]

[0056]

[0057] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 9 is:

[0058]

[0059] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 10:

[0060]

[0061] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 10 is:

[0062]

[0063] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 11:

[0064]

[0065] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 11 is:

[0066]

[0067] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 12:

[0068]

[0069] In a possible implementation manner in combination with the first aspect or the second aspect, the extended indication matrix corresponding to matrix 12 is:

[0070]

[0071] In a possible implementation manner in combination with the first aspect or the second aspect, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 13:

[0072]

[0073] In a possible implementation manner in combination with the first aspect or the second aspect, the extended indication matrix corresponding to matrix 13 is:

[0074]

[0075] In a possible implementation manner in combination with the first aspect or the second aspect, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 14:

[0076]

[0077] In a possible implementation manner in combination with the first aspect or the second aspect, the extended indication matrix corresponding to matrix 14 is:

[0078]

[0079] In a possible implementation manner in combination with the first aspect or the second aspect, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is the following matrix 15:

[0080]

[0081] In a possible implementation manner in combination with the first aspect or the second aspect, the extended indication matrix corresponding to matrix 15 is:

[0082]

[0083] In a possible implementation manner in combination with the first aspect or the second aspect, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity-check matrix is the following matrix 16:

[0084]

[0085] In a possible implementation manner in combination with the first aspect or the second aspect, the extended indication matrix corresponding to matrix 16 is:

[0086]

[0087] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is the following matrix 17:

[0088]

[0089] Combined with the first aspect or the second aspect, in a possible implementation, the extended indication matrix corresponding to matrix 17 is:

[0090]

[0091] Combined with the first aspect or the second aspect, in a possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity-check matrix is the following matrix 18:

[0092] -1 61 -1 75 4 -1 63 -1-1 56 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 8 -1-1 2-1-1 17 25 -1 1 -1 0 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 61 -1 75 -1-1 4 -1 6356 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 8 -1-1 -1-1 2 17 -1-1 25 -1 1 -1 0 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 56 -1-1 74 -1 77 20 -1-1 -1-1 -1-1 -1 64 -1-1 24 -1 4-1 67 -1-1 7 -1-1 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 -1-1 -1-1 -1-1 -1 -1 5674 -1 77 -1-1 20 -1-1 -1-1 -1-1 -1 64 24 -1 4 -1 67 -1-1 -1-1 7 -1-1 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 -1-1 -1-1 -1-1 28 -1 21 -1-1 68 10 -1-1 7 -1 14 -165 -1-1 -1-1 -1-1 -1 23 -1-1 -1-1 -1-1 75 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1-1-1 -1-1 -1 -1 28 -1 21 68 -1-1 10 7 -1 14 -1 65 -1-1 -1-1 -1-1 -1 23 -1-1 -1-1 -1-1 -1-1 75 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 -1-1 -1-1 -1 48 -1 38 43-1 78 -1-1 76 -1-1 -1-1 -1-1 -1-1 5 -1-1 36 -1-1 15 -1 72 -1-1 -1-1 -1-1 -1-1-1-1 -1 0 -1 0 -1-1 -1-1 -1-1 -1 48 -1 38 -1-1 43 -1 78 76 -1-1 -1-1 -1-1 -1-1 -1-1 5 36 -1-1 -1-1 15 -1 72 -1-1 -1-1 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 -1-1 40 -1-12 -1 53 25 -1-1 -1 52 -1-1 62 -1-1 -1 20 -1-1 -1-1 -1 44 -1-1 -1-1 -1-1 -1-1 0 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 -1 -1 40 2 -1 53 -1-1 25 -1-1 -1 52 62 -1-1 -1 20 -1-1 -1-1 -1 44 -1-1 -1-1 -1-1 -1-1 -1-1 0 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1-1 69 -1-1 23 64 -1 10 -1 22 -1-1 -1-1 21 -1-1 -1-1 -1-1-1-1 -1-1 -1 68 23 -1 29 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1 -169 23 -1-1 64 -1 10 -1 22 -1-1 21 -1-1 -1-1 -1-1 -1-1 -1-1 -1 68 -1-1 23 -129 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 0 -1 0 -1-1 -1 12 -1 0 68 -1 20 -1-1 5561 -1-1 -1-1 40 -1-1 -1-1 -1-1 52 -1-1 -1-1 -1-1 -1-1 44 -1-1 -1-1 -1-1 -1-1-1-1 -1-1 0 -1 0 -1 12 -1 0 -1-1 68 -1 20 55 -1-1 61 -1-1 40 -1-1 -1-1 -1-1 -1-1 52 -1-1 -1-1 -1-1 44 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 0 -1 0 -1 58 -1 8-1 34 -1 64 -1 78 -1-1 -1-1 -1 11 -1 78 24 -1-1 -1-1 -1-1 -1-1 -1-1 -1 58 -11 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1 0 -1 58 -1 8 -1 34 -1 64 -1 78 -1-1 -1-1 -1 11 -1 78 -1-1 24 -1-1 -1-1 -1-1 -1-1 -1-1 -1 58 -1 1 -1-1 -1-1 -1-1 -1-1 -1-1 -1-1 -1Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 18 is:

[0093]

[0094] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 19:

[0095]

[0096] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 19 is:

[0097]

[0098] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity-check matrix is the following matrix 20:

[0099]

[0100] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 20 is:

[0101]

[0102] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 21:

[0103]

[0104] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 21 is:

[0105]

[0106] Combined with the first aspect or the second aspect, in a possible implementation manner, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity-check matrix is the following matrix 22:

[0107]

[0108] Combined with the first aspect or the second aspect, in a possible implementation manner, the extended indication matrix corresponding to matrix 22 is:

[0109]

[0110] In a third aspect, an embodiment of the present application provides a first communication device for performing the method in the first aspect or any possible implementation manner. The first communication device includes a module for performing the method in the first aspect or any possible implementation manner.

[0111] In a fourth aspect, an embodiment of the present application provides a second communication device for performing the method in the second aspect or any possible implementation manner. The second communication device includes a module for performing the method in the second aspect or any possible implementation manner.

[0112] In a fifth aspect, an embodiment of the present application provides a first communication device. The first communication device includes a processor for performing the method shown in the first aspect or any possible implementation manner above. The processor is used to execute a program stored in a memory. When the program is executed, the method shown in the first aspect or any possible implementation manner above is executed.

[0113] In a possible implementation manner, the memory is located outside the first communication device.

[0114] In a possible implementation manner, the memory is located inside the first communication device.

[0115] In an embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together. Exemplarily, the first communication device may be a chip.

[0116] In a possible implementation manner, the first communication device further includes a transceiver for receiving information or sending information.

[0117] In a sixth aspect, an embodiment of the present application provides a second communication device. The second communication device includes a processor for performing the method shown in the second aspect or any possible implementation manner above. The processor is used to execute a program stored in a memory. When the program is executed, the method shown in the second aspect or any possible implementation manner above is executed.

[0118] In a possible implementation manner, the memory is located outside the second communication device.

[0119] In a possible implementation manner, the memory is located inside the second communication device.

[0120] In an embodiment of the present application, the processor and the memory may also be integrated into one device, that is, the processor and the memory may also be integrated together. Exemplarily, the second communication device may be a chip.

[0121] In a possible implementation, the second communication device further includes a transceiver, which is used to receive information or send information.

[0122] In a seventh aspect, an embodiment of the present application provides a first communication device, which includes a logic circuit and an interface, and the logic circuit is coupled to the interface; the interface is used to input and / or output information, and the logic circuit is used to execute the method described in the first aspect or any possible implementation.

[0123] In an eighth aspect, an embodiment of the present application provides a second communication device, which includes a logic circuit and an interface, and the logic circuit is coupled to the interface; the interface is used to input and / or output information, and the logic circuit is used to execute the method described in the second aspect or any possible implementation.

[0124] In a ninth aspect, an embodiment of the present application provides a computer-readable storage medium, which is used to store a computer program. When it runs on a computer, the method described in any one of the first aspect to the second aspect or any possible implementation is executed.

[0125] In a tenth aspect, an embodiment of the present application provides a computer program product. When it runs on a computer, the method described in any one of the first aspect to the second aspect or any possible implementation is executed.

[0126] In an eleventh aspect, an embodiment of the present application provides a computer program. When it runs on a computer, the method described in any one of the first aspect to the second aspect or any possible implementation is executed.

[0127] In a twelfth aspect, an embodiment of the present application provides a communication system, which includes a first communication device and / or a second communication device. The first communication device is used to execute the method described in the first aspect or any possible implementation of the first aspect, and the second communication device is used to execute the method described in the second aspect or any possible implementation of the second aspect. Description of the Drawings

[0128] Figure 1a is a schematic diagram of a matrix prototype of a reference check matrix provided by an embodiment of the present application;

[0129] Figure 1b is a schematic diagram of a CPM provided by an embodiment of the present application;

[0130] Figure 2a is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application;

[0131] Figure 2b It is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application;

[0132] Figure 2c It is a schematic diagram of the architecture of a communication system provided by an embodiment of the present application;

[0133] Figure 3 It is a schematic flowchart of an encoding method and a decoding method provided by an embodiment of the present application;

[0134] Figure 4a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0135] Figure 4b It is provided by an embodiment of the present application and Figure 4a The corresponding extended indication matrix schematic diagram;

[0136] Figure 5a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0137] Figure 5b It is provided by an embodiment of the present application and Figure 5a The corresponding extended indication matrix schematic diagram;

[0138] Figure 6a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0139] Figure 6b It is provided by an embodiment of the present application and Figure 6a The corresponding extended indication matrix schematic diagram;

[0140] Figure 7a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0141] Figure 7b It is provided by an embodiment of the present application and Figure 7a The corresponding extended indication matrix schematic diagram;

[0142] Figure 8a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0143] Figure 8b It is provided by an embodiment of the present application and Figure 8a The corresponding extended indication matrix schematic diagram;

[0144] Figure 9a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0145] Figure 9b It is provided by an embodiment of the present application and Figure 9aSchematic diagram of the corresponding extended indication matrix;

[0146] Fig.10a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0147] Fig.10b It is provided by an embodiment of the present application and is Fig.10a Schematic diagram of the corresponding extended indication matrix;

[0148] Fig.11a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0149] Fig.11b It is provided by an embodiment of the present application and is Fig.11a Schematic diagram of the corresponding extended indication matrix;

[0150] Fig.12a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0151] Figure 12b It is provided by an embodiment of the present application and is Fig.12a Schematic diagram of the corresponding extended indication matrix;

[0152] Fig.13a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0153] Fig.13b It is provided by an embodiment of the present application and is Fig.13a Schematic diagram of the corresponding extended indication matrix;

[0154] Fig.13c It is provided by an embodiment of the present application and is Fig.13a Schematic diagram of the corresponding extended indication matrix;

[0155] Fig.14a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0156] Fig.14b It is provided by an embodiment of the present application and is Fig.14a Schematic diagram of the corresponding extended indication matrix;

[0157] Fig.15a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0158] Fig.15b It is provided by an embodiment of the present application and is Fig.15a Schematic diagram of the corresponding extended indication matrix;

[0159] Fig.16a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0160] Fig.16b is the schematic diagram of the extended indication matrix provided by the embodiment of the present application corresponding to Fig.16a ;

[0161] Fig.17a is the schematic diagram of the matrix prototype of a check matrix provided by the embodiment of the present application;

[0162] Fig.17b is the schematic diagram of the extended indication matrix provided by the embodiment of the present application corresponding to Fig.17a ;

[0163] Fig.18 is the partial schematic diagram of the shortening operation in LDPC coding provided by the embodiment of the present application;

[0164] Fig.19a is the schematic diagram after the positive diagonal expansion of element i provided by the embodiment of the present application;

[0165] Fig.19b is the schematic diagram after the anti-diagonal expansion of element i provided by the embodiment of the present application;

[0166] Fig.20a is the schematic diagram of two options of positive diagonal expansion and anti-diagonal expansion provided by the embodiment of the present application;

[0167] Fig.20b is the schematic diagram of a tree expansion provided by the embodiment of the present application;

[0168] Fig.21a is the schematic diagram of a simulation result provided by the embodiment of the present application;

[0169] Figure 21b is the schematic diagram of a simulation result provided by the embodiment of the present application;

[0170] Fig.21c is the schematic diagram of a simulation result provided by the embodiment of the present application;

[0171] Fig.21d is the schematic diagram of a simulation result provided by the embodiment of the present application;

[0172] Fig. 22 is the schematic diagram of the structure of a communication device provided by the embodiment of the present application;

[0173] Fig.23 is the schematic diagram of the structure of a communication device provided by the embodiment of the present application;

[0174] Fig.24 is the schematic diagram of the structure of a communication device provided by the embodiment of the present application;

[0175] Fig.25 It is a schematic diagram of the matrix prototype grouping design of the basic check matrix provided by an embodiment of the present application;

[0176] Fig.26a and Figure 26b It is a schematic diagram of the extended indication matrix provided by an embodiment of the present application;

[0177] Fig.27a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0178] Figure 27b It is provided by an embodiment of the present application and Fig.27a The corresponding extended indication matrix schematic diagram;

[0179] Fig.28a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0180] Fig.28b It is provided by an embodiment of the present application and Fig.28a The corresponding extended indication matrix schematic diagram;

[0181] Fig.29a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0182] Fig.29b It is provided by an embodiment of the present application and Fig.29a The corresponding extended indication matrix schematic diagram;

[0183] Fig.30a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0184] Fig.30b It is provided by an embodiment of the present application and Fig.30a The corresponding extended indication matrix schematic diagram;

[0185] Fig.31a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0186] Fig.31b It is provided by an embodiment of the present application and Fig.31a The corresponding extended indication matrix schematic diagram;

[0187] Fig.32a It is a schematic diagram of the matrix prototype of a check matrix provided by an embodiment of the present application;

[0188] Figure 32b It is provided by an embodiment of the present application and Fig.32a The corresponding extended indication matrix schematic diagram;

[0189] Fig.33aIt is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0190] Figure 33b is provided by an embodiment of the present application and Fig.33a corresponding extended indication matrix schematic diagram;

[0191] Fig.34a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0192] Fig.34b is provided by an embodiment of the present application and Fig.34a corresponding extended indication matrix schematic diagram;

[0193] Fig.35a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0194] Fig.35b is provided by an embodiment of the present application and Fig.35a corresponding extended indication matrix schematic diagram;

[0195] Fig.36a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0196] Fig.36b is provided by an embodiment of the present application and Fig.36a corresponding extended indication matrix schematic diagram;

[0197] Fig.37a It is a schematic diagram of the matrix prototype of a parity-check matrix provided by an embodiment of the present application;

[0198] Figure 37b is provided by an embodiment of the present application and Fig.31a corresponding extended indication matrix schematic diagram. Detailed implementation manners

[0199] To facilitate understanding of the technical solution of the present application, the present application will be further described below with reference to the accompanying drawings.

[0200] Terms such as "first" and "second" in the specification, claims and drawings of the present application are only used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device, etc. that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices, etc.

[0201] As used herein, "embodiment" means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art can explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0202] In the present application, "at least one (item)" means one or more, "a plurality" means two or more, "at least two (items)" means two or three or more, and "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously. Here, A and B can be singular or plural. "Or" means that two relationships can exist, such as only A exists and only B exists; when A and B are not mutually exclusive, it can also mean that three relationships exist, such as only A exists, only B exists, and both A and B exist simultaneously. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (one) of the following" or its similar expression refers to any combination of these items. For example, at least one (one) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0203] The LDPC codes adopted in standards such as IEEE802.11ac / ax are quasi-cyclic (QC) LDPC (QC-LDPC) codes. QC-LDPC codes are a class of widely used structured LDPC codes. Due to the unique structure of their parity-check matrices, they can be implemented using simple feedback shift registers during encoding, and can better solve the encoding complexity problem of LDPC codes.

[0204] Currently, 12 LDPC code check matrices are adopted in the standard. Among them, there are three types of code lengths N: N = 648, or N = 1296, or N = 1944. Each code length can support 4 different code rates: 1 / 2, 2 / 3, 3 / 4, 5 / 6. The matrix prototypes of the check matrices for each code length and code rate are different. The check bit parts (the matrices corresponding to the check bits shown below, or the check square matrices) in the matrix prototypes of the 12 check matrices with different code lengths and code rates have the same structure. Exemplarily, the selection of the code rate can be determined by the modulation and coding scheme (MCS) adaptively selected by the current transmission system according to the link. Thus, the communication device in the wireless local area network (WLAN) can select a check matrix from the 12 check matrices according to the given code length and code rate. The above-mentioned same structure can be understood as Figure 1a the element in the first row and first column of the check bit part in the matrix prototypes of different check matrices is 1, and the element in the last row and first column is 1. As Figure 1a shown in the first matrix in, the first column of the check bit part is the 13th column in the matrix prototype of the check matrix, and the last column of the check bit part is the 24th column in the matrix prototype of the check matrix. Figure 1a In the second matrix in, the first column of the check bit part is the 17th column in the matrix prototype of the check matrix, and the last column of the check bit part is the 24th column in the matrix prototype of the check matrix. Figure 1a In the third matrix in, the first column of the check bit part is the 19th column in the matrix prototype of the check matrix, and the last column of the check bit part is the 24th column in the matrix prototype of the check matrix. Figure 1a In the second matrix in, the first column of the check bit part is the 21st column in the matrix prototype of the check matrix, and the last column of the check bit part is the 24th column in the matrix prototype of the check matrix.

[0205] Figure 1a What is shown is the matrix prototype of the LDPC code check matrix with code length N = 1944 and different code rates. Figure 1a The "-" in represents the all-zero matrix of Z*Z, Figure 1a The "0" in represents the identity matrix of Z*Z, Figure 1a The non-0 elements in represent the circulant permutation matrix (CPM) of the identity matrix of Z*Z. Such as CPM is represented by P iIt is represented that \(i\) represents the cyclic shift value, or the number of bits by which the identity matrix is cyclically shifted to the right, or the CPM coefficient, or the elements greater than or equal to 0 in the matrix prototype of the parity-check matrix, etc. For the specific name of \(i\), the embodiments of the present application do not make any limitations. \(i\) is a non-negative integer, such as \(0\leq i\leq Z - 1\). When \(i = 0\), the CPM can be understood as a \(Z\times Z\) identity matrix, or a CPM with a cyclic shift value of 0. Exemplarily, Figure 1a in which \(Z = N / 24\). The aforementioned "24" can be the same as the number of columns of the matrix prototype of the parity-check matrix in the IEEE802.11ac / ax standard. For IEEE801.11ac / ax, regardless of whether the code length \(N = 648\), or \(N = 1296\), or \(N = 1944\), the number of columns of the matrix prototype of the parity-check matrix is 24 columns.

[0206] Exemplarily, taking Figure 1a the element "1" (i.e., \(i = 1\)) in as an example, this element 1 can be expanded into a CPM of \(81\times81\) (\(1944 / 24 = 81\)). This CPM can be obtained by cyclically shifting the identity matrix 1 bit to the right, as shown below:

[0207]

[0208] Exemplarily, taking a \(4\times4\) CPM as an example, Figure 1b respectively shows the CPM when \(i = 0\), the CPM when \(i = 1\), the CPM when \(i = 2\), and the CPM when \(i = 3\). Figure 1b The CPM shown is only an example. For other CPMs of the \(Z\times Z\) identity matrix in the embodiments of the present application, the final P can be obtained with reference to the principle shown in Figure 1a or Figure 1b shown, and will not be elaborated hereinafter. i

[0209] Since LDPC codes can improve the transmission reliability of wireless transmission systems, LDPC codes have been widely used in WLAN standards. To further improve the data transmission reliability of Wi-Fi systems, current standards or next-generation standards, etc. may consider LDPC codes with longer code lengths, so as to enable the coding module to have stronger error control performance and improve the decoding performance of the decoding module.

[0210] In view of this, embodiments of the present application provide an encoding method, a decoding method, and a device. The method involves a new LDPC code that can support a longer code length. The parity-check matrix provided by the embodiments of the present application can be applicable to a longer code length. For example, the parity-check matrix can be applicable to n times the code length of 1944, where n is an integer greater than or equal to 2, and the parity-check matrix can also improve the decoding performance. Exemplarily, based on the existing WLAN LDPC long code (such as a code length of 1944 bits), the LDPC code (or referred to as the LDPC long code) provided by the embodiments of the present application (such as a code length of 3888 bits) can achieve excellent performance. Further, the new LDPC long code provided by the embodiments of the present application can reuse the encoding and decoding architecture of the original WLAN LDPC code as much as possible. For example, the changes to the existing LDPC encoding module and LDPC decoding module are small, which can reduce the implementation complexity of LDPC encoding and decoding.

[0211] In the embodiments of the present application, each matrix shown below can be referred to as a prototype of the parity-check matrix, or a matrix prototype of the parity-check matrix (matrix prototypes of the parity-matrices), or a matrix prototype for the codeword block length N (matrix prototypes for codeword block length N), or a mother matrix, etc. The present application does not limit the specific names of the matrices involved in the embodiments of the present application. Generally speaking, a matrix including elements 0 and 1 expanded based on Z and the cyclic shift value i is called a parity-check matrix. Therefore, each matrix shown below can also be called a matrix before CPM expansion, etc. Each matrix shown in Examples 1 to 14 below can be called a matrix prototype of the parity-check matrix, and a matrix expanded based on the elements in each matrix shown in Examples 1 to 14 can be called a parity-check matrix. For the specific expansion method, reference can be made to the relevant descriptions regarding Figure 1a and Figure 1b The specific content of the expanded parity-check matrix will not be listed one by one in the embodiments of the present application.

[0212] The code length in the embodiments of the present application can also be referred to as a codeword block length (a codeword block length), etc. The present application does not limit the specific names of the code length. Z in the embodiments of the present application can be referred to as a subblock size, or an expansion factor, or a lift factor, etc. The present application does not limit the specific names of Z. For ease of description, the following takes Z as an example of an expansion factor for illustration.

[0213] In the embodiments of the present application, Z = N / 48. However, with the progress of the standard, the method for calculating Z may also change in the future, and the embodiments of the present application do not limit this. For ease of understanding, different letter parameters are used to represent different meanings in the embodiments of the present application. For example, N represents the code length, Z represents the extension factor, R represents the code rate, K represents the number of information bits, E represents the number of parity bits, etc. However, the various letter parameters shown in the embodiments of the present application are only examples and should not be construed as limitations on the embodiments of the present application.

[0214] The communication system involved in the embodiments of the present application is introduced below.

[0215] The technical solutions provided by the embodiments of this application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi. For example, the methods provided by the embodiments of this application can be applicable to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of protocols, such as the 802.11be protocol, the 802.11bn protocol, or the next-generation protocol of the 802.11bn protocol, or a protocol that supports ambient power (AMP), etc., which will not be listed one by one. The technical solutions provided by the embodiments of this application can also be applied to wireless personal area networks (WPANs) based on millimeter wave (MMW) and ultra-wideband (UWB) technologies. For example, the methods provided by the embodiments of this application can be applicable to the IEEE 802.15 series of protocols, such as the 802.15.4a protocol, the 802.15.4z protocol, or the 802.15.4ab protocol, or a future generation of UWB WPAN protocol, etc., which will not be listed one by one. The technical solutions provided by the embodiments of this application can also be applied to the following communication systems. For example, it can be an Internet of Things (IoT) system, vehicle-to-everything (V2X, where X can represent anything), device-to-device (D2D), narrow band Internet of Things (NB-IoT) system, long term evolution (LTE) system, fifth-generation (5G) communication system, and new communication systems that emerge in the future development of communications. For example, the V2X can include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), or vehicle-to-network (V2N) communication, etc.

[0216] The WLAN system can provide high-speed and low-latency transmission. With the continuous evolution of WLAN application scenarios, the WLAN system will be applied to more scenarios or industries. For example, it can be applied to the Internet of Things industry, the vehicle-to-everything (V2X) industry, the banking industry, enterprise offices, stadiums, exhibition halls, concert halls, hotel rooms, dormitories, wards, classrooms, shopping malls, squares, streets, production workshops, and warehouses, etc. Of course, the devices that support WLAN communication or sensing (such as access points or stations) can be sensor nodes in a smart city (such as smart water meters, smart electricity meters, smart air detection nodes), smart devices in a smart home (such as smart cameras, projectors, displays, televisions, speakers, refrigerators, washing machines, etc.), nodes in the Internet of Things, entertainment terminals (such as wearable devices like augmented reality (AR), virtual reality (VR), etc.), smart devices in smart offices (such as printers, projectors, loudspeakers, speakers, etc.), V2X devices in the vehicle-to-everything network, infrastructure in daily life scenarios (such as vending machines, self-service navigation desks in shopping malls, self-service cashiers, self-service ordering machines, etc.), and devices in large sports and music stadiums, etc.

[0217] Although the embodiments of this application mainly take WLAN as an example, especially for networks applying the IEEE 802.11 series of standards. The embodiments of this application can also support Wi-Fi 8, also known as ultra-high reliability (UHR) or ultra-high reliability and throughput (UHRT), etc., which will not be listed one by one here. All aspects involved in the embodiments of this application can be extended to other networks adopting various standards or protocols. For example, Bluetooth, high performance radio LAN (HIPERLAN) (a wireless standard similar to the IEEE 802.11 standard), and wide area network (WAN) or other currently known or future-developed networks.

[0218] In a possible implementation manner, the method provided by the embodiments of this application can be implemented by a communication device in a communication system. For example, the communication device can be an access point (AP) or a station (STA).

[0219] An AP is a device with wireless communication capabilities that supports communication, sensing, or energy transfer using the WLAN protocol. It has the function of communicating, sensing, or transferring energy with other devices (such as non-access point stations (non-APSTA) or other access points) in the WLAN network. Of course, it can also have the function of communicating, sensing, or transferring energy with other devices. Alternatively, the access point is equivalent to a bridge connecting the wired network and the wireless network. Its main role is to connect various wireless network clients together and then connect the wireless network to the Ethernet. In the WLAN system, the access point can be referred to as an access point station (AP STA). The device with wireless communication capabilities can be a complete device or a chip, processing system, or functional module installed in the complete device. The device installing these chips, processing systems, or functional modules can, under the control of the chips, processing systems, or functional modules, implement the methods and functions of the embodiments of this application. The AP in the embodiments of this application is a device that provides services for non-AP STA and can support 802.11 series protocols or subsequent protocols, etc. For example, the access point can be an access point for a terminal (such as a mobile phone) to enter the wired (or wireless) network, mainly deployed in homes, buildings, and campuses, with a typical coverage radius of dozens of meters to hundreds of meters. Of course, it can also be deployed outdoors. Another example is that the AP can be a communication entity such as a communication server, router, switch, or bridge; the AP can include various forms of macro base stations, micro base stations, relay stations, etc. Of course, the AP can also be a chip, processing system, or module in the above various forms of devices to implement the methods and functions of the embodiments of this application.

[0220] STA is a device with wireless communication capabilities, supporting communication, sensing, or energy transfer using the WLAN protocol, and having the ability to communicate, sense, or transfer energy with other non-AP STAs or access points in the WLAN network. In a WLAN system, a station can be referred to as a non-access point station (non-AP STA). For example, an STA is any user communication device that allows a user to communicate, sense, or transfer energy with an AP and thereby communicate with the WLAN. This device with wireless communication capabilities can be a complete device, or it can be a chip, processing system, or functional module installed in a complete device. The device installed with these chips, processing systems, or functional modules can, under the control of the chip, processing system, or functional module, implement the methods and functions of the embodiments of this application. For example, an STA can be a wireless communication chip, wireless sensor, or wireless communication terminal, etc., and can also be referred to as a user. Another example is that an STA can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, a vehicle-mounted communication device supporting Wi-Fi communication, and a computer supporting Wi-Fi communication, etc. Of course, an STA can also be a chip, processing system, or module in the above various forms of devices to implement the methods and functions of the embodiments of this application.

[0221] Exemplarily, the communication system to which the method provided by the embodiments of this application can be applied can include an access point and stations. For example, the embodiments of this application can be applicable to scenarios of communication or sensing between an AP and an STA, between an AP and an AP, or between an STA and an STA in a WLAN. The embodiments of this application do not limit this. Optionally, an AP can communicate or sense with a single STA, or an AP can communicate or sense with multiple STAs simultaneously. Specifically, the communication or sensing between an AP and multiple STAs can be further divided into a downlink transmission in which the AP simultaneously sends signals to multiple STAs, and an uplink transmission in which multiple STAs send signals to the AP. Among them, between an AP and an STA, between an AP and an AP, and between an STA and an STA, the WLAN communication protocol can be supported. This communication protocol can include protocols in the IEEE802.11 series, such as being applicable to the 802.11bn protocol, and of course, it is also applicable to protocols after 802.11bn.

[0222] Figure 2a It is a schematic diagram of the architecture of a communication system provided by the embodiments of this application. This communication system can include one or more APs and one or more STAs. Figure 2aTwo access points such as AP1 and AP2, and three stations such as STA1, STA2, and STA3 are shown. As an example, the method provided by the embodiments of the present application can be applied to data communication or sensing between an AP and one or more STAs, such as Figure 2a the communication between AP1 and STA1 as shown, and also such as Figure 2b the communication between the AP and the STA as shown, and also such as Figure 2a the communication, sensing, or energy transfer between AP1 and STA1 and STA2 as shown, and also such as Figure 2c the communication, sensing, or energy transfer between the AP and STA1, STA2, and STA3 as shown. As another example, the method provided by the embodiments of the present application can be applied to communication between APs, such as Figure 2a the communication or sensing between AP1 and AP2 as shown. As yet another example, the method provided by the embodiments of the present application can be applied to communication or sensing between STAs, such as Figure 2a the communication or sensing between STA2 and STA3 as shown.

[0223] Figure 2a to Figure 2c Taking the STA as a mobile phone and the AP as a router as an example does not represent a limitation on the types of APs and STAs in the embodiments of the present application. At the same time, Figure 2a to Figure 2c the number of APs and STAs shown is only an example, and in specific implementations, the number of such APs or STAs can be more or less, and the embodiments of the present application do not make any limitations in this regard.

[0224] From different perspectives of transmitting signals and receiving signals, the first communication device shown below can be understood as the communication device that transmits signals, and the second communication device can be understood as the communication device that receives signals. Alternatively, the first communication device can also be referred to as the transmitting end, and the second communication device can also be referred to as the receiving end. In the embodiments of the present application, the signal can be an encoded sequence or a signal obtained by processing the encoded sequence.

[0225] From the perspective of different devices, as an example, the first communication device and the second communication device can be Wi-Fi chips, functional modules, processing systems, etc. provided in different Wi-Fi devices. As another example, the first communication device can be an AP, and the second communication device can be a non-AP STA. As yet another example, both the first communication device and the second communication device can be non-AP STAs or both can be APs. As yet another example, the first communication device can be a non-AP STA, and the second communication device can be an AP. As yet another example, at least one of the first communication device and the second communication device can be a multi-link device (MLD), etc., and the embodiments of the present application will not list them one by one. Exemplarily, a multi-link device (MLD) refers to a device that simultaneously has multiple stations (such as an AP or a non-AP STA), each working on a different frequency band or channel. A multi-link device includes multiple subordinate stations, and the subordinate stations can be physical stations or logical stations. Each station can work on one link, one frequency band, one channel, etc. The above-mentioned subordinate stations can be APs or non-AP STAs. A multi-link device (such as a non-AP MLD or an AP MLD) can be a communication device with wireless communication capabilities. This communication device can be a complete device, or it can be a chip, a processing system, a module, etc. installed in a complete device. The device installed with these chips, processing systems, or modules can, under the control of these chips, processing systems, or modules, implement the methods and functions of the embodiments of the present application. A multi-link device can implement wireless communication by following the 802.11 series of protocols, thereby realizing communication with other devices. The other devices shown here can be multi-link devices or can be non-multi-link devices. The frequency bands on which a multi-link device works can include but are not limited to: sub1GHz, 2.4GHz, 5GHz, 6GHz, etc., and will not be listed one by one here.

[0226] The embodiments of the present application describe the methods provided by the embodiments of the present application from both sides of the first communication device and the second communication device. However, during the process of transmitting signals by the first communication device and the second communication device, the signal can also be forwarded by other devices, such as by a forwarding device to forward the signal between the first communication device and the second communication device. The embodiments of the present application do not limit other devices other than the first communication device and the second communication device.

[0227] The following introduces the methods involved in the embodiments of the present application.

[0228] Figure 3 It is a schematic flowchart of an encoding method and a decoding method provided by the embodiments of the present application. The descriptions of the first communication device, the second communication device, etc. can refer to the above, and will not be elaborated here. As Figure 3 As shown in the figure, the method includes:

[0229] 301. The first communication device obtains an information bit sequence.

[0230] The information bit sequence may be a bit sequence containing information volume. For example, the length of the information bit sequence is N2, or the number of bits in the information bit sequence is N2. N2 is a positive integer. The N2 bits may include K information bits or K data bits or K payload bits. K is a positive integer. N2 may be an integer greater than or equal to K. For example, when N2 is greater than K, the information bit sequence may further include (N2 - K) 0s. For the relevant description of the "0" shown here, reference can be made to the description of the shortening operation below, which will not be elaborated here first. Fig.18 For the description of the shortening operation in the following text, it will not be elaborated here first.

[0231] The value of the foregoing N2 may be related to the code length and the code rate. As the length of the encoded sequence in step 302 below is N1, then N2 = N1 * R, where R is the encoding code rate of the information bit sequence. The N1 shown here may also be referred to as the code length corresponding to the parity check matrix. N1 may also be understood as the original code length of a single LDPC codeword, and N2 may be understood as the original information bits of a single LDPC codeword.

[0232] In a possible implementation manner, Figure 3 the method shown may further include:

[0233] The first communication device obtains the code length N1.

[0234] As an example, N1 may be m times of 1296, where m is an integer greater than or equal to 2. For example, N1 = 1296 * 2 = 2592. Another example is N1 = 1296 * 3 = 3888, etc., which will not be listed one by one here.

[0235] As another example, N1 may be n times of 1944, where n is an integer greater than or equal to 2. For example, N1 = 1944 * 2 = 3888, or N1 = 1944 * 3 = 5832, etc., which will not be listed one by one here.

[0236] In a possible implementation manner, Figure 3 the method shown may further include:

[0237] The first communication device obtains the code rate R.

[0238] In a WLAN system, different code lengths and code rates can correspond to different parity check matrices. Therefore, before the first communication device performs LDPC encoding, the code rate R can also be obtained. After obtaining the code rate R, the first communication device can select a parity check matrix based on the code rate R and the code length N1. The code rate R can be determined based on the MCS selected by link adaptation. For example, the code rate R can be determined based on the current channel information. The specific determination method of the code rate R is not limited in the embodiments of the present application. As an example, the MCS can be sent by the AP. As another example, the MCS can be determined by the first communication device, etc. For example, the first communication device sends the MCS to the second communication device, and the second communication device receives the MCS and obtains the code rate R based on the MCS. Another example is that the second communication device sends the MCS to the first communication device, and the first communication device receives the MCS and obtains the code rate R based on the MCS. The specific interaction process of the MCS is not limited in the embodiments of the present application.

[0239] Exemplarily, R can be any one of the following: 1 / 2, 2 / 3, 3 / 4, 5 / 6. Of course, with the progress of the standard, subsequent values of R can also have other numerical values, which are not limited in the embodiments of the present application.

[0240] The embodiments of the present application do not limit the order of the first communication device obtaining the code length and the code rate. After the first communication device obtains the code length and the code rate, it can determine the matrix prototype of the corresponding parity check matrix based on the code length and the code rate. Similarly, the order of the first communication device obtaining the information bit sequence and the code length (or code rate) is not limited either.

[0241] 302. The first communication device performs LDPC encoding on the information bit sequence based on the parity check matrix to obtain an encoded sequence. The length of the encoded sequence is N1. For example, N1 is n times of 1944, and n is an integer greater than or equal to 2.

[0242] The encoded sequence can include K information bits and E parity bits. Or, the encoded sequence can be composed of an information bit sequence and a parity bit sequence. The length of the information bit sequence can be N2, and the length of the parity bit sequence can be E. N1 = N2 + E. The value of E is related to N1 and R. For example, if N1 = 3888 and R = 1 / 2, then E = 1944. Another example is that if N1 = 3888 and R = 2 / 3, then E = 3888 * 1 / 3 = 1296. Another example is that if N1 = 3888 and R = 3 / 4, then E = 3888 * 1 / 4 = 972. Another example is that if N1 = 3888 and R = 5 / 6, then E = 3888 * 1 / 6 = 648.

[0243] The following introduces the matrix prototype of the parity check matrix involved in the embodiments of the present application.

[0244] In the matrix prototype of the parity-check matrix shown below, "-1" represents the all-zero matrix of Z*Z, "0" represents the identity matrix of Z*Z, and non-zero elements represent the CPM of the identity matrix of Z*Z. Of course, "-1" in the matrix prototype can also be replaced by "-", which is not limited in this application. For the description of each parameter and the description of CPM, etc., reference can be made to the above, and details are not elaborated here. The "1" in Example 1 below, the "2" in Example 2, or the "3" in Example 3, etc. are for distinguishing different examples and facilitating subsequent reference.

[0245] As an example 1, the matrix prototype of the parity-check matrix can be as Figure 4a shown. The description of Figure 4b can be referred to below, and details are not elaborated here first.

[0246] As another example 2, the matrix prototype of the parity-check matrix can be as Figure 5a shown. The description of Figure 5b can be referred to below, and details are not elaborated here first.

[0247] As yet another example 3, the matrix prototype of the parity-check matrix can be as Figure 6a shown. The description of Figure 6b can be referred to below, and details are not elaborated here first.

[0248] For the parity-check matrix corresponding to the matrix prototypes shown in the above Examples 1 to 3, R can be equal to 1 / 2. At the same time, the R corresponding to the parity-check matrix is also equal to 1 / 2. Exemplarily, for the matrix prototypes shown in the above Examples 1 to 3, N1 corresponding to the parity-check matrix can be equal to 3888. At the same time, N1 corresponding to the parity-check matrix is also equal to 3888. And when the first communication device performs LDPC coding using the parity-check matrix corresponding to the matrix prototypes shown in Examples 1 to 3, the length of the encoded sequence obtained is 3888 bits.

[0249] Each non-negative integer (such as element i) in the matrix prototypes of the parity-check matrices shown in Examples 1 to 3 can be expanded into the CPM of the identity matrix of Z*Z. The element i in Examples 1 to 3 can be expanded into a CPM, for example, this CPM is obtained by circularly shifting the identity matrix to the right by i bits. For example, the element 0 in Examples 1 to 3 can be expanded into the 81*81 identity matrix, and for an element i greater than 0 (such as i > 0), an 81*81 CPM can be obtained by circularly shifting the identity matrix to the right by i bits. For example, the element "57" in the matrix prototype can be expanded into the CPM of the 81*81 identity matrix, and this CPM can be obtained by circularly shifting the 81*81 identity matrix to the right by 57 bits.

[0250] In the embodiments of the present application, the matrix prototype shown in Examples 1 to 3 includes 24 rows and 48 columns. Thus, the parity check matrix expanded based on the expansion factor Z can include 24 * 81 rows and 48 * 81 columns (i.e., 1944 rows and 3888 columns). Regarding how to expand the matrix prototype into a parity check matrix, reference can be made to Figure 1a or Figure 1b for description, or relevant standards or protocols, etc., which will not be elaborated here. The relevant description of the expansion factor Z here also applies to Examples 4 to 14 below and will not be repeated.

[0251] For ease of description, in the following, the first X columns in the matrix prototype of the parity check matrix are referred to as the matrix corresponding to the information bits, or the information bit part of the LDPC codeword, or the information bit part of the matrix prototype, etc., and the last Y columns in the matrix prototype of the parity check matrix are referred to as the matrix corresponding to the parity check bits, or the parity check square matrix, or the parity check bit part of the LDPC codeword, or the parity check bit part of the matrix prototype, etc. Both X and Y are positive integers. Exemplarily, X = 48 * R. Y = 48 * (1 - R). For the matrix prototype shown in Examples 1 to 3, X = 24 and Y = 24.

[0252] As an example, when K = 3888 * 1 / 2 = 1944, that is, when the information bit sequence includes 1944 information bits, the encoded sequence can include 1944 information bits and 1944 parity check bits.

[0253] As another example, when K is less than 1944, that is, when the number of information bits included in the information bit sequence is less than 1944, the encoded sequence can include K information bits and 1944 parity check bits. Although the encoded sequence includes K information bits and 1944 parity check bits, the length of the encoded sequence is N1. As shown Fig.18 below, since the number of information bits is less than 1944, before performing LDPC encoding, the first communication device can obtain the information bit sequence by filling in a certain number of 0s, and then delete these 0s after completing LDPC encoding. Exemplarily, the number of 0s can be equal to 1944 - K. The relevant description of the shortening operation can be referred to Fig.18 , which will not be elaborated here first.

[0254] As another example, when the number of information bits to be transmitted obtained before the first communication device acquires the information bit sequence is greater than 1944, the first communication device may perform sub - codeword processing on the information bits before LDPC encoding. For example, after sub - codeword processing, multiple codewords (or referred to as blocks or segments, etc.) can be obtained, and the number of information bits carried by each codeword can be less than or equal to 1944. For the specific description of sub - codeword processing, relevant standards or protocols, etc. can be referred to, and the embodiments of this application do not limit this. Of course, after the first communication device performs sub - codeword processing, it can also be combined with shortening operations, etc. The combination of the above - mentioned shortening operation and sub - codeword operation will not be elaborated here.

[0255] The relevant descriptions about the values of different Ks here also apply to Examples 4 to 14 below, and will not be repeated below.

[0256] As an example 4, the matrix prototype of the parity - check matrix can be as Figure 7a shown. The description about Figure 7b can be referred to below, and will not be elaborated here first.

[0257] As another example 5, the matrix prototype of the parity - check matrix can be as Figure 8a shown. The description about Figure 8b can be referred to below, and will not be elaborated here first.

[0258] As yet another example 6, the matrix prototype of the parity - check matrix can be as Figure 9a shown. The description about Figure 9b can be referred to below, and will not be elaborated here first.

[0259] For the matrix prototypes of the parity - check matrices shown in the above Examples 4 to 6, R can be equal to 2 / 3. At the same time, the R corresponding to the parity - check matrix is also equal to 2 / 3. Exemplarily, for the matrix prototypes of the parity - check matrices shown in the above Examples 4 to 6, N1 can be equal to 3888. At the same time, the N1 corresponding to the parity - check matrix is also equal to 3888. And the first communication device uses the parity - check matrix corresponding to the matrix prototype shown in Examples 4 to 6 for LDPC encoding, and the length of the encoded sequence obtained is 3888 bits.

[0260] For Examples 4 to 6, X = 48 * 2 / 3 = 32, Y = 48 * 1 / 3 = 16. The relevant descriptions about X and Y can be referred to the above Examples 1 to 3, and will not be elaborated here.

[0261] The descriptions about the expansion factor, CPM, and K can be referred to the above Examples 1 to 3, and will not be elaborated here.

[0262] As an example 7, the matrix prototype of the parity - check matrix can be as Fig.10a shown. The description about Fig.10bThe description can be referred to the following text and will not be elaborated here.

[0263] As another example 8, the matrix prototype of the parity-check matrix can be as Fig.11a shown. Regarding Fig.11b the description can be referred to the following text and will not be elaborated here.

[0264] As yet another example 9, the matrix prototype of the parity-check matrix can be as Fig.12a shown. Regarding Figure 12b the description can be referred to the following text and will not be elaborated here.

[0265] As yet another example 10, the matrix prototype of the parity-check matrix can be as Fig.13a shown. Regarding Fig.13b the description can be referred to the following text and will not be elaborated here.

[0266] For the matrix prototypes of the parity-check matrices shown in the above Examples 7 to 10, R can be equal to 3 / 4. At the same time, the R corresponding to the parity-check matrix is also equal to 3 / 4. Exemplarily, for the matrix prototypes of the parity-check matrices shown in the above Examples 7 to 10, N1 can be equal to 3888. At the same time, the N1 corresponding to the parity-check matrix is also equal to 3888. And the first communication device performs LDPC coding using the parity-check matrix corresponding to the matrix prototypes shown in Examples 7 to 10, and the length of the encoded sequence obtained is 3888 bits.

[0267] For Examples 7 to 10, X = 48 * 3 / 4 = 36, and Y = 48 * 1 / 4 = 12. The relevant descriptions of X and Y can be referred to the above Examples 1 to 3 and will not be elaborated here.

[0268] The descriptions of the expansion factor, CPM, and K can be referred to the above Examples 1 to 3 and will not be elaborated here.

[0269] As an example 11, the matrix prototype of the parity-check matrix can be as Fig.14a shown. Regarding Fig.14b the description can be referred to the following text and will not be elaborated here.

[0270] As another example 12, the matrix prototype of the parity-check matrix can be as Fig.15a shown. Regarding Fig.15b the description can be referred to the following text and will not be elaborated here.

[0271] As yet another example 13, the matrix prototype of the parity-check matrix can be as Fig.16a shown. Regarding Fig.16b the description can be referred to the following text and will not be elaborated here.

[0272] As yet another example 14, the matrix prototype of the parity-check matrix can be as Fig.17a as shown. Regarding Fig.17b the description of, reference can be made to the following text, which will not be elaborated here for the time being.

[0273] For the matrix prototype of the parity check matrix shown in the above Examples 11 to 14, R can be equal to 5 / 6. At the same time, the R corresponding to the parity check matrix is also equal to 5 / 6. Exemplarily, for the matrix prototype of the parity check matrix shown in the above Examples 11 to 14, N1 can be equal to 3888. At the same time, the N1 corresponding to the parity check matrix is also equal to 3888. And the first communication device uses the parity check matrix corresponding to the matrix prototype shown in Examples 7 to 10 for LDPC coding, and the length of the encoded sequence obtained is 3888 bits.

[0274] For Examples 11 to 14, X = 48 * 5 / 6 = 40, Y = 48 * 1 / 6 = 8. Regarding the relevant descriptions of X and Y, reference can be made to the above Examples 1 to 3, which will not be elaborated here.

[0275] Regarding the description of the expansion factor, CPM, and K, reference can be made to the above Examples 1 to 3, which will not be elaborated here.

[0276] The matrix prototypes of the parity check matrices shown in the above Examples 1 to 14 are only examples. The matrix prototypes of the parity check matrices shown in the embodiments of the present application can also obtain other matrix prototypes through the determination method shown below, which will not be listed one by one here.

[0277] 303. The first communication device outputs the encoded sequence.

[0278] Exemplarily, the first communication device can perform LDPC coding through an encoding module (such as an LDPC encoding module) to obtain the encoded sequence, and output the encoded sequence from the encoding module. Regarding the relevant description of the length of the encoded sequence, reference can be made to the above Step 301 or Step 302, which will not be elaborated here.

[0279] In a possible implementation manner, after the first communication device outputs the encoded sequence, it can also perform a shortening operation. The following is an example.

[0280] Generally speaking, the information bit sequence needs to be placed into an integer number of orthogonal frequency division multiplexing (OFDM) symbols after encoding, and at the same time, the encoded sequence also needs to be exactly placed into an integer number of LDPC codewords. Therefore, before the first communication device performs LDPC coding, the first communication device also needs to first determine the minimum number of OFDM symbols N SYM , and then based on N SYMCalculate the total number of coded bits N that can be stored in all OFDM symbols according to the current coding and modulation scheme (such as the modulation order indicated by MCS, etc.) TCB = N CBPS * N SYM , where N CBPS is the number of coded bits that can be stored in each OFDM symbol. Then, the first communication device can calculate the LDPC code length (i.e., the code length shown in the embodiments of the present application) and the required number of codewords N CW . Exemplarily, when there are not enough information bits (such as the case where K is less than 1944 shown in Examples 1 to 3 below) to fill the information bit part in the LDPC codeword, the first communication device can perform a shortening operation before LDPC coding (which can also be referred to as generating parity bits). The shortening operation refers to filling a certain number of 0s in the information bits before generating parity bits through LDPC coding, and then deleting these 0s after generating the parity bits by coding. Fig.18 is a partial schematic diagram of the shortening operation in LDPC coding provided by the embodiments of the present application. As Fig.18 shown, step 1801 indicates that the first communication device can obtain the payload bits to be coded (such as the K information bits shown in the embodiments of the present application). Step 1802 indicates that the first communication device can calculate the LDPC code length and the number of codewords, Fig.18 exemplarily shows three LDPC codewords. The length (i.e., the code length) of each LDPC codeword can be equal to the code length. Step 1803 indicates that the first communication device can perform a shortening operation on the information bits, Fig.18 shows the codeword containing the payload bits and shortening zero bits. Step 1804 indicates that the first communication device can generate parity bits using the payload bits and the shortening bits, Fig.18 shows the codeword containing the payload bits, shortening zero bits, and parity bits. Step 1805 indicates that the first communication device discards these shortening bits, Fig.18 shows the codeword containing the data bits and parity bits. The above descriptions regarding the shortening operation and the like are only examples, and the relevant descriptions regarding the shortening operation and the like can also refer to relevant standards or protocols, etc., and the embodiments of the present application do not limit this.

[0281] 304. The first communication device sends a signal corresponding to the encoded sequence, and the second communication device receives the signal.

[0282] The signal corresponding to the encoded sequence mentioned above refers to the processed signal transmitted by the first communication device through the channel after the encoded sequence is output from the encoding module and then further processed.

[0283] Exemplarily, the first communication device may perform rate matching on the encoded sequence, and the rate matching method may include puncturing, repetition, shortening. For example, the first communication device may puncture the parity bits in the encoded sequence to obtain a higher code rate or a shorter code length, etc. Exemplarily, the first communication device may also perform at least one of the following processes on the encoded sequence: stream parsing, constellation mapping, LDPC subcarrier mapping, stream cyclic shift, space and frequency mapping, inverse discrete Fourier transform (IDFT), inserting a cyclic prefix, and windowing. Exemplarily, after receiving the signal transmitted through the channel, the second communication device may perform corresponding processing on the signal. For example, before obtaining the information to be decoded, the second communication device may perform at least one of the following processes: removing the cyclic prefix, discrete Fourier transform (DFT), space and frequency demapping, deinterleaving, and demodulating the constellation.

[0284] For other processing of the encoded sequence by the first communication device and the corresponding processing before the second communication device obtains the information to be decoded, reference may also be made to relevant standards or protocols, etc., and the embodiments of the present application do not limit this.

[0285] 305. The second communication device performs LDPC decoding on the information to be decoded based on the parity-check matrix to obtain an information bit sequence.

[0286] The length of the information to be decoded may be N1. For example, the information to be decoded may include bits or real numbers, etc., and the embodiments of the present application do not limit the specific content included in the information to be decoded. Exemplarily, before obtaining the information to be decoded, the second communication device may also supplement shortened bits, such as combining the code length and K to supplement shortened bits, or may also supplement punctured bits, etc., and the embodiments of the present application do not limit this.

[0287] Exemplarily, the decoding methods that the second communication device may adopt include, but are not limited to, hard decision decoding methods, soft decision decoding methods, or hybrid decoding methods. The embodiments of the present application will not elaborate on the specific decoding process.

[0288] Exemplarily, the second communication device may also adopt a similar Fig.18The method for determining the code length N1, etc., for the relevant description of how the second communication device obtains the code length N1 and the code rate R, refer to the above description of the first communication device, which will not be described in detail here. For the method for the first communication device to obtain N1 and R, and the method for the second communication device to obtain N1 and R, refer to relevant standards or protocols, etc., which are not limited in the embodiments of the present application.

[0289] In the embodiment of the present application, the above steps 302 to 303 can be implemented by the encoding module, and the above step 305 can be implemented by the decoding module. In the specific implementation, Figure 3 The method shown can also be divided into an encoding method or a decoding method. If the encoding method may include steps 302 to 303, or include steps 301 to 303, the first communication device may include an encoding module. If the decoding method may include step 305, the second communication device may include a decoding module. Optionally, in addition to the above-mentioned encoding module, the first communication device may also include an acquisition module, which may be used to obtain code length and code rate, etc. Optionally, the first communication device may also include a shortening module or a blocking module, etc. Optionally, in addition to the decoding module, the second communication device may also include an acquisition module, which may be used to obtain information to be decoded.

[0290] In an embodiment of the present application, the check matrix can be applied to an information bit sequence whose code length is n times of 1944, where n is an integer greater than or equal to 2, thereby improving the transmission reliability of the system and improving the decoding performance.

[0291] The following describes a method for determining a check matrix according to an embodiment of the present application.

[0292] The method for determining the check matrix shown in the embodiment of the present application is only an example. In a specific implementation, the determination method shown below can be defined by a standard. Alternatively, in a specific implementation, the communication parties may not perform the determination method shown below, such as the communication parties may save the matrix prototype of the check matrix, or save the extended indicator matrix (or referred to as the accompanying extended indicator matrix, etc.). The matrix prototypes of the 14 check matrices shown above can be obtained by the determination method shown below. Although the matrix prototypes of 14 check matrices are exemplarily shown above, the matrix prototypes of other check matrices determined by the determination method shown in the embodiment of the present application also belong to the protection scope of the embodiment of the present application.

[0293] The determination method shown below is illustrated by taking the base check matrix with a code length N0 = 1944 as an example. As shown in step 301 above, N1 can also be m times 1296, that is, according to the determination method shown below, a check matrix with a code length greater than 1944 can also be determined based on the check matrix corresponding to a code length of 1296. According to the determination method shown below, a check matrix with a code length greater than 1944 determined by using the check matrix corresponding to a code length of 1296 as the base check matrix also falls within the protection scope of the embodiments of the present application. The following takes the matrix prototype of the base check matrix being Figure 1a the matrix shown as an example to illustrate the determination method of the matrix prototype of the check matrix shown in the embodiments of the present application. Of course, the name of the base check matrix shown in the embodiments of the present application is only an example. For example, this base check matrix can also be called a reference check matrix or a benchmark check matrix or an original check matrix, etc.

[0294] To reuse the encoding and decoding architectures of the original WLAN LDPC codes as much as possible, the embodiments of the present application respectively expand the LDPC codes with different code rates and a code length of 1944 bits in the existing WLAN system as the base matrices, so as to respectively obtain the LDPC code check matrices with a code length of 3888 bits and corresponding code rates. Among them, in the matrix prototypes ( Figure 1a shown) of the four check matrices with the original code length of 1944 bits, the CPM size of each element is 81, and the CPM size of each element in the matrix prototype of the LDPC code check matrix with a code length of 3888 bits shown in the embodiments of the present application is also 81. However, the matrix prototype size of the check matrix shown in the embodiments of the present application is twice the matrix prototype size of the base check matrix. The following details are provided.

[0295] Explanation of the base check matrix:

[0296] The code length N0 of the base check matrix is 1944, and the code rates include: 1 / 2, 2 / 3, 3 / 4, 5 / 6. The expansion factor Z of the base check matrix is 1944 / 24 = 81.

[0297] When R = 1 / 2, the matrix prototype of the base check matrix is a matrix with a size of 12 * 24, that is, the matrix prototype of this base check matrix includes 12 rows and 24 columns. The base check matrix expanded based on this matrix prototype can include 972 rows and 1944 columns. X = 12, Y = 12.

[0298] When R = 2 / 3, the matrix prototype of the base check matrix is a matrix with a size of 8 * 24, that is, the matrix prototype of this base check matrix includes 8 rows and 24 columns. The base check matrix expanded based on this matrix prototype can include 648 rows and 1944 columns. X = 16, Y = 8.

[0299] When R = 3 / 4, the matrix prototype of the basic parity-check matrix is a matrix of size 6 * 24, that is, the matrix prototype of this basic parity-check matrix includes 6 rows and 24 columns. The extended basic parity-check matrix based on this matrix prototype can include 648 rows and 1944 columns. X = 18, Y = 6.

[0300] When R = 5 / 6, the matrix prototype of the basic parity-check matrix is a matrix of size 4 * 24, that is, the matrix prototype of this basic parity-check matrix includes 4 rows and 24 columns. The extended basic parity-check matrix based on this matrix prototype can include 324 rows and 1944 columns. X = 20, Y = 4.

[0301] Description of the parity-check matrix:

[0302] The code length N1 of the parity-check matrix is 3888, and the code rates include: 1 / 2, 2 / 3, 3 / 4, 5 / 6. The expansion factor Z of the parity-check matrix is 3888 / 48 = 81.

[0303] When R = 1 / 2, the matrix prototype of the parity-check matrix is a matrix of size 24 * 48, that is, the matrix prototype of this parity-check matrix includes 24 rows and 48 columns. The extended parity-check matrix based on this matrix prototype includes 1944 rows and 3888 columns. X = 24, Y = 24.

[0304] When R = 2 / 3, the matrix prototype of the parity-check matrix is a matrix of size 16 * 48, that is, the matrix prototype of this parity-check matrix includes 16 rows and 48 columns. The extended parity-check matrix based on this matrix prototype includes 1296 rows and 3888 columns. X = 32, Y = 16.

[0305] When R = 3 / 4, the matrix prototype of the parity-check matrix is a matrix of size 12 * 48, that is, the matrix prototype of this parity-check matrix includes 12 rows and 48 columns. The extended parity-check matrix based on this matrix prototype includes 972 rows and 3888 columns. X = 36, Y = 12.

[0306] When R = 5 / 6, the matrix prototype of the parity-check matrix is a matrix of size 8 * 48, that is, the matrix prototype of this parity-check matrix includes 8 rows and 48 columns. The extended parity-check matrix based on this matrix prototype includes 648 rows and 3888 columns. X = 40, Y = 8.

[0307] In the embodiments of the present application, the parity-check matrix can be obtained by positive diagonal expansion or anti-diagonal expansion of the element in the x-th row and y-th column in the matrix prototype of the basic parity-check matrix. The code length N0 corresponding to the basic parity-check matrix is less than or equal to 1944, and the code rate corresponding to the basic parity-check matrix is the same as the code rate corresponding to the parity-check matrix. The element in the x-th row and y-th column is greater than or equal to 0. By performing positive diagonal expansion or anti-diagonal expansion on each item in the basic parity-check matrix to obtain the parity-check matrix, each module in the LDPC encoding and decoding architecture with a code length of 1944 bits can be effectively reused. The following is a detailed description.

[0308] For example, if the element in the \(x\)-th row and \(y\)-th column of the matrix prototype of the basic parity-check matrix is \(i\), after positive diagonal expansion of \(i\), the matrix shown in Fig.19a can be obtained. After anti-diagonal expansion of \(i\), the matrix shown in Fig.19b can be obtained. \(i\) can be an integer greater than or equal to 0. Another example is that if the element in the \(x\)-th row and \(j\)-th column of the matrix prototype of the basic parity-check matrix is “-1” or “-”, the corresponding element in the parity-check matrix can still be “-1” or “-”. Thus, the element \(i\) in the matrix prototype of the basic parity-check matrix can be subjected to positive diagonal expansion or anti-diagonal expansion. For example, each element can be expanded into a \(2\times2\) square matrix, and the non-negative elements in the square matrix can represent the CPM of the \(Z\times Z\) identity matrix (e.g., 0 in the square matrix can represent the \(Z\times Z\) identity matrix, and elements greater than 0 can represent the CPM of the \(Z\times Z\) identity matrix). Fig.19a and Fig.19b what is not shown in the blank spaces in is “-1” (or “-”). The “-1” in the square matrix can represent the all-zero square matrix of \(Z\times Z\).

[0309] Taking (d) \(R = 5 / 6\) in Figure 1a as an example, for the basic parity-check matrix, \(Z = 81\), and the size of the matrix prototype of the basic parity-check matrix is 4 rows and 24 columns. After positive diagonal expansion or anti-diagonal expansion of the element \(i\) in the basic parity-check matrix, the \(Z\) of the parity-check matrix is still equal to 81, that is, the size of the expansion factor of the basic parity-check matrix remains unchanged. For example, when the element \(i\) is expanded into a \(2\times2\) square matrix, the size of the matrix prototype of the parity-check matrix is 8 rows and 48 columns, and the code rate of the parity-check matrix is still equal to 5 / 6. Thus, the code length can be equal to \(1944\times2 = 3888\). Of course, the expansion of the element \(i\) in the matrix prototype of the basic parity-check matrix shown in the embodiments of the present application into a \(2\times2\) square matrix is only an example. For example, the element \(i\) can also be expanded into a \(3\times3\) square matrix, or the element \(i\) can also be expanded into a \(4\times4\) square matrix, etc., which are not listed one by one here. At this time, the code length of the expanded parity-check matrix can be longer. For example, when the element \(i\) in the matrix prototype of the basic parity-check matrix is expanded into a \(3\times3\) square matrix, the corresponding code length of the parity-check matrix can be \(24\times3\times81 = 5382\). Another example is that when the element \(i\) in the matrix prototype of the basic parity-check matrix is expanded into a \(4\times4\) square matrix, the corresponding code length of the parity-check matrix can be \(24\times4\times81 = 7776\). These are not listed one by one here.

[0310] In the embodiments of the present application, the element i in the matrix prototype of the basic check matrix can be subjected to positive diagonal expansion or anti-diagonal expansion, which does not mean that each element in the matrix prototype of the basic check matrix is subjected to positive diagonal expansion or anti-diagonal expansion. Instead, the first part of the elements greater than or equal to 0 in the matrix prototype of the basic check matrix is subjected to positive diagonal expansion, and the second part of the elements greater than or equal to 0 is subjected to anti-diagonal expansion. The matrix corresponding to the information bits in the matrix prototype of the check matrix is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and y-th column in the matrix corresponding to the information bits in the matrix prototype of the basic check matrix. That is, the first part of the elements greater than or equal to 0 in the information bit part of the matrix prototype of the basic check matrix is subjected to positive diagonal expansion, and the second part of the elements greater than or equal to 0 is subjected to anti-diagonal expansion, and then the information bit part in the matrix prototype of the check matrix can be obtained.

[0311] Further, the first column and the second column in the matrix corresponding to the check bits in the matrix prototype of the check matrix are obtained by performing positive diagonal expansion or anti-diagonal expansion on both the first element and the last element in the first column in the matrix corresponding to the check bits in the matrix prototype of the basic check matrix. That is, by performing positive diagonal expansion or anti-diagonal expansion on both the first element (such as element 1) or the last element (such as element 1) in the first column of the check bit part in the matrix prototype of the basic check matrix, the first column and the second column in the check bit part in the matrix prototype of the check matrix can be obtained. That is, the expansion methods of the first element and the last element in the first column of the last Y columns in the matrix prototype of the basic check matrix are the same.

[0312] For example, after both the element in the first row and the first column and the element in the last row and the first column of the last Y columns in the matrix prototype of the basic check matrix are subjected to positive diagonal expansion (or both are subjected to anti-diagonal expansion), the element in the first row and the first column, the element in the second row and the first column, the element in the first row and the second column, the element in the second row and the second column, as well as the element in the last row and the first column, the element in the penultimate row and the first column, the element in the last row and the second column, and the element in the penultimate row and the second column in the last Y columns in the matrix prototype of the check matrix are obtained. Exemplarily, the element in the first row and the first column and the element in the last row and the first column in the last Y columns in the expansion indication matrix are the same. Fig.13b For example, Y = 6, that is, the element in the first row and the first column of the last 6 columns in the expansion indication matrix is 0, and the element in the last row and the first column is also 0, as Fig.13c shown. Similarly, Fig.14b in the expansion indication matrix, the element in the first row and the first column of the last column is 1, and the element in the last row and the first column is also 1. And so on, which will not be elaborated one by one here.

[0313] Exemplarily, the element 0 in the first column of the parity bit part in the matrix prototype of the basic parity check matrix can be obtained by positive diagonal extension or anti-diagonal extension to get the element at the corresponding position in the matrix prototype of the parity check matrix.

[0314] Generally speaking, the first column of the parity bit part in the matrix prototype of the basic parity check matrix is in the "1-0-1" structure, that is, the first row and the last row from top to bottom in this column are both 1, and the rest of the rows are 0. Therefore, to maintain the fast and efficient encoding algorithm of the original WLAN LDPC, the embodiments of this application maintain a similar structure in the parity bit part. For example, the first row element and the last row element in the last Y columns of the extension indication matrix are both 0 or both 1. Thus, the fast and efficient encoding algorithm of the LDPC code can be ensured.

[0315] Furthermore, the elements in the matrix corresponding to the parity bits in the matrix prototype of the parity check matrix except for the first column and the second column are: obtained by positive diagonal extension of the elements 0 in the matrix corresponding to the parity bits in the matrix prototype of the basic parity check matrix except for the first column. The elements (such as 0) except for "-1" (or "-") in the columns of the parity bit part in the matrix prototype of the basic parity check matrix except for the first column can all be positively diagonally extended. For example Figure 1a in the matrix prototype, the element 0 in the parity bit part is positively diagonally extended, and the element 1 in the first column of this parity bit part is also positively diagonally extended (or anti-diagonally extended), so that the parity bit part in the matrix prototype of the parity check matrix can be obtained.

[0316] That is to say, the first column and the second column in the parity bit part in the matrix prototype of the parity check matrix can be obtained by positive diagonal extension or anti-diagonal extension of the first element and the last element in the first column of the parity bit part in the matrix prototype of the basic parity check matrix, and the remaining columns in the parity bit part in the matrix prototype of this parity check matrix can be obtained by positive diagonal extension of the elements 0 in the other columns of the parity bit part in the matrix prototype of the basic parity check matrix except for the first column. Thus, as an example, the extension methods of the elements in the parity bit part in the matrix prototype of the basic parity check matrix may all be the same. For example Figure 4a as shown, the parity bit part in the matrix prototype of the parity check matrix can be obtained by positive diagonal extension of all the elements in the parity bit part in the matrix prototype of the basic parity check matrix. As another example, the extension methods of the elements in the parity bit part in the matrix prototype of the basic parity check matrix may not be completely the same. For example Figure 8bAs shown, the parity bit part in the matrix prototype of the parity check matrix can be obtained by performing anti-diagonal expansion based on the first and last elements in the first column of the parity bit part in the matrix prototype of the basic parity check matrix, and performing positive diagonal expansion on all elements 0 in the parity bit part except the first and last elements in the first column. Details are not listed one by one here.

[0317] The matrix prototype of the parity check matrix shown above can be obtained by performing corresponding expansion on the elements in the matrix prototype of the basic parity check matrix. The expansion method of each element shown above can also be represented by an expansion indication matrix. Exemplarily, the matrix prototype of the parity check matrix can be determined based on the matrix prototype of the basic parity check matrix and the expansion indication matrix. Or, the relationship between the matrix prototype of the basic parity check matrix and the matrix prototype of the parity check matrix can be represented by the expansion indication matrix.

[0318] The size of this expansion indication matrix is the same as the size of the matrix prototype of the basic parity check matrix. For example, the element in the x-th row and y-th column of this expansion indication matrix is used to indicate that the square matrix at the corresponding position in the matrix prototype of the parity check matrix is obtained by performing positive diagonal expansion or anti-diagonal expansion on the element in the x-th row and y-th column of the matrix prototype of the basic parity check matrix. Another example is that the element in the x-th row and y-th column of this expansion indication matrix can be used to indicate the following operations on the x-th row and j-th column of the matrix prototype of the basic parity check matrix to obtain the element at the corresponding position in the matrix prototype of the parity check matrix: positive diagonal expansion, anti-diagonal expansion, remain unchanged.

[0319] For example, if the element in the x-th row and j-th column of the expansion indication matrix is element j, then this element j can be equal to 0, or 1, or "-1" (which can also be replaced by "-"). Among them, j = 0 can indicate that the element at the corresponding position in the matrix prototype of the parity check matrix is obtained by performing positive diagonal expansion on the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix. j = 1 can indicate that the element at the corresponding position in the matrix prototype of the parity check matrix is obtained by performing anti-diagonal expansion on the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix. j = -1 can indicate that the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix (i.e., "-1" or "-") is expanded into a 2*2 all-zero square matrix, or j = -1 can indicate that the element at the corresponding position in the matrix prototype of the parity check matrix is still the same as the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix, i.e., "-1" (or understood as no expansion, or understood as remaining unchanged). The relationship between the values and meanings of j shown here is only an example. In specific implementations, other values can also be used to represent the above meanings, and details are not listed one by one here.

[0320] Regarding the code rate R = 1 / 2, the following explanations are provided:

[0321] As an example, Figure 4a The matrix prototype of the parity-check matrix shown can be based on Figure 4b the extended indication matrix shown and Figure 1a the matrix (a) shown (i.e., R = 1 / 2).

[0322] For example, Figure 1a the element in the first row and first column of the matrix (a) shown is 57, Figure 4b and the element in the first row and first column of the extended indication matrix shown is 1. This means that the elements in the first row and first column, first row and second column, second row and first column, and second row and second column of the matrix prototype of the parity-check matrix are obtained by anti-diagonal extension based on the element 57. That is, the element in the first row and first column of the matrix prototype of the parity-check matrix is "-1", the element in the first row and second column is 57, the element in the second row and first column is 57, and the element in the second row and second column is "-1".

[0323] Another example, Figure 1a the element in the first row and second column of the matrix (a) shown is "-1", then Figure 4b the element in the first row and second column of the extended indication matrix shown is still "-1". Then, the elements in the first row and third column, first row and fourth column, second row and third column, and second row and fourth column of the matrix prototype of the parity-check matrix remain unchanged, that is, they are still "-1".

[0324] Another example, Figure 1a the element in the third row and first column of the matrix (a) shown is 30, Figure 4b and the element in the third row and first column of the extended indication matrix shown is 0. This means that the elements in the fifth row and first column, fifth row and second column, sixth row and first column, and sixth row and second column of the matrix prototype of the parity-check matrix are obtained by positive diagonal extension based on the element 30. That is, the element in the fifth row and first column of the matrix prototype of the parity-check matrix is 30, the element in the fifth row and second column is "-1", the element in the sixth row and first column is "-1", and the element in the sixth row and second column is 30.

[0325] Regarding the descriptions of the other elements in the matrix prototype of the basic parity-check matrix, the other elements in the extended indication matrix, and the elements in the matrix prototype of the parity-check matrix, they are not listed one by one here.

[0326] As another example, Figure 5a the matrix prototype of the parity-check matrix shown can be based on Figure 5b the extended indication matrix shown and Figure 1a the matrix (a) shown (i.e., R = 1 / 2).

[0327] As yet another example, Figure 6a the matrix prototype of the parity-check matrix shown can be based on Figure 6b the extended indication matrix shown and Figure 1a the matrix (a) shown (i.e., R = 1 / 2).

[0328] For the code rate R = 2 / 3, the following explanations are given:

[0329] As an example, Figure 7a the matrix prototype of the parity-check matrix shown can be determined based on Figure 7b the extended indication matrix shown and Figure 1a the matrix (b) shown (i.e., R = 2 / 3).

[0330] As another example, Figure 8a the matrix prototype of the parity-check matrix shown can be determined based on Figure 8b the extended indication matrix shown and Figure 1a the matrix (b) shown (i.e., R = 2 / 3).

[0331] As yet another example, Figure 9a the matrix prototype of the parity-check matrix shown can be determined based on Figure 9b the extended indication matrix shown and Figure 1a the matrix (b) shown (i.e., R = 2 / 3).

[0332] For the code rate R = 3 / 4, the following explanations are given:

[0333] As an example, Fig.10a the matrix prototype of the parity-check matrix shown can be determined based on Fig.10b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0334] As another example, Fig.11a the matrix prototype of the parity-check matrix shown can be determined based on Fig.11b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0335] As yet another example, Fig.12a the matrix prototype of the parity-check matrix shown can be determined based on Figure 12b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0336] As yet another example, Fig.13a the matrix prototype of the parity-check matrix shown can be determined based on Fig.13b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0337] For a code rate R = 5 / 6, the following explanations are provided:

[0338] As an example, Fig.14a the matrix prototype of the parity-check matrix shown can be based on Fig.14b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0339] As another example, Fig.15a the matrix prototype of the parity-check matrix shown can be based on Fig.15b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0340] As yet another example, Fig.16a the matrix prototype of the parity-check matrix shown can be based on Fig.16b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0341] As yet another example, Fig.17a the matrix prototype of the parity-check matrix shown can be based on Fig.17b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0342] As an example, both communication parties (such as the first communication device and the second communication device) store each element in the matrix prototype of the parity-check matrix. For example, by storing each element in the matrix prototype of the parity-check matrix, when the code length is 3888 bits, both communication parties can directly obtain the parity-check matrix based on the elements they store and the extension factor. Another example is that when the code length is 1944 bits, both communication parties can obtain the basic parity-check matrix based on the above extension method. That is to say, by storing each element in the matrix prototype of the parity-check matrix (or called each CPM coefficient or cyclic shift value, etc.), both communication parties can obtain LDPC codes with two code lengths, saving storage space. As another example, both communication parties can also store the basic parity-check matrix and the extended indication matrix. For example, when the code length is 3888 bits, both communication parties can obtain the matrix prototype of the parity-check matrix based on the matrix prototype of the basic parity-check matrix and the extended indication matrix.

[0343] The above indicates the expansion method of each element in the matrix prototype of the base parity-check matrix in the form of a matrix. However, the matrix form shown above is only an example. In specific implementations, other deformations can also be made to the above expansion indication matrix. For example, the expansion method of each element in the matrix prototype of the base parity-check matrix can be indicated in the form of a bitmap. For example, the length of the bitmap can be equal to the number of elements greater than or equal to 0 in the matrix prototype of the base parity-check matrix. Another example is to indicate the expansion method of each element in the matrix prototype of the base parity-check matrix in the form of a table, etc., which will not be listed one by one here.

[0344] The matrix prototype (or parity-check matrix) of the parity-check matrix obtained based on the above determination method is within the protection scope of the embodiments of the present application. In addition, combined with the above method and the tree structure, parity-check matrices with better decoding performance can be effectively screened out, further improving the decoding performance of the parity-check matrix.

[0345] According to the expansion methods of positive diagonal expansion or anti-diagonal expansion, each element in the matrix prototype of the base parity-check matrix can select one of the above two expansion methods, that is, positive diagonal (Opt A) or anti-diagonal (Opt B). Fig.20a The small squares in it can represent the element values in the matrix prototype of the base parity-check matrix. Option A (Opt A) can represent the square matrix after positive diagonal expansion of the element value, and Option B (Opt B) represents the square matrix after anti-diagonal expansion of the element value.

[0346] Specifically, when selecting OptA or OptB for the above element value, the nodes to be selected can be expanded according to the tree, and the expansion method with a deeper depth can be selected. The specific tree expansion schematic diagram is as Fig.20b shown. The circles represent variable nodes, and the squares represent check nodes. The deeper the depth of the expanded tree, the fewer short cycles the corresponding matrix contains. Short cycles have a negative impact on the decoding performance. When each variable node is expanded according to the tree, the corresponding depths of each Opt A or Opt B in the corresponding matrix may be different, and the loop structures caused by them in the overall factor graph (tanner graph) of the parity-check matrix will also be different. Therefore, the embodiments of the present application comprehensively consider the loop structures of the matrix locally and globally, and design all non-zero elements according to the tree expansion, so as to ensure that the factor graph corresponding to the parity-check matrix has a good loop structure.

[0347] Combined with the determination method and the tree structure shown above, it can effectively ensure that the parity-check matrix provided by the embodiments of the present application can maintain the fast and efficient encoding method of the original WLAN LDPC code and improve the decoding performance.

[0348] The following introduces the simulation results of the parity-check matrix provided by the embodiments of the present application.

[0349] The performance comparison between the above parity-check matrix and the base parity-check matrix is given below respectively. Figure 21a to Figure 21d In [figure], the abscissa represents the signal-to-noise ratio (SNR) with the unit of dB, and the ordinate represents the block error rate (BLER). The decoding method used is the soft-decision decoding method, such as the belief propagation (BP) algorithm, and the number of decoding iterations is 8 times. Figure 21a to Figure 21d The serial numbers 1 to 4 in [figure] are set for the convenience of distinguishing different curves and should not be construed as limitations on the embodiments of the present application.

[0350] Fig.21a What is shown is the performance comparison between the parity-check matrix with a code length of 3888 and the base parity-check matrix with a code length of 1944. R = 1 / 2.

[0351] Figure 21b What is shown is the performance comparison between the parity-check matrix with a code length of 3888 and the base parity-check matrix with a code length of 1944. R = 2 / 3.

[0352] Fig.21c What is shown is the performance comparison between the parity-check matrix with a code length of 3888 and the base parity-check matrix with a code length of 1944. R = 3 / 4

[0353] Fig.21d What is shown is the performance comparison between the parity-check matrix with a code length of 3888 and the base parity-check matrix with a code length of 1944. R = 5 / 6.

[0354] It can be seen from the above that at the same SNR, the BLER corresponding to the parity-check matrix is lower, so the decoding performance of the parity-check matrix is better. Therefore, each parity-check matrix provided by the embodiments of the present application can obtain a significant improvement in decoding performance and can achieve a good compromise between decoding performance and complexity.

[0355] In the embodiments of the present application, in the matrix prototype of the parity-check matrix of the designed LDPC code, the influence of columns with different column weights participating in small loops (or also called short loops) on the final performance is different. For example, if small loops are formed between columns with small column weights (such as column weight 2 or 3), the deterioration of performance is more serious than that of small loops formed between columns with large column weights. The small column weight and the large column weight are relative. For example, the small column weight refers to the column weight less than or equal to the first value, and the large column weight refers to the column weight greater than or equal to the second value. The first value can be equal to the second value, or the first value can be less than the second value. The specific values of the first value and the second value are not limited in the embodiments of the present application.

[0356] Therefore, it is possible to preferentially avoid small loops between columns with small column weights. In the embodiments of the present application, the basic parity-check matrix can be extended and designed according to different column weights; alternatively, the basic parity-check matrix can be extended and designed according to different column-weight groups. Or rather, the regions with the same column weight in the basic parity-check matrix can be preferentially extended and designed, that is, the extended indication matrix corresponding to the regions with the same column weight is preferentially designed. The extended indication matrix designed in the embodiments of the present application can be designed according to different column weights or according to different column-weight groups.

[0357] Fig.25 It is a schematic diagram of the matrix prototype grouping design of the basic parity-check matrix provided by the embodiments of the present application. Fig.25 Exemplarily, when the code rate R = 5 / 6 and N = 1944, a schematic diagram of the matrix prototype grouping design of the basic parity-check matrix is shown. As Fig.25 shown, when the code rate R = 5 / 6 and N = 1944, the design of the matrix prototype of the LDPC basic parity-check matrix can be divided into 3 groups according to the column weight, and then each group is optimized and designed in turn according to the priority. For example, first, for the region corresponding to the highest-priority short-loop optimization, the extended indication matrix corresponding to this region (such as the column weight is 2) can be designed first to preferentially ensure the performance of this region. Second, for the region corresponding to the second-highest-priority short-loop optimization, the extended indication matrix corresponding to this region (such as the column weight is 3) can be optimized. Finally, the region corresponding to the low-priority short-loop optimization (such as the column weight is 4) is optimized. Fig.25 Exemplarily, the case of R = 5 / 6 is shown. For other code rates, the extended indication matrix can also be designed according to the column weight. The method of grouping or optimizing by region according to the column weight is similar to the above example, and each grouped region can also be designed according to the short-loop optimization priority, which will not be listed one by one here. The above column weight is shown by taking the number of non "-1" in a column as an example.

[0358] In the method of designing the LDPC parity-check matrix or the extended indication matrix shown above, the extended indication matrix corresponding to the columns with the same column weight can be within the protection scope of the embodiments of the present application. That is to say, according to the above design method, the extended indication matrix corresponding to one or more grouped regions is also within the protection scope of the embodiments of the present application, and this principle applies to all embodiments of the present application. The extended indication matrix shown in the embodiments of the present application can also be called an extended pattern. For example, Fig.25For example, the extended indication matrix corresponding to the above-mentioned highest-priority short-loop optimization (or the first-part extended indication matrix) and the matrix prototype of the parity-check matrix (or the first-part matrix prototype) may fall within the protection scope of the embodiments of the present application. The extended indication matrix corresponding to the above-mentioned second-highest-priority short-loop optimization (or the second-part extended indication matrix) and the matrix prototype of the parity-check matrix (or the second-part matrix prototype) also fall within the protection scope of the embodiments of the present application. The extended indication matrix corresponding to the above-mentioned low-priority short-loop optimization (or the third-part extended indication matrix) and the matrix prototype of the parity-check matrix (or the third-part matrix prototype) also fall within the protection scope of the embodiments of the present application. Similarly, for Fig.25 the extended indication matrix corresponding to all the regions shown and the matrix prototype of the parity-check matrix also fall within the protection scope of the embodiments of the present application.

[0359] In the extended indication matrix, except for the matrix corresponding to the parity-check square matrix, taking the inverse of all columns or part of the columns of the remaining matrices also falls within the protection scope of the embodiments of the present application. That is to say, in the extended indication matrix, taking the inverse of all columns or part of the columns of the matrix corresponding to the information-bit part also falls within the protection scope of the embodiments of the present application. For the sake of convenience of description, the remaining matrix region in the extended indication matrix except for the matrix corresponding to the parity-check square matrix is called the information-part matrix or the system-part matrix. Due to the structural characteristics of the matrix prototype of the 11n LDPC parity-check matrix, the structure of its parity-check square matrix is fixed and includes a double-diagonal structure. Therefore, for fast encoding, the matrix corresponding to the parity-check square matrix in the extended indication matrix may not be inverted. Regarding whether to invert the matrix corresponding to the parity-check square matrix, the embodiments of the present application do not make any limitations.

[0360] In the embodiments of the present application, the matrix obtained by performing column permutation or row permutation on the matrix prototype of the parity-check matrix also falls within the protection scope of the embodiments of the present application. That is, after performing column permutation or row permutation on the matrix prototype of each parity-check matrix shown in the present application, or performing row permutation and column permutation simultaneously, the matrix prototype of the parity-check matrix can also be obtained. The performance of the matrix prototype before permutation is the same as that after permutation. The method for determining the extended indication matrix or the method for determining the matrix prototype of the parity-check matrix shown in the embodiments of the present application also fall within the protection scope of the embodiments of the present application. Due to the above-mentioned changes in the matrix prototype of the parity-check matrix, and since each matrix prototype is listed one by one in the embodiments of the present application, all or part of the deformations of the above-mentioned various LDPC matrices are also within the protection scope of the present application.

[0361] Fig.26a and Figure 26b are schematic diagrams of the extended indication matrix provided by the embodiments of the present application. For Fig.25The matrix prototype of the LDPC check matrix with code rate R = 5 / 6 and N = 1944 shown in the figure. The embodiments of the present application show an extended indication matrix.

[0362] Figure 26b The extended indication matrix shown in the figure is obtained by taking the inverse of the information part matrix of Fig.26a the extended indication matrix shown in the figure. The specific way of taking the inverse is as follows: in the information part matrix of the extended indication matrix, "1" is inverted to "0", "0" is inverted to "1", and "-1" remains unchanged. At the same time, the rightmost 4x4 check matrix part remains unchanged. Since after taking the inverse of the information part matrix according to the above method, the loop length distribution of each variable node corresponding to the extended check matrix is the same as that of the extended check matrix before taking the inverse, these two extension methods can be considered equivalent under the principle of optimizing the loop length distribution.

[0363] That is to say, for all the matrix prototypes of the extended indication matrices or check matrices, or the check matrices given in the embodiments of the present application, the extended indication matrix obtained by taking the inverse of the corresponding information part matrix (such as "1" being inverted to "0", "0" being inverted to "1", and "-1" remaining unchanged), and the matrix prototype of the check matrix obtained according to this extended indication matrix, and the check matrix obtained according to this extended indication matrix all fall within the protection scope of the embodiments of the present application.

[0364] In addition to the matrix prototypes of the respective check matrices and the extended indication matrices shown above, the embodiments of the present application also provide the following matrices. The R corresponding to the matrix prototype of the check matrix shown below is the same as the R corresponding to the check matrix. Exemplarily, N1 corresponding to the matrix prototype of the check matrix shown below may be equal to 3888. At the same time, N1 corresponding to the check matrix is also equal to 3888. The descriptions of R or N1, etc. can refer to the above, and will not be elaborated here.

[0365] Regarding the code rate R = 1 / 2, the following explanations are provided:

[0366] As an example, the matrix prototype of the check matrix can be as Fig.27a shown in the figure. Fig.27a The matrix prototype of the check matrix shown in the figure can be based on Figure 27b the extended indication matrix shown in the figure and Figure 1a the matrix (a) shown in the figure (i.e., R = 1 / 2).

[0367] As another example, the matrix prototype of the check matrix can be as Fig.28a shown in the figure. Fig.28a The matrix prototype of the check matrix shown in the figure can be based on Fig.28b the extended indication matrix shown in the figure and Figure 1a the matrix (a) shown in the figure (i.e., R = 1 / 2).

[0368] Fig.28b The extended indication matrix shown is Figure 27b an extended indication matrix obtained by inverting the information part matrix in the extended indication matrix shown. Figure 27b and Fig.28b exemplarily shows the extended indication matrix after inverting the information part matrix in the extended indication matrix, Fig.27a and Fig.28a exemplarily shows the matrix prototype of the parity-check matrix corresponding to the inverted extended indication matrix. For the sake of brevity, the extended indication matrix after inverting the information part matrix in the extended indication matrix will not be shown hereinafter.

[0369] As another example, the matrix prototype of the parity-check matrix can be as Fig.29a shown. Fig.29a The matrix prototype of the parity-check matrix shown can be based on Fig.29b the extended indication matrix shown and Figure 1a the matrix (a) (i.e., R = 1 / 2) shown.

[0370] For the code rate R = 2 / 3, the following description is given:

[0371] As an example, the matrix prototype of the parity-check matrix can be as Fig.30a shown. Fig.30a The matrix prototype of the parity-check matrix shown can be based on Fig.30b the extended indication matrix shown and Figure 1a the matrix (b) (i.e., R = 2 / 3) shown. As another example, the matrix prototype of the parity-check matrix can be as Fig.31a shown. Fig.31a The matrix prototype of the parity-check matrix shown can be based on Fig.31b the extended indication matrix shown and Figure 1a the matrix (b) (i.e., R = 2 / 3) shown.

[0372] As another example, the matrix prototype of the parity-check matrix can be as Fig.32a shown. Fig.32a The matrix prototype of the parity-check matrix shown can be based on Figure 32b the extended indication matrix shown and Figure 1a the matrix (b) (i.e., R = 2 / 3) shown.

[0373] For the code rate R = 3 / 4, the following description is given:

[0374] As an example, the matrix prototype of the parity-check matrix can be as Fig.33a shown. Figure 33a The matrix prototype of the parity-check matrix shown can be based on Figure 33bThe extended indication matrix shown and Figure 1a determined by the matrix (c) shown (i.e., R = 3 / 4).

[0375] As another example, the matrix prototype of the parity-check matrix can be as Figure 34a shown. Figure 34a The matrix prototype of the parity-check matrix shown can be based on Figure 34b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0376] As yet another example, the matrix prototype of the parity-check matrix can be as Figure 35a shown. Figure 35a The matrix prototype of the parity-check matrix shown can be based on Figure 35b the extended indication matrix shown and Figure 1a the matrix (c) shown (i.e., R = 3 / 4).

[0377] Regarding the code rate R = 5 / 6, the following description is provided:

[0378] As an example, the matrix prototype of the parity-check matrix can be as Figure 36a shown. Figure 36a The matrix prototype of the parity-check matrix shown can be based on Figure 36b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0379] As another example, the matrix prototype of the parity-check matrix can be as Figure 37a shown. Figure 37a The matrix prototype of the parity-check matrix shown can be based on Figure 37b the extended indication matrix shown and Figure 1a the matrix (d) shown (i.e., R = 5 / 6).

[0380] The communication device provided in the embodiments of the present application will be introduced below.

[0381] The present application divides the communication device into functional modules according to the above method embodiments. For example, each functional module can be corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the present application is illustrative, only a logical function division, and there can be other division methods in actual implementation. The communication device of the embodiments of the present application will be described in detail below in combination with Figures 22 to 24 The communication device of the embodiments of the present application will be described in detail.

[0382] Figure 22It is a schematic structural diagram of a communication device provided by an embodiment of the present application. As Figure 22 shown, the communication device includes a processing module 2201 and a transceiver module 2202. The transceiver module 2202 can implement corresponding communication functions, and the processing module 2201 is used to implement corresponding processing functions. For example, the transceiver module 2202 can also be referred to as an interface, a communication interface, a communication module, etc.

[0383] In some embodiments of the present application, the communication device can be used to perform the actions performed by the first communication device in the above method embodiments. At this time, the first communication device can be the Wi-Fi device itself or a chip or functional module that can be configured in the device, etc. The transceiver module 2202 is used to perform the operations related to the transceiver of the first communication device in the above method embodiments, and the processing module 2201 is used to perform the operations related to the processing of the first communication device in the above method embodiments.

[0384] Exemplarily, the processing module 2201 can be used to obtain an information bit sequence and perform LDPC encoding on the information bit sequence based on a parity-check matrix to obtain an encoded sequence; the transceiver module 2202 can be used to output the encoded sequence.

[0385] Exemplarily, the processing module 2201 can also be used to perform other processing on the encoded sequence; the transceiver module 2202 can also be used to send or output the signal after other processing.

[0386] Exemplarily, the processing module 2201 can include an encoding module. For example, the processing module 2201 can also include an acquisition module, a shortening module, a block module, etc. Exemplarily, the processing module 2201 can also include at least one of the following modules: a constellation mapping module, a stream cyclic shift module, a space and frequency mapping module, an IDFT module, an insert cyclic prefix and windowing module. Exemplarily, the transceiver module 2202 can include a radio frequency module, an antenna module, etc. Exemplarily, the transceiver module 2202 can include a pin module, etc.

[0387] Multiplexing Figure 22 In other embodiments of the present application, the communication device can be used to perform the actions performed by the second communication device in the above method embodiments. At this time, the communication device can be the Wi-Fi device itself or a chip or functional module that can be configured in the device, etc. The transceiver module 2202 is used to perform the operations related to the transceiver of the second communication device in the above method embodiments, and the processing module 2201 is used to perform the operations related to the processing of the second communication device in the above method embodiments.

[0388] Exemplarily, the transceiver module 2202 can be used to receive or input the signal transmitted through the channel; the processing module 2201 can be used to process the signal to obtain the information to be decoded.

[0389] Exemplarily, the transceiver module 2202 can be used to input the information to be decoded; the processing module 2201 can perform LDPC decoding on the information to be decoded based on the parity check matrix to obtain an information bit sequence.

[0390] Exemplarily, the processing module 2201 can include a decoding module. For example, the processing module 2201 can also include an acquisition module, etc. Exemplarily, the processing module 2201 can further include at least one of the following components: a cyclic prefix removal module, a DFT module, an interleaving module, a constellation demodulation module, a descrambling module. Exemplarily, the transceiver module 2202 can include a radio frequency module, an antenna module, etc. Exemplarily, the transceiver module 2202 can include a pin module, etc.

[0391] Optionally, in each of the above embodiments, the communication device can further include a storage module, which can be used to store instructions and / or data. The processing module 2201 can read the instructions and / or data in the storage module so that the communication device can implement the foregoing method embodiments. Exemplarily, the storage module can store the matrix prototype of the parity check matrix shown above, or the storage module can be used to store the CPM coefficients or the extended indication matrix, etc. in the matrix prototype of the parity check matrix shown above.

[0392] In each of the above embodiments, the specific descriptions of terms or steps such as the reference parity check matrix, the parity check matrix, the prototype of the parity check matrix, the prototype of the reference parity check matrix, CPM, cyclic shift number, extension factor, code length, code rate, etc. can refer to the introduction in the foregoing method embodiments, and will not be elaborated herein one by one.

[0393] The specific descriptions of the transceiver module and the processing module shown in each of the above embodiments are only examples. For the specific functions or steps executed by the transceiver module and the processing module, reference can be made to the foregoing method embodiments, and will not be elaborated herein.

[0394] The communication device of the embodiments of the present application has been introduced above. The possible product forms of the communication device will be introduced below. Any product form that has the functions of the Figure 22 above-mentioned communication device falls within the protection scope of the embodiments of the present application. The following introduction is only for example and does not limit the product form of the communication device of the embodiments of the present application to this.

[0395] In a possible implementation manner, Figure 22In the communication device shown, the processing module 2201 can be one or more processors, and the transceiver module 2202 can be a transceiver, or the transceiver module 2202 can also be a sending module and a receiving module. The sending module can be a transmitter, and the receiving module can be a receiver. The sending module and the receiving module are integrated into one device, such as a transceiver. In the embodiments of the present application, the processor and the transceiver can be coupled, etc. The embodiments of the present application do not limit the connection manner between the processor and the transceiver. During the process of executing the above method, the process of sending information in the above method can be the process of outputting the above information by the processor. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After the above information is output by the processor, other processing may be required before it reaches the transceiver. Similarly, the process of receiving information in the above method can be the process of the processor receiving the input above information. When the processor receives the input information, the transceiver receives the above information and inputs it to the processor. Further, after the transceiver receives the above information, the above information may need to be processed otherwise before being input to the processor.

[0396] As Figure 23 shown, the communication device 230 includes one or more processors 2320 and a transceiver 2310.

[0397] In some embodiments of the present application, the communication device can be used to execute the steps, methods, or functions executed by the above first communication device. For example, the processor 2320 can be used to execute the functions or steps implemented by the processing module 2201 as Figure 22 shown, and the transceiver 2310 can be used to execute the functions or steps implemented by the transceiver module 2202 as Figure 22 shown. Specific descriptions of the processor 2320 and the transceiver 2310 can be referred to Figure 22 or the method embodiments shown above, and will not be elaborated here.

[0398] In other embodiments of the present application, the communication device is used to execute the steps, methods, or functions executed by the above second communication device. For example, the processor 2320 can be used to execute the functions or steps implemented by the processing module 2201 as Figure 22 shown, and the transceiver 2310 can be used to execute the functions or steps implemented by the transceiver module 2202 as Figure 22 shown. Specific descriptions of the processor 2320 and the transceiver 2310 can be referred to Figure 22 or the method embodiments shown above, and will not be elaborated here.

[0399] In Figure 23In each implementation of the communication device shown, the transceiver may include a receiver and a transmitter. The receiver is used to perform the receiving function (or operation), and the transmitter is used to perform the transmitting function (or operation). And the transceiver is used to communicate with other devices / units via a transmission medium.

[0400] Optionally, the communication device 230 may further include one or more memories 2330 for storing program instructions and / or data. The memory 2330 is coupled to the processor 2320. The coupling in the embodiments of the present application is an indirect coupling or communication connection between communication devices, units or modules, which can be electrical, mechanical or other forms for information interaction between communication devices, units or modules. The processor 2320 may cooperate with the memory 2330. The processor 2320 may execute the program instructions stored in the memory 2330. Optionally, at least one of the above one or more memories may be included in the processor.

[0401] In the embodiments of the present application, the specific connection medium between the transceiver 2310, the processor 2320 and the memory 2330 is not limited. In the embodiments of the present application Figure 23 it is shown that the memory 2330, the processor 2320 and the transceiver 2310 are connected via a bus 2340. The bus is represented by a thick line in Figure 23 The connection manners between other components are only schematically illustrated and are not limiting. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 23 only one thick line is used to represent it in

[0402] In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., which can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor, etc.

[0403] In the embodiments of the present application, the memory may include, but is not limited to, non-volatile memories such as a hard disk drive (HDD) or a solid-state drive (SSD), a Random Access Memory (RAM), an Erasable Programmable ROM (EPROM), a Read-Only Memory (ROM), or a Compact Disc Read-Only Memory (CD-ROM), etc. The memory is any storage medium that can be used to carry or store program code in the form of instructions or data structures and can be read and / or written by a computer (such as the communication device shown in the present application), but is not limited thereto. The memory in the embodiments of the present application may also be a circuit or any other device capable of implementing a storage function, for storing program instructions and / or data.

[0404] The processor 2320 is mainly used for processing communication protocols and communication data, and controlling the entire communication device, executing software programs, and processing the data of software programs. The memory 2330 is mainly used for storing software programs and data. The transceiver 2310 may include a control circuit and an antenna. The control circuit is mainly used for converting baseband signals and radio frequency signals and processing radio frequency signals. The antenna is mainly used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, keyboards, etc., are mainly used for receiving data input by users and outputting data to users.

[0405] After the communication device is powered on, the processor 2320 can read the software program in the memory 2330, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be wirelessly transmitted, the processor 2320 performs baseband processing on the data to be transmitted and then outputs a baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 2320. The processor 2320 converts the baseband signal into data and processes the data.

[0406] In another implementation, the radio frequency circuit and the antenna may be provided independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuit and the antenna may be independent of the communication device and arranged in a remote manner.

[0407] The communication device shown in the embodiments of the present application may also have more than Figure 23More components, etc. are not limited in the embodiments of the present application. The methods executed by the above-mentioned processor and transceiver are only examples, and for the specific steps executed by the processor and transceiver, reference can be made to the methods introduced above.

[0408] In another possible implementation, Figure 22 In the communication device shown, the processing module 2201 may be one or more logic circuits, and the transceiver module 2202 may be an input / output interface, or also referred to as a communication interface, or an interface circuit, or an interface, etc. Or the transceiver module 2202 may also be a sending module and a receiving module. The sending module may be an output interface, and the receiving module may be an input interface. The sending module and the receiving module are integrated into one module, such as an input / output interface. As Figure 24 shown, Figure 24 The communication device shown includes a logic circuit 2401 and an interface 2402. That is, the above-mentioned processing module 2201 can be implemented by the logic circuit 2401, and the transceiver module 2202 can be implemented by the interface 2402. Among them, the logic circuit 2401 may be a chip, a processing circuit, an integrated circuit, or a system on chip (SoC) chip, etc., and the interface 2402 may be a communication interface, an input / output interface, a pin, etc. Exemplarily, Figure 24 is shown by taking the above-mentioned communication device as a chip as an example. The chip includes a logic circuit 2401 and an interface 2402.

[0409] In the embodiments of the present application, the logic circuit and the interface may also be coupled to each other. For the specific connection manner between the logic circuit and the interface, the embodiments of the present application do not make a limitation. Exemplarily, the logic circuit 2401 may be used to execute the functions or steps implemented by the processing module 2201 as Figure 22 shown, and the interface 2402 may be used to execute the functions or steps implemented by the transceiver module 2202 as Figure 22 shown. For the specific description of the logic circuit 2401 and the interface 2402, reference can be made to Figure 22 or the method embodiments shown above, which will not be elaborated here.

[0410] The communication device shown in the embodiments of the present application may implement the method provided in the embodiments of the present application in the form of hardware, or may also implement the method provided in the embodiments of the present application in the form of software, etc. The embodiments of the present application do not make a limitation on this.

[0411] The embodiments of the present application also provide a communication system, which includes a first communication device and a second communication device. The first communication device and the second communication device may be used to execute the methods in any of the foregoing embodiments.

[0412] In addition, the present application also provides a computer program, which is used to implement the operations and / or processes executed by each communication device in the method provided by the present application.

[0413] The present application also provides a computer-readable storage medium, in which computer code is stored. When the computer code runs on a computer, the computer is caused to execute the operations and / or processes executed by each communication device in the method provided by the present application.

[0414] The present application also provides a computer program product, which includes computer code or a computer program. When the computer code or the computer program runs on a computer, the operations and / or processes executed by each in the method provided by the present application are caused to be executed.

[0415] In several embodiments provided by the present application, it should be understood that the disclosed system, communication device, and method can be implemented in other ways. For example, the communication device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection to each other can be an indirect coupling or communication connection through some interfaces, communication devices, or modules, and can also be in the form of electrical, mechanical, or other connections.

[0416] The modules described as separate components may or may not be physically separated. The components displayed as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the technical effects of the solution provided by the embodiments of the present application.

[0417] In addition, in each embodiment of the present application, the functional modules can be integrated in a processing module, or each module can exist physically alone, or two or more modules can be integrated in one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0418] When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs.

[0419] As described above, the above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A coding method, characterized in that: The method comprises: Obtaining an information bit sequence; Performing low-density parity check (LDPC) coding on the information bit sequence based on a check matrix to obtain a coded sequence, wherein the length of the coded sequence is N1, wherein N1 is n times 1944, n is an integer greater than or equal to 2, and an expansion factor of the check matrix is ​​Z=81; The encoded sequence is output.

2. A decoding method, characterized in that: The method comprises: Obtain information to be decoded, where the length of the information to be decoded is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2; Low-density parity check (LDPC) decoding is performed on the information to be decoded based on a check matrix to obtain an information bit sequence, wherein an expansion factor of the check matrix is ​​Z=81.

3. The method according to claim 1 or 2, characterized in that: The first column and the second column in the matrix prototype of the check matrix corresponding to the check bit are obtained by performing diagonal expansion or anti-diagonal expansion on the first element and the last element in the first column of the matrix corresponding to the check bit in the matrix prototype of the basic check matrix, and the code rate corresponding to the basic check matrix is ​​the same as the code rate corresponding to the check matrix.

4. The method according to any one of claims 1 to 3, characterized in that: The elements in the matrix prototype of the check matrix corresponding to the check bits except the first column and the second column are obtained by diagonally expanding all the elements 0 except the first column in the matrix prototype of the basic check matrix corresponding to the check bits, and the code rate corresponding to the basic check matrix is ​​the same as the code rate corresponding to the check matrix.

5. The method according to any one of claims 1 to 4, characterized in that: The matrix corresponding to the information bits in the matrix prototype of the check matrix is ​​obtained by performing diagonal expansion or anti-diagonal expansion on the elements of the x-th row and y-th column in the matrix corresponding to the information bits in the matrix prototype of the basic check matrix, the elements of the x-th row and j-th column are greater than or equal to 0, x and y are both positive integers, and the code rate corresponding to the basic check matrix is ​​the same as the code rate corresponding to the check matrix.

6. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=1 / 2, the matrix prototype of the check matrix is ​​any one of the following matrices: or, or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

7. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=2 / 3, the matrix prototype of the check matrix is ​​any one of the following matrices: or, or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

8. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​any one of the following matrices: or, or, or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

9. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​any one of the following matrices: or, or, or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

10. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=1 / 2, the matrix prototype of the check matrix is ​​any one of the following matrices: or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

11. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=2 / 3, the matrix prototype of the check matrix is ​​any one of the following matrices: or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

12. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=3 / 4, the matrix prototype of the check matrix is ​​any one of the following matrices: or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

13. The method according to any one of claims 1 to 5, characterized in that: When the code rate of the information bit sequence is R=5 / 6, the matrix prototype of the check matrix is ​​any one of the following matrices: or, Among them, -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z unit matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z unit matrix.

14. A communication device, characterized in that: The method comprises a module for executing the method according to any one of claims 1 to 13.

15. A communication device, characterized in that: The method comprises a processor configured to execute the method according to any one of claims 1 to 13.

16. A communication device, characterized in that: comprising a logic circuit and an interface, wherein the logic circuit and the interface are coupled; The interface is used to input and / or output information, and the logic circuit is used to execute the method according to any one of claims 1-13.

17. A computer-readable storage medium, characterized in that: The computer-readable storage medium is used to store a computer program. When the computer program is executed, the method according to any one of claims 1 to 13 is executed.

18. A computer program product, characterized in that When the computer program product is executed, the method according to any one of claims 1 to 13 is performed.

19. A communication system, characterized in that: The communication system comprises a first communication device and a second communication device, wherein the first communication device is used to execute the method according to any one of claims 1 and 3-13, and the second communication device is used to execute the method according to any one of claims 2-13.

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