Data sending method and device, computer equipment and storage medium

Abstract

The invention discloses a data sending method and device, computer equipment and a storage medium, and relates to the technical field of data transmission, and the method comprises the step of dynamically adjusting the data transmission frequency according to the signal states of two clock domains. And if the receiving bandwidth of the first interface is relatively low, when it is detected that the signal values of the synchronous effective signal and the second effective signal at the target moment are different, the second interface stops sending data, so that the transmission frequency is reduced, the bandwidth requirement of the first interface is met, and data loss is avoided. On the contrary, if the receiving bandwidth of the first interface is high, when the signal values of the synchronous effective signal and the second effective signal at the target moment are the same, the second interface can perform data transmission. According to the technical scheme, the bandwidth of the second interface can be dynamically adjusted to be matched with the bandwidth of the first interface, bandwidth differences of different interfaces can be adapted, data transmission is more stable, and flexible bandwidth matching is achieved.

Description

Technical Field

[0001] This application relates to the technical field of data transmission, and particularly to a data sending method, apparatus, computer device, and storage medium. Background Art

[0002] During the data transmission process, the data path includes an uplink and a downlink. When the bandwidth of the interface of the uplink does not match the bandwidth of the interface of the downlink, the data transmission efficiency will be greatly reduced, which may not only cause data loss, but also seriously affect the stability and reliability of the entire data transmission process. Summary of the Invention

[0003] This application provides a data sending method, apparatus, computer device, and storage medium to at least solve the problem in the related art that the mismatch of the bandwidth of the interface leads to a significant reduction in data transmission efficiency, which may cause data loss and reduce the stability and reliability of the entire data transmission process.

[0004] This application provides a data sending method, including:

[0005] Synchronizing a first valid signal in a first clock domain associated with a first interface to a second clock domain to obtain a synchronized valid signal;

[0006] Obtaining a second valid signal in a second clock domain associated with a second interface;

[0007] When it is determined that the signal values of the synchronized valid signal and the second valid signal at a target moment are the same, controlling the signal value of a third valid signal at the target moment to be a first level value;

[0008] When controlling the signal value of the third valid signal at the target moment to be the first level value, controlling the second interface to send target data to the first interface;

[0009] When it is determined that the signal values of the synchronized valid signal and the second valid signal at the target moment are different, controlling the signal value of the third valid signal at the target moment to be a second level value;

[0010] When controlling the signal value of the third valid signal at the target moment to be the second level value, controlling the second interface to stop sending target data to the first interface.

[0011] This application further provides a data sending apparatus, including:

[0012] An obtaining module, configured to synchronize a first valid signal in a first clock domain associated with a first interface to a second clock domain to obtain a synchronized valid signal; and obtain a second valid signal in a second clock domain associated with a second interface;

[0013] A comparison module, configured to control the signal value of a third valid signal at a target moment to be a first level value when it is determined that the signal values of a synchronization valid signal and a second valid signal at the target moment are the same;

[0014] When controlling the signal value of the third valid signal at the target moment to be the first level value, control the second interface to send target data to the first interface;

[0015] When it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different, control the signal value of the third valid signal at the target moment to be a second level value;

[0016] When controlling the signal value of the third valid signal at the target moment to be the second level value, control the second interface to stop sending target data to the first interface.

[0017] The present application further provides a computer device, including: a memory for storing a computer program; a processor for implementing the steps of the above data sending method when executing the computer program.

[0018] The present application further provides a computer storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the steps of the above data sending method are implemented.

[0019] The present application synchronizes a first valid signal in a first clock domain to a second clock domain to obtain a synchronization valid signal, and compares it with a second valid signal in the second clock domain. When the signal values of the two are the same at the target moment, it indicates that the first clock domain and the second clock domain are in a relatively synchronized state at the target moment. At this time, control the signal value of the third valid signal at the target moment to be the first level value, and when controlling the signal value of the third valid signal at the target moment to be the first level value, control the second interface to send target data to the first interface. It effectively avoids data transmission errors caused by clock asynchronization, reduces the risk of data loss or incorrect transmission, improves data transmission efficiency, and significantly improves the utilization efficiency of bandwidth.

[0020] When the signal values of the synchronization valid signal and the second valid signal at the target moment are different, it indicates that there is a difference between the first clock domain and the second clock domain. At this time, control the signal value of the third valid signal at the target moment to be the second level value, so that the second interface stops sending target data to the first interface. It prevents data from accumulating excessively at the interface, effectively prevents bandwidth congestion, ensures the smoothness of data transmission, reduces data loss and delay caused by bandwidth congestion, and improves the reliability of data transmission.

[0021] This application controls whether the second interface sends data by determining whether the signal values of the synchronization valid signal and the second valid signal are the same, thereby achieving dynamic adjustment of the bandwidth of the second interface. By dynamically adjusting the bandwidth of the second interface to match the bandwidth of the first interface, it can adapt to the bandwidth differences of different interfaces, making data transmission more stable and achieving flexible matching of bandwidths. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 Schematic diagram of the clock design of the field programmable gate array chip provided by the embodiment of this application;

[0024] Figure 2 Schematic diagram of a data sending structure based on a counter provided in the related art;

[0025] Figure 3 Schematic diagram of the flowchart of a data sending method provided by the embodiment of this application;

[0026] Figure 4 Schematic diagram of a data sending structure based on a comparison module provided by the embodiment of this application;

[0027] Figure 5 Schematic diagram of signal value comparison provided by the embodiment of this application;

[0028] Figure 6 Schematic diagram of the structure of a data sending device provided by the embodiment of this application;

[0029] Figure 7 Schematic diagram of the structure of a computer device provided by the embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following will clearly and completely describe the technical solutions in the embodiments of this application with reference to the drawings in the embodiments of this application. Obviously, the described embodiments are only some embodiments of this application, rather than all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of this application.

[0031] It should be noted that in the description of this application, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0032] This application takes into account that the Field-Programmable Gate Array (FPGA) chip not only inherits programmability, but also overcomes the problem of limited gate circuits in traditional programmable devices. In addition, it has the advantages of short development cycle, low cost and low risk, and is widely used. Therefore, the technical solution of this application mainly aims at the data transmission problem in the FPGA chip. Taking the FPGA chip as an example, when designing the FPGA data communication system, when the interface frequencies of two modules are inconsistent, it is necessary to process them and perform bandwidth matching of the two interfaces before proceeding with the next data processing.

[0033] Figure 1 It is a schematic diagram of the clock design of the FPGA chip provided by the embodiment of this application. As Figure 1 shown, an interface data clock Clk_port is set at the interface of the FPGA chip, corresponding to the first clock domain, with a frequency of 100Mhz. A system data clock Clk_sys is set inside the FPGA, corresponding to the second clock domain, with a frequency of 100.1Mhz. Since the data bit width is 8bit, in this way, the internal data processing bandwidth of the FPGA is 100.1 * 8 = 800.8Mb, and the data processing bandwidth at the interface is 100 * 8 = 800Mb. In this case, when sending data from the FPGA to the interface, if no processing is performed, since the internal data processing bandwidth of the FPGA is larger than the interface bandwidth, data loss on the interface will inevitably occur. Through the technical solution of this application for bandwidth matching, controlling the sending of internal data of the FPGA to the interface can avoid data loss.

[0034] In the related art, the following methods are adopted to solve the data transmission problem caused by bandwidth mismatch between interfaces:

[0035] By adopting the method of isolating clock domains with an asynchronous First Input First Output (FIFO) queue, the full signal of the FIFO is used as an indication bit to tell the previous module to stop sending data, so as to make the bandwidths on both sides match. However, when determining the almost-full position of the FIFO, if the almost-full position is set too high, it is easy for the FIFO to become full. If the FIFO becomes full and then the previous module is informed to stop sending data, the data that has been sent by the previous module on the path will be lost. However, if the almost-full position is designed too low, the previous module will be frequently informed to stop sending data, resulting in the previous module prematurely pausing data transmission, which will cause waste of FPGA logic resources.

[0036] In addition, Figure 2 FIG. 1 is a schematic diagram of a data transmission structure based on a counter provided in the related art. As Figure 2 shown, there is also a way to control data transmission by deploying a counter in the FPGA chip to compare the count values. Although it can avoid data loss and save logic resources. However, there are certain limitations, mainly reflected in the aspect that the adjustment of the valid flag depends on a third counter. The specific disadvantages are as follows:

[0037] In the solution shown in Figure 2 FIG. 2, the adjustment of the valid flag depends on multiple counters. For example, in the logic design of the FPGA, dedicated resources need to be allocated for the third counter and its related counting logic. The operation of the counter, the implementation of the counting rule, and the interaction with other modules all require consuming certain logic units, registers and other resources. With the expansion of the system scale and the increase of functions, if multiple data transmission channels all adopt a similar way of adjusting the valid flag depending on the counter, it will significantly increase the occupation of the internal logic resources of the FPGA, which may lead to resource tension and affect the normal deployment and operation of other functional modules.

[0038] The adjustment of the valid flag completely depends on the counter value. Once the counter fails, such as counting errors or abnormal count values caused by interference, it will directly affect the correct adjustment of the valid flag state. Incorrect adjustment may cause chaos in data transmission control and seriously affect the reliability and stability of the system.

[0039] Therefore, the present application designs a data transmission method, device, computer device and storage medium to solve the above problems.

[0040] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] An embodiment of the present application provides a data transmission method, Figure 3A schematic flowchart of a data sending method provided by an embodiment of the present application is as follows Figure 3 The execution flow of the data sending method shown is described in detail for this data sending method.

[0042] S101: Synchronize the first valid signal in the first clock domain associated with the first interface to the second clock domain to obtain a synchronized valid signal.

[0043] In this embodiment, it is necessary to obtain the first valid signal in the first clock domain, and synchronize the first valid signal in the first clock domain associated with the first interface to the second clock domain to obtain a synchronized valid signal. This application is a technical solution designed for the case of sending data from a large-bandwidth interface to a small-bandwidth interface in an FPGA chip, where the bandwidth frequencies do not match, but the clock frequencies are not very different.

[0044] In this embodiment, as an example, the signal synchronization of the first valid signal and the second valid signal can be achieved through a FIFO. The first valid signal in the first clock domain is used as the input signal of the FIFO, and the first valid signal is written into the FIFO. The read operation of the FIFO is controlled by the second clock domain. In the second clock domain, data is read from the FIFO, and the read data is the synchronized valid signal synchronized to the second clock domain. Implementing signal synchronization through a FIFO can buffer data to a certain extent and adapt to the frequency differences between different clock domains.

[0045] S102: Obtain the second valid signal in the second clock domain associated with the second interface.

[0046] In this embodiment, the clock frequency of the first clock domain corresponds to the bandwidth corresponding to the first interface, and the clock frequency of the second clock domain corresponds to the bandwidth corresponding to the second interface. The bandwidth corresponding to the second interface is greater than or equal to the bandwidth corresponding to the first interface. As an example, for every 8 bits of valid data transmitted, a transmission bit width of 10 bits is required. At this time, the bandwidth B = clock frequency f × data bit width n × 8 / 10.

[0047] In this embodiment, the signal value of the first valid signal in the first clock domain is inverted according to the clock frequency of the first clock domain. For example, the signal value of the first valid signal in the first clock domain is the first level value 0 in the current clock cycle and the second level value 1 in the next clock cycle. The signal value of the first valid signal is inverted between 0 and 1 according to the clock frequency of the first clock domain.

[0048] In this embodiment, the signal value of the second valid signal in the second clock domain is inverted according to the clock frequency of the second clock domain. For example, the signal value of the second valid signal in the second clock domain is the first level value 0 in the current clock cycle and the second level value 1 in the next clock cycle. The signal value of the second valid signal is inverted between 0 and 1 according to the clock frequency of the second clock domain.

[0049] In this embodiment, as an example, an asynchronous first-in first-out queue can be used to isolate the clock domains to obtain the first clock domain associated with the first interface and the second clock domain associated with the second interface.

[0050] In this embodiment, the comparison module inside the field programmable gate array chip can be used to determine whether the signal values of the synchronous valid signal and the second valid signal at the target moment are the same. As an example, Figure 4 This is a schematic diagram of the data transmission structure provided by the embodiment of the present application based on the comparison module. As Figure 4 shown, the comparison module can be set in the second clock domain.

[0051] In this embodiment, only a comparison module needs to be set inside the FPGA chip, without the need for complex counter counting rule setting and counting process, which greatly reduces the occupation of resources such as logic units and registers, leaving more space for the deployment of other functional modules.

[0052] In the related art, once the counter fails (such as counting errors or abnormal count values caused by interference), it will directly affect the adjustment of the valid marker signal, thereby causing data transmission problems. In this embodiment, the comparison module directly compares the signal values and does not rely on the counting result of the counter, avoiding the incorrect adjustment of the valid marker signal caused by the counter failure, reducing the risk of data transmission interruption or loss, and improving the reliability and stability of the system.

[0053] In this embodiment, the comparison module directly compares the synchronous valid signal and the second valid signal, and can quickly obtain the result of whether the signal values are the same at the target moment, and can adjust the data transmission state more timely according to the signal comparison result.

[0054] When the system needs to add or modify the control conditions for data transmission, the related art is limited by the counting logic and architecture of the counter, and it is difficult to modify and expand. This embodiment is implemented through a comparison module. Only by adjusting the input signal or comparison logic of the comparison module can the comparison conditions be easily added or modified, facilitating the implementation of more complex data transmission control strategies and enhancing the expandability of the system functions.

[0055] S103: When it is determined that the signal values of the synchronous valid signal and the second valid signal at the target moment are the same, control the signal value of the third valid signal at the target moment to be the first level value.

[0056] In this embodiment, the signal value is 0 or 1. As an example, the signal value of the synchronization valid signal at the target moment is 0, and the signal value of the second valid signal at the target moment is also 0. It is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are the same.

[0057] As an example, the first level value can be a high level 1. When it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are the same, the third valid signal is pulled high, and the signal value of the third valid signal at the target moment is controlled to be the first level value (1).

[0058] S104: When controlling the signal value of the third valid signal to be the first level value at the target moment, control the second interface to send target data to the first interface.

[0059] In this embodiment, the target data is obtained by processing the quantity of the data received by the module corresponding to the second interface, or is the data generated by the module corresponding to the second interface itself. The second interface sends the target data to the first interface, and the module corresponding to the first interface can receive the target data.

[0060] In this embodiment, the fact that the signal values of the synchronization valid signal and the second valid signal at the target moment are the same indicates that the first clock domain and the second clock domain are in a relatively synchronized state at this target moment. At this time, the third valid signal is pulled high, and the second interface is controlled to send the target data to the first interface. It effectively avoids data transmission errors caused by clock asynchronization, reduces the risk of data loss or incorrect transmission, improves data transmission efficiency, and significantly improves the utilization efficiency of the bandwidth.

[0061] As an example, when controlling the signal value of the third valid signal to be the first level value at the target moment, the module corresponding to the second interface can also be controlled to perform operations on the target data. For example, operations of processing the original data to obtain the target data.

[0062] Figure 5 For the signal value comparison schematic diagram provided by the embodiment of the present application, as Figure 5 shown, within the 1st to 20th clock cycles of the second clock domain, it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are the same, the third valid signal is pulled high, the signal value of the third valid signal is pulled high to 1, and the second interface is controlled to send the target data to the first interface. Within the 21st clock cycle of the second clock domain, it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different, the third valid signal is pulled low, the signal value of the third valid signal is pulled low to 0, and the second interface is controlled to stop sending the target data to the first interface.

[0063] S105: When it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different, control the signal value of the third valid signal at the target moment to be the second level value.

[0064] As an example, the second level value can be a low level 0. When it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different, pull down the third valid signal to control the signal value of the third valid signal at the target moment to be the second level value (0).

[0065] S106: When controlling the signal value of the third valid signal at the target moment to be the second level value, control the second interface to stop sending the target data to the first interface.

[0066] In this embodiment, as an example, when controlling the signal value of the third valid signal at the target moment to be the second level value, it is also possible to control the module corresponding to the second interface to stop working on the target data. For example, the work of processing the original data to obtain the target data. Controlling the module corresponding to the second interface to stop working on the target data can effectively avoid the problems of occupying computing resources and storage resources, improve the utilization efficiency of system resources, and ensure the smoothness of the data transmission channel.

[0067] In this embodiment, the external interface of the FPGA chip is a channel connecting the FPGA chip with external devices or other modules to achieve data and signal transmission and interaction. As an example, for the downlink, the first interface can be the external interface of the FPGA chip, and the second interface can be the interface of the internal data processing module of the FPGA chip. If it is determined that the signal values are different, it indicates that there is a difference in the data bandwidth between the external interface of the FPGA chip and the internal data processing module. At this time, data loss will occur if data transmission is still carried out. At this time, the bandwidth of the second interface is greater than that of the first interface. Control the second interface to stop sending the target data to the first interface to control the internal data of the field programmable gate array chip to stop sending to the first interface. When the internal data quantity module of the field programmable gate array chip sends the target data to the first interface, if the third valid signal is the first level value, that is, the high level, it can send the target data to the lower level. If the third valid signal is the second level value, that is, the low level, it stops sending the target data to the lower level.

[0068] As another example, for the uplink, the second interface can be the external interface of the FPGA chip, and the first interface can be the interface of the internal data processing module of the FPGA chip. If it is determined that the signal values are different, it indicates that there is a difference in the data bandwidth between the external interface of the FPGA chip and the internal data processing module. At this time, data transmission will cause data loss. At this time, the bandwidth of the second interface is greater than that of the first interface, and the second interface is controlled to stop sending the target data to the first interface, so as to control the external interface of the FPGA chip to stop sending data to the internal data processing module of the field programmable gate array chip. The internal data processing module of the field programmable gate array chip can continue to process the data that has been received.

[0069] The technical solution of the present application is not only applicable to data transmission and sending between the external interface of the FPGA chip and the FPGA chip, but also applicable to data sending between two interconnected modules inside the FPGA chip (the two interconnected modules are in different clock domains and the clock frequencies are not very different).

[0070] In this embodiment, the different signal values of the synchronization valid signal and the second valid signal at the target moment respectively indicate that there is a difference between the first clock domain and the second clock domain. At this time, the third valid signal is pulled low to make the second interface stop sending the target data to the first interface. Prevent data from accumulating excessively at the interface, effectively prevent bandwidth congestion, ensure the smoothness of data transmission, reduce data loss and delay caused by bandwidth congestion, and improve the reliability of data transmission.

[0071] The present application controls whether the second interface sends data by determining whether the signal values of the synchronization valid signal and the second valid signal are the same, so as to realize the dynamic adjustment of the bandwidth of the second interface. By dynamically adjusting the bandwidth of the second interface to match the bandwidth of the first interface, it can adapt to the bandwidth differences of different interfaces, make data transmission more stable, and realize flexible matching of bandwidth.

[0072] The present application only needs to set a comparison module inside the FPGA chip, without the need for complex counter counting rule setting and counting process, and also avoids complex operations such as determining the almost full position of the FIFO, greatly reducing the occupation of resources such as logic units and registers. In the FIFO scheme, setting the almost full position too low will frequently stop the previous module from sending data, resulting in waste of FPGA logic resources. Setting the almost full position too high is likely to cause the situation of the FIFO being full, resulting in data loss of the data sent by the previous module on the path. This embodiment controls data transmission by comparing the signal values of the synchronization valid signal and the second valid signal, can more accurately judge the data transmission timing, and avoids unnecessary resource waste. Only when the signal values are the same (i.e., the clock domains are relatively synchronized) is data transmission controlled, effectively avoiding data transmission errors caused by clock asynchronization and reducing the risk of data loss or incorrect transmission.

[0073] The comparison module of the present application directly compares the synchronous valid signal and the second valid signal, and can quickly obtain the result of whether the signal values are the same, and can adjust the data transmission state more timely according to the signal comparison result.

[0074] The essence of the present application is to compare the signals in two clock domains with close frequencies. As time goes by, when the error accumulates to a certain extent, the two signal values will be different. When the signal values are different, the third valid signal is pulled low, and at the same time, a new round of comparison is started. After the third valid signal is pulled low, the relevant second interface stops sending data, so as to achieve the purpose of balancing the data bandwidth.

[0075] In an alternative embodiment, the data sending method further includes:

[0076] When the comparison module determines that the signal values of the synchronous valid signal and the second valid signal at the target moment are the same, the comparison module controls the signal value of the third valid signal at the target moment to be the first level value.

[0077] When the comparison module determines that the signal values of the synchronous valid signal and the second valid signal at the target moment are different, the comparison module controls the signal value of the third valid signal at the target moment to be the second level value.

[0078] In this embodiment, when the comparison module determines that the signal values of the synchronous valid signal and the second valid signal at the target moment are the same, the comparison module pulls up the third valid signal and controls the signal value of the third valid signal at the target moment to be the first level value (1).

[0079] In this embodiment, when the comparison module determines that the signal values of the synchronous valid signal and the second valid signal at the target moment are different, the comparison module pulls down the third valid signal and controls the signal value of the third valid signal at the target moment to be the second level value (0).

[0080] In this embodiment, the third valid signal is the enable signal for controlling data transmission in the second clock domain. The third valid signal is output by the comparison module.

[0081] In an alternative embodiment, the data sending method further includes:

[0082] When controlling the signal value of the third valid signal at the target moment to be the second level value, the signal values of the first valid signal in the first clock domain and the second valid signal in the second clock domain are reset to preset values.

[0083] In this embodiment, as an example, the signal values of the valid signals generated after the first valid signal in the first clock domain associated with the first interface until the target moment, including the valid signal generated at the target moment, can be reset to a preset value, and the preset value can be 0. The signal values of the valid signals generated after the second valid signal in the second clock domain associated with the second interface until the target moment, including the valid signal generated at the target moment, can be reset to a preset value, and the preset value can be 0. In addition, the preset value can also be 1.

[0084] In this embodiment, after resetting the signal values of the first valid signal in the first clock domain and the second valid signal in the second clock domain to the preset value, inversion is performed again. The signal value of the first valid signal in the first clock domain is inverted according to the clock frequency of the first clock domain, and the signal value of the second valid signal in the second clock domain is inverted according to the clock frequency of the second clock domain. In this embodiment, after resetting the signal values of the first valid signal in the first clock domain and the second valid signal in the second clock domain to the preset value, the technical solutions of S101 - S106 are executed again. For the detailed content, refer to the technical solutions of S101 - S106 above, and will not be elaborated here.

[0085] In an alternative embodiment, the target moment is within the target clock period, and the target clock period is the clock period of the second clock domain.

[0086] In this embodiment, as an example, the target moment can be the start moment of the target clock period, can be the end moment of the target clock period, or can also be any moment between the start moment and the end moment of the target clock period.

[0087] In this embodiment, as a moment, for each comparison, it is not limited to the same moment within the target clock period. For example, for the previous comparison, when it is determined that the signal values of the synchronous valid signal and the second valid signal at the start moment of the previous target clock period are the same, the signal value of the third valid signal at the start moment of the previous target clock period is controlled to be the first level value. For the current comparison, when it is determined that the signal values of the synchronous valid signal and the second valid signal at the end moment of the current target clock period are the same, the signal value of the third valid signal at the end moment of the current target clock period is controlled to be the first level value.

[0088] In this embodiment, comparison can be performed within each target clock cycle, that is, within the clock cycle of the second clock domain, to determine whether the signal values of the synchronization valid signal and the second valid signal at the target moment are the same. Performing the comparison within each target clock cycle can ensure that all judgments and controls related to data transmission are precisely matched to the rhythm of the second clock domain, effectively avoiding data transmission errors caused by clock asynchronization and improving the accuracy of clock synchronization. The signal state information can be obtained in a timely manner, and then the actions of data transmission can be quickly determined. When it is determined that the two signal values are the same, the third valid signal is immediately controlled to be pulled high to allow data to be transmitted from the second interface to the first interface. If the signal values are different, the third valid signal is quickly pulled low to stop data transmission. This timely control mechanism effectively reduces the waiting time and the possibility of incorrect transmission during data transmission, and significantly improves the efficiency of data transmission.

[0089] In an alternative embodiment, the data sending method further includes:

[0090] When it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different, a clock frequency adjustment operation is performed.

[0091] The clock frequency adjustment operation includes:

[0092] Determining the target number of times within the target time range.

[0093] When the target number of times is greater than or equal to the preset number of times, a corresponding clock frequency adjustment range is determined according to the target number of times.

[0094] The clock frequency of the second clock domain is adjusted according to the clock frequency adjustment range to reduce the difference between the synchronization valid signal and the second valid signal.

[0095] When the target number of times is less than the preset number of times, the execution of the clock frequency adjustment operation is ended.

[0096] In this embodiment, as an example, the clock frequency of the second clock domain can be adjusted according to the clock frequency adjustment range until the phase difference between the synchronization valid signal and the second valid signal is less than or equal to the preset range. The preset range can be set and adjusted according to actual needs. The phase relationship between the synchronization valid signal and the second valid signal is compared, and the adjustment method of the clock frequency of the second clock domain is determined according to the phase relationship between the synchronization valid signal and the second valid signal.

[0097] As an example, when the phase of the synchronization valid signal is ahead of the second valid signal, it indicates that the clock frequency of the second clock domain is relatively slow, resulting in the second valid signal lagging behind. At this time, it is necessary to appropriately increase the clock frequency of the second clock domain. Therefore, when the phase of the synchronization valid signal is ahead of the second valid signal, the clock frequency of the second clock domain is increased according to the clock frequency adjustment range. As an example, the clock frequency can be increased in a certain proportion or by a fixed step size. For example, a certain percentage (such as 1%, 2%, etc.) of the original frequency is increased each time, and then the phase relationship between the two signals is compared again, and the adjustment is continued until the phase difference is reduced to the preset range.

[0098] As an example, when the phase of the synchronization valid signal is behind the second valid signal, it indicates that the clock frequency of the second clock domain is relatively fast, resulting in the second valid signal being ahead. At this time, it is necessary to appropriately reduce the clock frequency of the second clock domain. Therefore, when the phase of the synchronization valid signal is behind the second valid signal, the clock frequency of the second clock domain is reduced according to the clock frequency adjustment range.

[0099] In this embodiment, the target number is the number of times when the signal values of the synchronization valid signal and the second valid signal at the target moment are determined to be different within the target time range. The target time range is the time range starting from the standard moment to the preset duration before the standard moment. The standard moment is the moment when it is recently determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different.

[0100] In this embodiment, performing the clock frequency adjustment operation and pulling down the third valid signal, controlling the signal value of the third valid signal to be the first level value at the target moment, and controlling the second interface to send the target data to the first interface are two independent processes and can be carried out simultaneously without affecting each other. In this embodiment, there may be a situation where the clock frequency of the second clock domain is adjusted continuously for multiple times.

[0101] In this embodiment, the preset number of times can be designed and adjusted according to actual needs. That the target number of times is greater than or equal to the preset number of times indicates that the asynchronization between the two clock domains is relatively serious, and it is necessary to adjust the clock frequency of the second clock domain. Different clock frequency adjustment ranges corresponding to different target numbers of times can be preset. For example, the clock frequency adjustment range corresponding to a target number of times of 12 is r = ±2%. The larger the target number of times, the larger the corresponding clock frequency adjustment range. Considering that the clock frequencies of the two clock domains are not very different, in order to avoid new asynchronization problems after adjustment or the original asynchronization situation becoming more serious, the following constraint conditions should be met: The maximum adjustment range of the clock frequency adjustment range is less than or equal to the maximum difference between the clock frequency of the first clock domain and the clock frequency of the second clock domain, and the clock frequency of the second clock domain after adjustment is less than or equal to the maximum clock frequency of the second clock domain. And when presetting different clock frequency adjustment ranges corresponding to different target numbers of times, the absolute value of the clock frequency adjustment range should be less than or equal to the preset adjustment value, and the preset adjustment value is, for example, 5%.

[0102] As an example, the clock frequency f1 of the first clock domain is 100 MHz, the current clock frequency f2 of the second clock domain is 120 MHz, and the maximum clock frequency f 2max = 130 MHz.

[0103] Determine the number of times that the signal values of the synchronization valid signal and the second valid signal at the target moment are different within the target time range, for example, it is 12, and use it as the target number of times n.

[0104] Compare the target number of times n with the preset number of times N(10).

[0105] The target number of times 12 > the preset number of times 10. Determine the corresponding clock frequency adjustment range r = ±2% according to the target number of times 12.

[0106] Adjust the clock frequency f2 of the second clock domain according to the clock frequency adjustment range r: Compare the phase relationship between the synchronization valid signal and the second valid signal. If the synchronization valid signal is in the leading phase, it means that the clock frequency of the second clock domain is too high and the frequency should be reduced; if the synchronization valid signal is in the lagging phase, it means that the clock frequency of the second clock domain is too low and the frequency should be increased.

[0107] If the frequency is increased, the clock frequency of the second clock domain after adjustment is:[[]]

[0108] f 2new = 120×(1 + 2%) = 122.4 MHz.

[0109] If the frequency is reduced, the clock frequency of the second clock domain after adjustment is:[[]]

[0110] f 2new= 120 × (1 - 2%) = 117.6 MHz.

[0111] Constraint condition check. If the constraint conditions are met and the frequency is increased, the clock frequency of the second clock domain is adjusted from 120 MHz to 122.4 MHz. If the frequency is decreased, the clock frequency of the second clock domain is adjusted from 120 MHz to 117.6 MHz.

[0112] As an example, the data sending method further includes:

[0113] Before controlling the second interface to send the target data to the first interface, the target data can be classified to obtain at least one type of data, and a priority is assigned to each type of data. For example, the critical control instruction data has the highest priority, and the ordinary service data has the second highest priority. In this way, during the data transmission process, the timely and accurate transmission of high-priority data is guaranteed first.

[0114] Specifically, a preset number of types and the corresponding priority for each type can be preset. Multiple priority queues can be set at the second interface, and each queue corresponds to a priority.

[0115] The target data can be divided into at least one type of data according to the data characteristics, and the priority corresponding to each type of data is determined. A priority mark is added to each type of data so that different-priority data can be identified and distinguished during the subsequent transmission process. After the classification and marking of the target data are completed, the target data is stored in the corresponding queue according to the priority. The target data is sent in the order of decreasing priority.

[0116] As an example, the data characteristics at least include: importance characteristics and real-time characteristics.

[0117] The importance characteristics at least include:

[0118] Business impact degree: Data with higher importance, for example, control instruction data that affects the core function of the system is crucial for the normal operation of the business; data with lower importance, for example, some auxiliary log record data has less impact on the core function of the business.

[0119] Data integrity requirements: Data with higher integrity requirements, for example, some data involving key transactions or decisions, once the data is missing or incorrect, may lead to serious consequences, and this type of data has higher importance; data with lower integrity requirements, for example, some temporary statistical data.

[0120] Real-time characteristics: Data with high real-time requirements, such as real-time monitoring data, real-time control instructions, etc., need to be transmitted and processed within a short time, otherwise it may lose its value; data with low real-time requirements, such as some periodically generated report data.

[0121] According to the above data characteristics, the target data can be divided into the following categories, and the corresponding preset number of types includes five types:

[0122] Key control instruction data: such as control instruction data for system startup, stop, reset, etc.

[0123] Real-time monitoring data: such as monitoring data of the real-time temperature, pressure, flow rate, etc. of the device. The requirement for real-time performance is high, but the importance is slightly lower than that of the control instruction data.

[0124] Key business transaction data: such as order data, etc.

[0125] Ordinary business data: such as daily business operation records, general statistical data, etc. The requirements for importance and real-time performance are relatively low.

[0126] Log record data: Log information used for system fault troubleshooting and auditing. The requirements for importance and real-time performance are both low.

[0127] Allocate corresponding priorities to each type of data:

[0128] Key control instruction data: The highest priority (such as level 1);

[0129] Real-time monitoring data: High priority (such as level 2);

[0130] Key business transaction data: Medium-high priority (such as level 3);

[0131] Ordinary business data: Medium priority (such as level 4);

[0132] Log record data: Low priority (such as level 5).

[0133] Add priority marks to each type of data so that different priority data can be identified and distinguished during subsequent transmission. The mark can be implemented by adding a priority field in the data header. For example, use a one-byte field to represent the priority, and the value range is 1-5, corresponding to the above different priority levels respectively.

[0134] In order to ensure that high-priority data can be transmitted first, multiple priority queues can be set at the second interface, and each queue corresponds to a priority level. After the data classification and marking are completed, the data is stored in the corresponding queues according to the priority. Adopt a priority-based scheduling algorithm, such as a static priority scheduling algorithm. In each transmission cycle, first check whether there is data in the highest priority queue. If there is, transmit the data in this queue first; if the highest priority queue is empty, check the next highest priority queue, and so on, until all queues have been checked.

[0135] To avoid the situation where data in the low - priority queue cannot be transmitted for a long time, a certain time threshold can be set. When the waiting time of the data in the low - priority queue exceeds the preset time threshold, its priority is temporarily increased so that it can be transmitted at an appropriate time. For example, it can be increased by one level from the initial priority level, such as from level 5 to level 4. After the data is sent to the first interface and reaches level 4, the initial priority level is restored, that is, from level 4 back to level 5.

[0136] Through the description of the above - mentioned embodiments, those skilled in the art can clearly understand that the method according to the above - mentioned embodiments can be implemented by means of software plus a necessary general - purpose hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0137] Figure 6 It is a schematic structural diagram of a data - sending device provided by an embodiment of the present application.

[0138] An embodiment of the present application also provides a data - sending device, as Figure 2 shown. The data - sending device includes:

[0139] An acquisition module 11, configured to synchronize a first valid signal in a first clock domain associated with a first interface to a second clock domain to obtain a synchronized valid signal, and acquire a second valid signal in a second clock domain associated with a second interface.

[0140] A comparison module 12, configured to control the signal value of a third valid signal to be a first level value at a target moment when it is determined that the signal values of the synchronized valid signal and the second valid signal at the target moment are the same.

[0141] When controlling the signal value of the third valid signal to be the first level value at the target moment, control the second interface to send target data to the first interface.

[0142] When it is determined that the signal values of the synchronized valid signal and the second valid signal at the target moment are different, control the signal value of the third valid signal to be a second level value at the target moment.

[0143] When controlling the signal value of the third valid signal to be the second level value at the target moment, control the second interface to stop sending target data to the first interface.

[0144] In an alternative embodiment, the comparison module 12 is disposed inside a field - programmable gate array chip. The comparison module is further configured to determine whether the signal values of the synchronized valid signal and the second valid signal at the target moment are the same. Among them, the comparison module is set in the second clock domain.

[0145] In an alternative embodiment, the target moment is within the target clock cycle, and the target clock cycle is the clock cycle of the second clock domain.

[0146] In an alternative embodiment, the comparison module 12 is further configured to control the signal value of the third valid signal to be the first level value at the target moment when it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are the same.

[0147] The comparison module 12 is further configured to control the signal value of the third valid signal to be the second level value at the target moment when it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different.

[0148] In an alternative embodiment, when the comparison module 12 controls the signal value of the third valid signal to be the second level value at the target moment, the comparison module 12 is further configured to reset the signal values of the first valid signal in the first clock domain and the second valid signal in the second clock domain to preset values.

[0149] In an alternative embodiment, the comparison module 12 is further configured to perform a clock frequency adjustment operation when it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different.

[0150] The clock frequency adjustment operation includes:

[0151] Determining a target number of times within a target time range.

[0152] Wherein, the target number of times is the number of times that it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different within the target time range. The target time range is a time range starting from a standard moment and ending at a preset duration before the standard moment. The standard moment is the most recent moment when it is determined that the signal values of the synchronization valid signal and the second valid signal at the target moment are different.

[0153] When the target number of times is greater than or equal to a preset number of times, determining a corresponding clock frequency adjustment range according to the target number of times.

[0154] Adjusting the clock frequency of the second clock domain according to the clock frequency adjustment range to reduce the difference between the synchronization valid signal and the second valid signal.

[0155] In an alternative embodiment, the clock frequency of the first clock domain corresponds to the bandwidth of the first interface, and the clock frequency of the second clock domain corresponds to the bandwidth of the second interface, and the bandwidth of the second interface is greater than or equal to the bandwidth of the first interface.

[0156] The further function descriptions of the above respective modules are the same as those in the corresponding above embodiments, and will not be elaborated herein.

[0157] Figure 7 The structural schematic diagram of a computer device provided by an embodiment of the present application. An embodiment of the present application also provides a computer device, such as Figure 7 shown, including a memory 10 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute the steps in any of the above-mentioned data sending method embodiments.

[0158] An embodiment of the present application also provides a computer storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned data sending method embodiments when running.

[0159] In an exemplary embodiment, the above computer storage medium may include, but is not limited to: various media that can store computer programs such as USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs.

[0160] An embodiment of the present application also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data sending method embodiments.

[0161] An embodiment of the present application also provides another computer program product, including a non-volatile computer storage medium. The non-volatile computer storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned data sending method embodiments.

[0162] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this document can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0163] The above has introduced in detail a data sending method, device, computer device, and storage medium provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data transmission method, characterized in that: include: Synchronize a first valid signal in a first clock domain associated with a first interface to a second clock domain to obtain a synchronized valid signal; Acquire a second valid signal in a second clock domain associated with a second interface; When it is determined that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are the same, controlling the signal value of the third valid signal at the target time to be a first level value; When the signal value of the third valid signal at the target time is controlled to be the first level value, controlling the second interface to send target data to the first interface; When it is determined that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are different, controlling the signal value of the third valid signal at the target time to be a second level value; When the signal value of the third valid signal at the target time is controlled to be the second level value, the second interface is controlled to stop sending the target data to the first interface.

2. The data transmission method according to claim 1, characterized in that: The method further comprises: A comparison module inside a field programmable gate array chip is used to determine whether the signal values ​​of the synchronous valid signal and the second valid signal at the target time are the same; wherein the comparison module is set in the second clock domain.

3. The data transmission method according to claim 2, characterized in that: The method further comprises: When the comparison module determines that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are the same, the signal value of the third valid signal at the target time is controlled by the comparison module to be the first level value; When the comparison module determines that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are different, the comparison module controls the signal value of the third valid signal at the target time to be a second level value.

4. The data transmission method according to claim 3, characterized in that: The method further comprises: When the signal value of the third valid signal at the target time is controlled to be the second level value, the signal value of the first valid signal in the first clock domain and the signal value of the second valid signal in the second clock domain are reset to preset values.

5. The data transmission method according to claim 1, characterized in that: The target time is within a target clock cycle, and the target clock cycle is a clock cycle of the second clock domain.

6. The data transmission method according to claim 1, characterized in that: The method further comprises: When it is determined that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are different, performing a clock frequency adjustment operation; The clock frequency adjustment operation includes: Determine target number of times within target time frame; The target number is the number of times that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are determined to be different within the target time range; the target time range is the time range from the standard time to a preset time before the standard time; the standard time is the time when the signal values ​​of the synchronization valid signal and the second valid signal at the target time are determined to be different for the most recent time; When the target number is greater than or equal to the preset number, determining a corresponding clock frequency adjustment range according to the target number; The clock frequency of the second clock domain is adjusted according to the clock frequency adjustment range to reduce the difference between the synchronous valid signal and the second valid signal.

7. The data transmission method according to claim 1, characterized in that: The clock frequency of the first clock domain corresponds to the bandwidth corresponding to the first interface, the clock frequency of the second clock domain corresponds to the bandwidth corresponding to the second interface, and the bandwidth corresponding to the second interface is greater than or equal to the bandwidth corresponding to the first interface.

8. A data sending device, characterized in that: include: An acquisition module, used for synchronizing a first valid signal in a first clock domain associated with a first interface to a second clock domain to obtain a synchronized valid signal; Acquire a second valid signal in a second clock domain associated with a second interface; A comparison module, configured to control the signal value of the third valid signal at the target time to be a first level value when it is determined that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are the same; When the signal value of the third valid signal at the target time is controlled to be the first level value, controlling the second interface to send target data to the first interface; When it is determined that the signal values ​​of the synchronization valid signal and the second valid signal at the target time are different, controlling the signal value of the third valid signal at the target time to be a second level value; When the signal value of the third valid signal at the target time is controlled to be the second level value, the second interface is controlled to stop sending the target data to the first interface.

9. A computer device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data sending method according to any one of claims 1 to 7 when executing the computer program.

10. A computer storage medium, characterized in that: The computer storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the data sending method according to any one of claims 1 to 7.

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