Interface conversion device and system on chip

Abstract

The invention discloses an interface conversion device and a system on chip, and belongs to the technical field of computer communication, and the device comprises an interface control module which is used for carrying out clock domain crossing processing on data at two sides of an advanced peripheral bus interface and an advanced extensible interface; the address generation module is used for remapping a base address of the advanced extensible interface; the state configuration module is used for determining an access address of the advanced peripheral bus interface at the advanced extensible interface according to a preset mapping relation, and configuring and recording a data interaction process on two sides; the bit width conversion module is used for performing bit width conversion on read-write data of the advanced peripheral bus interface and the advanced extensible interface; and the transmission control module is used for transmitting control signals of the advanced peripheral bus interface and the advanced extensible interface and transmitting read-write data of the advanced peripheral bus interface and the advanced extensible interface according to configuration data of the state configuration module. Through the device, protocol conversion from the APB to the AXI can be realized.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technologies, and particularly to an interface conversion device and a system on chip. Background Art

[0002] AXI (Advanced eXtensible Interface) is a high-performance, high-bandwidth, and low-latency on-chip bus protocol proposed by ARM Corporation. It is part of the AMBA (Advanced Microcontroller Bus Architecture) standard and is widely used in the design of high-performance SoCs (System on Chip). And APB (Advanced Peripheral Bus) is a low-power, low-complexity on-chip bus protocol in the AMBA bus architecture proposed by ARM Corporation, mainly used to connect peripheral devices with low bandwidth and not requiring a high-performance bus.

[0003] In some special application scenarios, the conversion from APB to AXI is used. For example, when the SoC has fixedly used the APB bus as the access interface bus for the registers of peripheral devices or internal storage, and the access interface of the newly developed IP (Intellectual Property, an integrated circuit module with a pre-designed specific function) is AXI, at this time, the conversion from APB to AXI is required. However, currently, there is no conversion device from APB to AXI, and this problem urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide an interface conversion device and a system on chip to solve the problem in the related art that the conversion from APB to AXI cannot be achieved.

[0005] To solve the above technical problem, the present invention provides an interface conversion device, including:

[0006] An interface control module, configured to perform cross-clock domain processing on data on both sides of the advanced peripheral bus interface and the advanced extensible interface, so that the data on both sides is consistent with the clock;

[0007] An address generation module, configured to remap the base address of the advanced extensible interface according to a preset mapping relationship;

[0008] A status configuration module, configured to determine the access address of the advanced peripheral bus interface in the advanced extensible interface according to the preset mapping relationship, and configure and record the data interaction process on both sides;

[0009] A bit-width conversion module is used to perform bit-width conversion on the read and write data of the advanced peripheral bus interface and the advanced extensible interface;

[0010] A transmission control module is used to transmit the control signals of the advanced peripheral bus interface and the advanced extensible interface, and transmit the read and write data of the advanced peripheral bus interface and the advanced extensible interface according to the configuration data of the status configuration module, so as to trigger the bit-width conversion module to complete the data interaction on both sides.

[0011] In a specific embodiment of the present application, the interface control module is specifically an asynchronous first-in first-out queue.

[0012] In a specific embodiment of the present application, the interface control module further includes:

[0013] An arbiter is used to determine the priority when multiple advanced peripheral bus interfaces access the advanced extensible interface.

[0014] In a specific embodiment of the present application, the address generation module includes:

[0015] A storage register is used to store the preset mapping relationship;

[0016] An adder unit is used to remap the base address of the advanced extensible interface according to the preset mapping relationship.

[0017] In a specific embodiment of the present application, the bit-width conversion module includes:

[0018] A write register is used to cache the write data from the advanced peripheral bus interface to the advanced extensible interface when the advanced peripheral bus interface initiates a write operation to the advanced extensible interface, intercept data with the same data bit-width as the advanced extensible interface from the write data to obtain first intercepted data, forward the first intercepted data to the advanced extensible interface, and update the cached data in itself after the first intercepted data is forwarded to the advanced extensible interface;

[0019] A read register is used to cache the read data of the advanced extensible interface when the advanced peripheral bus interface initiates a read operation to the advanced extensible interface, intercept data with the same data bit-width as the advanced peripheral bus interface from the read data to obtain second intercepted data, forward the second intercepted data to the advanced peripheral bus interface, and update the cached data in itself after the second intercepted data is forwarded to the advanced peripheral bus interface.

[0020] In a specific implementation manner of the present application, the status configuration module includes:

[0021] An address register, configured to, when the advanced peripheral bus interface accesses the advanced extensible interface, determine the access address of the advanced peripheral bus interface to the advanced extensible interface according to the preset mapping relationship, obtain a target access address, and store the target access address to implement cross-segment access of the advanced peripheral bus interface to the advanced extensible interface;

[0022] A read prefetch quantity register, configured to store the data length when the advanced peripheral bus interface initiates a prefetch operation on the advanced extensible interface;

[0023] A write threshold register, configured to store the data length when the advanced peripheral bus interface initiates a burst transfer on the advanced extensible interface;

[0024] A read failure time register, configured to store the failure time when the advanced peripheral bus interface reads pre-data from the advanced extensible interface;

[0025] A wait time transfer register, configured to store the maximum interval time when the advanced peripheral bus interface writes a first data and a second data to the advanced extensible interface; the first data and the second data are two adjacent write data;

[0026] An error status register, configured to record the error transfer signal between the advanced peripheral bus interface and the advanced extensible interface.

[0027] In a specific implementation manner of the present application, the transmission control module includes:

[0028] An address channel, configured to, when the advanced peripheral bus interface initiates a read operation or a write operation to the advanced extensible interface, complete the transmission of address information according to the signal returned by the advanced extensible interface;

[0029] A data channel, configured to, after the address channel completes the transmission of the read address or the write address, transmit the read data of the advanced peripheral bus interface to the advanced extensible interface, or transmit the write data of the advanced peripheral bus interface to the advanced extensible interface;

[0030] A response channel, configured to parse the response data of the advanced extensible interface, return the parsing result to the advanced peripheral bus interface, and store the error information in the parsing result in the error status register.

[0031] In a specific implementation manner of the present application, the address channel includes:

[0032] A read address sub-channel, which is used to make the read address channel signal of the Advanced eXtensible Interface (AXI) valid when the write operation signal is invalid, and determine that the handshake of the read address channel between the Advanced Peripheral Bus Interface (APBI) and the AXI is completed when the read address handshake signal returned by the AXI is valid;

[0033] A write address sub-channel, which is used to make the write address channel signal of the AXI valid when the write operation signal is valid, and determine that the handshake of the write address channel between the APBI and the AXI is completed when the write address handshake signal returned by the AXI is valid.

[0034] In a specific embodiment of the present application, the data channel includes:

[0035] A read data sub-channel, which is used to transmit the read data from the APBI to the AXI according to the data length when the APBI initiates a pre-read operation on the AXI and the invalidation time when the APBI reads data from the AXI when the read address handshake signal returned by the AXI is valid;

[0036] A write data sub-channel, which is used to transmit the write data from the APBI to the AXI according to the data length when the APBI initiates a burst transfer on the AXI and the maximum time interval when the APBI writes the first data and the second data to the AXI when the write address handshake signal returned by the AXI is valid.

[0037] To solve the above technical problems, the present invention also provides a system on chip, including an interface conversion device as disclosed above.

[0038] Beneficial effects: In the interface conversion device provided by the present invention, there are an interface control module, an address generation module, a status configuration module, a bit width conversion module, and a transmission control module. Among them, the interface control module can perform cross-clock domain processing on the data on both sides of the advanced peripheral bus interface and the advanced extensible interface, so that the clocks of the data on both sides of the advanced peripheral bus interface and the advanced extensible interface are consistent. The address generation module can remap the base address of the advanced extensible interface according to the preset mapping relationship. The status configuration module can determine the access address of the advanced peripheral bus interface in the advanced extensible interface according to the preset mapping relationship, and configure and record the data interaction process on both sides of the advanced peripheral bus interface and the advanced extensible interface. The bit width conversion module can perform bit width conversion on the read and write data between the advanced peripheral bus interface and the advanced extensible interface. The transmission control module can transmit the control signals on the transmission channel between the advanced peripheral bus interface and the advanced extensible interface, and transmit the read and write data between the advanced peripheral bus interface and the advanced extensible interface according to the configuration data of the status configuration module, thereby triggering the bit width conversion module to complete the data interaction between the advanced peripheral bus interface and the advanced extensible interface. Through the collaborative work of each functional module in this device, the data conversion from the advanced peripheral bus interface to the advanced extensible interface can be realized, that is, the data conversion from APB to AXI can be realized, thus fully making up for the performance defects of the APB bus to the AXI bus. Brief Description of the Drawings

[0039] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0040] Figure 1 Structural diagram of an interface conversion device provided by an embodiment of the present invention;

[0041] Figure 2 Structural diagram of an interface control module provided by an embodiment of the present invention;

[0042] Figure 3 Functional schematic diagram of the address generation module;

[0043] Figure 4 Schematic diagram when the write register and the read register perform bit width conversion on the write data and the read data respectively;

[0044] Figure 5 Schematic diagram of the principle when the address channel, data channel, and response channel in the transmission control module perform data interaction with the interface control module, status configuration module, address generation module, and bit width conversion module in the interface conversion device;

[0045] Figure 6 It is a schematic diagram of transmission signals for the interface conversion device to perform the protocol conversion from APB to AXI;

[0046] Figure 7 It is a schematic diagram for using a state machine to control the data transmission process from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface. Specific embodiments

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] The terms "including" and "having" in the specification of the present invention and the accompanying drawings above, as well as any variations related to "including" and "having", are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0049] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0050] The SoC chip will connect some peripheral devices to the SoC chip using a specific type of interconnect bus according to the type, function, and bandwidth requirements of the devices. Since peripheral devices are usually provided by third-party suppliers, sometimes there will be a situation where the peripheral devices do not match the interconnect bus of the SoC chip. Especially in the later stage of the design of the SoC chip, if there are adjustments to the system-level interfaces on the SoC chip, it will have a greater impact on the entire design of the SoC chip. For example: if the SoC has fixedly used the APB bus as the access interface bus for the registers or internal storage of the peripherals, and the newly developed IP access interface is AXI, then an APB to AXI conversion is required at this time. However, there is currently no APB to AXI conversion device. To solve this technical problem, in the present invention, an interface conversion device is provided, and using this device, the protocol conversion from APB to AXI can be achieved.

[0051] Please refer to Figure 1 , Figure 1 It is a structural diagram of an interface conversion device provided by an embodiment of the present invention. The device includes:

[0052] The interface control module 11 is used to perform cross-clock domain processing on the data on both sides of the advanced peripheral bus interface and the advanced extensible interface, so that the data on both sides is consistent with the clock.

[0053] The address generation module 12 is used to remap the base address of the advanced extensible interface according to a preset mapping relationship.

[0054] The status configuration module 13 is used to determine the access address of the advanced peripheral bus interface in the advanced extensible interface according to a preset mapping relationship, and configure and record the data interaction process on both sides.

[0055] The bit-width conversion module 14 is used to perform bit-width conversion on the read and write data of the advanced peripheral bus interface and the advanced extensible interface.

[0056] The transmission control module 15 is used to transmit the control signals of the advanced peripheral bus interface and the advanced extensible interface, and transmit the read and write data of the advanced peripheral bus interface and the advanced extensible interface according to the configuration data of the status configuration module 13, so as to trigger the bit-width conversion module 14 to complete the data interaction on both sides.

[0057] In the interface conversion device provided in this embodiment, an interface control module 11, an address generation module 12, a status configuration module 13, a bit-width conversion module 14, and a transmission control module 15 are provided. Through the collaborative work of these functional modules, the protocol conversion from APB to AXI can be achieved.

[0058] It should be noted that in this application, the advanced peripheral bus interface refers to the APB interface, and the advanced extensible interface refers to the AXI interface. Usually, the clocks of the data on both sides of the advanced peripheral bus interface and the advanced extensible interface are inconsistent. In this case, the protocol conversion from APB to AXI cannot be achieved. Therefore, the role of the interface control module 11 is to perform cross-clock domain processing on the data on both sides of the advanced peripheral bus interface and the advanced extensible interface, so that the data clocks on both sides of the advanced peripheral bus interface and the advanced extensible interface can be kept consistent. Only when the data clocks on both sides of the advanced peripheral bus interface and the advanced extensible interface are kept consistent, can the data on both sides of the advanced peripheral bus interface and the advanced extensible interface continue the subsequent protocol conversion.

[0059] If the advanced peripheral bus interface wants to access the advanced extensible interface, then the advanced peripheral bus interface must know the address of the access data in the advanced extensible interface. In this case, the address generation module 12 can be used to remap the base address of the advanced extensible interface according to a preset mapping relationship, so as to map the addresses of each data in the advanced extensible interface to the address space accessible by the advanced peripheral bus interface.

[0060] Then, the status configuration module 13 determines the access address of the advanced peripheral bus interface in the advanced extensible interface according to the preset mapping relationship, so as to realize the cross-segment access of the advanced peripheral bus interface to the advanced extensible interface. Moreover, the status configuration module 13 also configures and records the data interaction process on both sides of the advanced peripheral bus interface and the advanced extensible interface, so that the data interaction process between the advanced peripheral bus interface and the advanced extensible interface is more orderly and efficient.

[0061] Since the advanced peripheral bus interface is a low-power and low-bandwidth interface, while the advanced extensible interface is a high-performance and high-bandwidth interface, and their data transmission efficiencies are different. Therefore, when performing protocol conversion between APB and AXI, it is also necessary to use the bit-width conversion module 14 to perform bit-width conversion on the read and write data between the advanced peripheral bus interface and the advanced extensible interface, so that the advanced peripheral bus interface and the advanced extensible interface can perform normal data interaction.

[0062] When APB and AXI perform protocol conversion, there are some control signals on the transmission channel between the advanced peripheral bus interface and the advanced extensible interface to trigger the data interaction process between the advanced peripheral bus interface and the advanced extensible interface. Therefore, in this embodiment, the transmission control module 15 can also transmit the control signals on the transmission channel between the advanced peripheral bus interface and the advanced extensible interface based on the AXI protocol, and can also transmit the read and write data between the advanced peripheral bus interface and the advanced extensible interface according to the configuration data in the status configuration module 13. At the same time, the control signals on the transmission channel between the advanced peripheral bus interface and the advanced extensible interface in the transmission control module 15 can also control the working timing of the bit-width conversion module 14, and inform the bit-width conversion module 14 when to start the data interaction process between the advanced peripheral bus interface and the advanced extensible interface, so that the advanced peripheral bus interface and the advanced extensible interface can successfully and efficiently complete the protocol conversion between them.

[0063] From the above discussion, it can be seen that in the interface conversion device provided in this embodiment, the data conversion from the advanced peripheral bus interface to the advanced extensible interface can be realized, that is, the data conversion from APB to AXI can be realized, thus fully making up for the performance defect of the APB bus to the AXI bus.

[0064] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. Please refer to Figure 2 , Figure 2 which is the structural diagram of an interface control module provided by an embodiment of the present invention. As a preferred implementation manner, the interface control module 11 is specifically an asynchronous first-in first-out queue 101.

[0065] Since the asynchronous first-in-first-out queue 101 is a storage structure for cross-clock data transfer, and the asynchronous first-in-first-out queue 101 can also efficiently solve the timing problems when transferring data between clock domains with different frequencies or phases through handshake signals and synchronization mechanisms, in this embodiment, the interface control module 11 is set as the asynchronous first-in-first-out queue 101.

[0066] Obviously, through the technical solution provided by this embodiment, the efficiency of cross-clock domain processing of data on both sides of the advanced peripheral bus interface and the advanced extensible interface can be relatively improved.

[0067] As a preferred implementation manner, the interface control module 11 further includes:

[0068] An arbiter 102, which is used to determine the priority when multiple advanced peripheral bus interfaces access the advanced extensible interface.

[0069] In practical applications, sometimes it may also be necessary to encounter the protocol conversion scenario from APB to AXI for multiple advanced peripheral bus interfaces. In this case, an arbiter 102 can also be set in the interface control module 11, and the arbiter 102 is used to determine the priority when multiple advanced peripheral bus interfaces access the advanced extensible interface.

[0070] Specifically, the arbiter 102 will assign corresponding IP addresses to these different advanced peripheral bus interfaces, and determine the priority corresponding to each advanced peripheral bus interface through the priority arbitration policy stored in its internal storage. Then, the protocol conversion from APB to AXI is performed on these advanced peripheral bus interfaces in the corresponding priority order.

[0071] Obviously, through the technical solution provided by this embodiment, the protocol conversion from APB to AXI for multiple advanced peripheral bus interfaces can also be achieved.

[0072] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation manner, the address generation module includes:

[0073] A storage register for storing a preset mapping relationship;

[0074] An adder unit for remapping the base address of the advanced extensible interface according to the preset mapping relationship.

[0075] In this embodiment, the internal structure of the address generation module is specifically described. Among them, a storage register and an adder unit are provided in the address generation module. The storage register is used to store a preset mapping relationship, and the adder unit is used to remap the base address of the Advanced eXtensible Interface according to the preset mapping relationship.

[0076] Please refer to Figure 3 , Figure 3 which is a functional schematic diagram of the address generation module. When the Advanced Peripheral Bus Interface (APB interface) wants to access the Advanced eXtensible Interface (AXI interface), the Advanced Peripheral Bus Interface first determines the address that the Advanced Peripheral Bus Interface wants to access in the Advanced eXtensible Interface according to the preset mapping relationship and the base address in the Advanced eXtensible Interface to obtain the target access address; then, it accesses the data it wants to access at the target access address of the Advanced eXtensible Interface.

[0077] In practical applications, in order to improve the protocol conversion efficiency from APB to AXI, the access address from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface can also be detected. If the Advanced Peripheral Bus Interface makes consecutive accesses to the Advanced eXtensible Interface and needs to continuously write data to the Advanced eXtensible Interface, at this time, the data written from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface can also be written centrally according to the data length stored in the write threshold register when the Advanced Peripheral Bus Interface initiates a burst transfer to the Advanced eXtensible Interface.

[0078] Obviously, through the technical solution provided in this embodiment, the Advanced Peripheral Bus Interface can access different address segments of the Advanced eXtensible Interface.

[0079] Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the bit-width conversion module includes:

[0080] A write register, which is used to cache the write data from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface when the Advanced Peripheral Bus Interface initiates a write operation to the Advanced eXtensible Interface, intercept the data with the same data bit-width as that of the Advanced eXtensible Interface from the write data to obtain the first intercepted data, forward the first intercepted data to the Advanced eXtensible Interface, and update the cached data in itself after the first intercepted data is forwarded to the Advanced eXtensible Interface;

[0081] A read register, which is used to cache the read data from the Advanced eXtensible Interface when the Advanced Peripheral Bus Interface initiates a read operation to the Advanced eXtensible Interface, intercept the data with the same data bit-width as that of the Advanced Peripheral Bus Interface from the read data to obtain the second intercepted data, forward the second intercepted data to the Advanced Peripheral Bus Interface, and update the cached data in itself after the second intercepted data is forwarded to the Advanced Peripheral Bus Interface.

[0082] In this embodiment, in order to enable the bit-width conversion module to perform bit-width conversion on the read and write data between the Advanced Peripheral Bus (APB) interface and the Advanced eXtensible Interface (AXI), write registers and read registers are set in the bit-width conversion module. Please refer to Figure 4 , Figure 4 FIG. for the schematic diagrams of the write registers and the read registers respectively performing bit-width conversion on the write data and the read data.

[0083] Specifically, when the APB interface initiates a write operation to the AXI interface, the write register caches the write data from the APB interface to the AXI interface, and intercepts the data with the same data bit-width as the AXI interface from the written data to obtain the first intercepted data; then, the write register forwards the first intercepted data to the AXI interface, and updates the cached data in itself after the first intercepted data is forwarded to the AXI interface, so as to achieve the purpose of shifting and updating the stored data in itself.

[0084] When the APB interface initiates a read operation to the AXI interface, the read register caches the read data from the AXI interface, and intercepts the data with the same data bit-width as the APB interface from the read data to obtain the second intercepted data; then, the second intercepted data is forwarded to the APB interface, and the cached data in itself is updated after the second intercepted data is forwarded to the APB interface, so as to achieve the purpose of shifting and updating the stored data in itself.

[0085] Obviously, through the technical solution provided in this embodiment, the bit-width conversion module can be used to perform bit-width conversion on the read and write data between the APB interface and the AXI interface.

[0086] Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the status configuration module includes:

[0087] An address register, which is used to determine the access address of the APB interface to the AXI interface according to a preset mapping relationship when the APB interface accesses the AXI interface, obtain the target access address, and store the target access address to implement cross-segment access of the APB interface to the AXI interface;

[0088] A read prefetch quantity register, which is used to store the data length when the APB interface initiates a prefetch operation to the AXI interface;

[0089] A write threshold register, which is used to store the data length when the APB interface initiates a burst transfer to the AXI interface;

[0090] A read failure time register, used to store the failure time of the advanced peripheral bus interface when reading pre-read data from the advanced extensible interface;

[0091] The waiting time transmission register is used to store the maximum interval time when the advanced peripheral bus interface writes the first data and the second data into the advanced extensible interface; the first data and the second data are two adjacent write data;

[0092] The error status register is used to record error transmission signals between the advanced peripheral bus interface and the advanced extensible interface.

[0093] In this embodiment, the state configuration module is specifically described, wherein the state configuration module is composed of an address register, a read pre-stored quantity register, a write threshold register, a read failure time register, a wait time transmission register and an error state register.

[0094] The address register is used to determine the access address of the advanced peripheral bus interface to the advanced extensible interface according to the preset mapping relationship stored in the address generation module when the advanced peripheral bus interface accesses the advanced extensible interface, obtain the target access address, and store the target access address. Under this setting mode, the advanced peripheral bus interface can access the data in the advanced extensible interface according to the target access address stored in the address register, thereby realizing the cross-segment access of the advanced peripheral bus interface to the advanced extensible interface.

[0095] Since the advanced peripheral bus interface is a low-bandwidth interface and the advanced extensible interface is a high-bandwidth interface, the two interfaces have inconsistent data reading rates. In order to reduce the occupancy time of the AXI bus, the data length of the advanced peripheral bus interface when initiating a pre-read operation on the advanced extensible interface can also be stored in the read pre-stored quantity register. In this way, before the advanced peripheral bus interface performs a read operation on the advanced extensible interface, it can read data of a specified length (the specified length is the data length of the advanced peripheral bus interface when initiating a pre-read operation on the advanced extensible interface) from the advanced extensible interface in advance into the cache, thereby reducing the delay time of the advanced peripheral bus interface when performing a read operation on the advanced extensible interface and improving data transmission efficiency.

[0096] The write threshold register stores the data length when the advanced peripheral bus interface initiates a burst transmission to the advanced extensible interface. When the advanced peripheral bus interface performs a write operation on the advanced extensible interface, when the written data reaches the data length when the advanced peripheral bus interface initiates a burst transmission to the advanced extensible interface, the advanced peripheral bus interface can also directly initiate a burst transmission to the advanced extensible interface, that is, transmit multiple continuous data in one transaction to reduce transaction overhead.

[0097] The read failure time register stores the failure time when the advanced peripheral bus interface reads pre-read data from the advanced scalable interface. When the time that the pre-read data read by the advanced peripheral bus interface from the advanced scalable interface stays in the cache reaches the failure time, these pre-read data will be marked as invalid data. This setting mechanism can prevent the cache from being filled with invalid data.

[0098] The latency transfer register stores the maximum interval time when the advanced peripheral bus interface writes the first data and the second data to the advanced scalable interface. That is, when the time interval between two consecutive data writes by the advanced peripheral bus interface to the advanced scalable interface exceeds the maximum interval time when the advanced peripheral bus interface writes the first data and the second data to the advanced scalable interface, it can be considered that there is no data to be written to the advanced scalable interface in the subsequent process. This mechanism can optimize the data transfer process and avoid unnecessary time waiting.

[0099] The error status register is used to record the error transfer signals between the advanced peripheral bus interface and the advanced scalable interface. During the data interaction process between the advanced peripheral bus interface and the advanced scalable interface, the system will detect various error situations, such as: transmission timeout, data error, etc. If the error transfer signals between the advanced peripheral bus interface and the advanced scalable interface are recorded by using the error status register, then the stored data in the error status register can be used to debug and repair the abnormal faults found in the future, which can further improve the maintenance efficiency of the staff.

[0100] Obviously, through the technical solution provided by this embodiment, the state configuration module can be used to configure and control the data interaction process on both sides of the advanced peripheral bus interface and the advanced scalable interface.

[0101] As a preferred implementation manner, the transmission control module includes:

[0102] An address channel, which is used to complete the transmission of address information according to the signal returned by the advanced scalable interface when the advanced peripheral bus interface initiates a read operation or a write operation to the advanced scalable interface;

[0103] A data channel, which is used to transmit the read data from the advanced peripheral bus interface to the advanced scalable interface or transmit the write data from the advanced peripheral bus interface to the advanced scalable interface after the address channel has completed the transmission of the read address or the write address;

[0104] A response channel, which is used to parse the response data of the advanced scalable interface, return the parsing result to the advanced peripheral bus interface, and store the error information in the parsing result in the error status register.

[0105] In this embodiment, the internal structure of the transmission control module is specifically described. Among them, an address channel, a data channel, and a response channel are provided in the transmission control module. The address channel corresponds to the SETUP phase of the APB transmission and is used to prepare the information required for data transmission in this phase. In the first clock cycle when PSEL is valid, the address channel initiates a read operation or a write operation on the Advanced eXtensible Interface and waits for the corresponding ADDR READY of the Advanced eXtensible Interface to become valid, so as to complete the transmission of the address information.

[0106] The transmission of read and write data by the data channel occurs in the ACCESS phase of the APB transmission, in which PSEL is valid and PENABLE is valid. After the address channel completes the transmission of the read address or write address, the data channel transmits the read data from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface, or transmits the write data from the Advanced Peripheral Bus Interface to the Advanced eXtensible Interface. When the data channel transmits the read data or write data, it generates the VALID signal of the corresponding data channel according to the control signal of the Advanced Peripheral Bus Interface, and determines the transmission of the data channel according to the handshake READY signal returned by the Advanced eXtensible Interface.

[0107] The response channel is used to parse the response data of the Advanced eXtensible Interface to judge the correctness of the data transmission between the Advanced Peripheral Bus Interface and the Advanced eXtensible Interface, and returns the parsing result to the Advanced Peripheral Bus Interface. At the same time, the response channel also stores the error information in the parsing result into the error status register in the status configuration module. Please refer to Figure 5 , Figure 5 FIG. is a schematic diagram of the principle when the address channel, data channel, and response channel in the transmission control module perform data interaction with the interface control module, status configuration module, address generation module, and bit width conversion module in the interface conversion device.

[0108] Obviously, through the technical solution provided by this embodiment, various control signals between the Advanced Peripheral Bus Interface and the Advanced eXtensible Interface can be transmitted by using the address channel, data channel, and response channel in the transmission control module.

[0109] As a preferred implementation manner, the address channel includes:

[0110] A read address sub-channel, which is used to make the read address channel signal of the Advanced eXtensible Interface valid when the write operation signal is invalid, and determines that the handshake of the read address channel between the Advanced Peripheral Bus Interface and the Advanced eXtensible Interface is completed when the read address handshake signal returned by the Advanced eXtensible Interface is valid;

[0111] A write address sub-channel, which is used to make the write address channel signal of the Advanced eXtensible Interface (AXI) valid when the write operation signal is valid, and to determine that the handshake of the write address channel between the Advanced Peripheral Bus Interface (APBI) and the AXI is completed when the write address handshake signal returned by the AXI is valid.

[0112] In this embodiment, the address channel actually includes two channels: a read address sub-channel and a write address sub-channel. When the write operation signal PWRITE is invalid, it indicates that the APBI initiates a read operation to the AXI. At this time, the read address channel signal ARVALID of the AXI is made valid and held until the read address handshake signal ARREADY returned by the AXI is valid, and the handshake of the read address sub-channel is completed. The address generated by the address generation module and the data length configured in the read prefetch count register have been transmitted to the AXI.

[0113] When the write operation signal PWRITE is valid, it indicates that the APBI initiates a write operation to the AXI. The data from the APBI is first cached. When the initiation condition for the write transfer is met, the write address channel signal AWVALID of the AXI is made valid and held until the write address handshake signal AWREADY returned by the AXI is valid, and the handshake of the write address channel is completed. The initiation condition for the write transfer is determined by the register of the status configuration module: one is that the number of data in the write cache reaches the value stored in the write threshold register, and it is considered that a transfer to the AXI can be initiated; the other is to set a counter. Each time the write operation signal from the APBI is valid, the counter starts counting from zero. When the count value of the counter reaches the value of the wait time transfer register, it is considered that there is no subsequent transfer on the APBI side, and a transfer to the AXI can be initiated.

[0114] As a preferred embodiment, the data channel includes:

[0115] A read data sub-channel, which is used to transfer the read data from the APBI to the AXI according to the data length when the APBI initiates a pre-read operation to the AXI and the invalid time when the APBI reads data from the AXI when the read address handshake signal returned by the AXI is valid;

[0116] A write data sub-channel, which is used to transfer the write data from the APBI to the AXI according to the data length when the APBI initiates a burst transfer to the AXI and the maximum time interval between writing the first data and the second data to the AXI when the write address handshake signal returned by the AXI is valid.

[0117] In this embodiment, the data channel actually includes a read data sub-channel and a write data sub-channel. The transmission of read and write data by the data channel occurs in the ACCESS stage of the APB transmission. When the previous stage is the transmission of the read address sub-channel, the read data is transmitted in this stage. At this time, the receive handshake signal RREADY output to the Advanced Extensible Interface is 1. When the data valid flag RVALID returned by the Advanced Extensible Interface is received and is 1, it is considered that the read operation is completed, the PREADY sent to the Advanced Peripheral Bus Interface is made valid, and at the same time, according to the data length when the Advanced Peripheral Bus Interface initiates a pre-read operation on the Advanced Extensible Interface and the invalidation time when the Advanced Peripheral Bus Interface reads data from the Advanced Extensible Interface, the read data from the Advanced Peripheral Bus Interface to the Advanced Extensible Interface is transmitted to the Advanced Peripheral Bus Interface.

[0118] In addition, in practical applications, a counter can also be used. After receiving the read data valid signal, the counter starts to count. When the count value of the counter is equal to the value stored in the read invalidation time register, it is considered that there is no subsequent read operation, and the read buffer can be reset.

[0119] If the previous stage is the transmission of the write address sub-channel, the write data is transmitted in this stage. At this time, the conversion device will transmit PWDATA as the write data, transmit PSTRB to the WSTRB port, and make the write data request WVALID valid. When the Advanced Peripheral Bus Interface receives that the write address handshake signal WREADY returned by the Advanced Extensible Interface is valid, it can transmit the write data from the Advanced Peripheral Bus Interface to the Advanced Extensible Interface according to the data length when the Advanced Peripheral Bus Interface initiates a burst transmission on the Advanced Extensible Interface and the maximum time interval when the Advanced Peripheral Bus Interface writes the first data and the second data to the Advanced Extensible Interface.

[0120] When the response channel parses the response data of the Advanced Extensible Interface, it also falls into two cases. The first case is that after the transmission of the read data sub-channel is completed, the Advanced Peripheral Bus Interface will wait for the data valid flag RVALID returned by the Advanced Extensible Interface. When the Advanced Peripheral Bus Interface receives that RVALID is valid, it will parse the RRESP signal returned by the Advanced Extensible Interface. If RRESP is not 0, PSLVERR is set to 1. If PRESP is 0, then PSLVERR is set to 0, and this signal is returned to the Advanced Peripheral Bus Interface.

[0121] The second case is that after the write data sub-channel is completed, the response handshake signal BREADY output to the Advanced eXtensible Interface is set to 1. When the BVALID signal returned by the Advanced eXtensible Interface is valid, the Advanced Peripheral Bus Interface sets PREADY to valid and parses the BRESP signal at the same time. When BRESP is not 0, PSLVERR is set to 1; when BRESP is 0, PSLVERR is set to 0, and this signal is returned to the Advanced Peripheral Bus Interface.

[0122] Please refer to Figure 6 , Figure 6 Figure for the transmission signals of the interface conversion device when performing the protocol conversion from APB to AXI. When PSEL is valid and PWRITE is valid, the interface conversion device will perform the transmission of the write address sub-channel. At this time, the write address valid signal AWVALID is set to 1, and the Advanced Peripheral Bus Interface sends the write address to the Advanced eXtensible Interface. The Advanced Peripheral Bus Interface also waits for the write address handshake signal AWREADY returned by the Advanced eXtensible Interface to be valid. After the Advanced Peripheral Bus Interface receives the valid write address handshake signal AWREADY returned by the Advanced eXtensible Interface, it starts the transmission of the write data sub-channel. At this time, the write data valid signal WVALID is set to 1, and the Advanced Peripheral Bus Interface sends the write data to the Advanced eXtensible Interface and waits for the write data handshake signal WREADY returned by the Advanced eXtensible Interface to be valid. After the Advanced Peripheral Bus Interface receives the valid write data handshake signal WREADY returned by the Advanced eXtensible Interface, it performs the transmission of the response channel. At this time, the write response handshake signal BREADY is set to 1. When the Advanced Peripheral Bus Interface receives the valid write response signal BVALID returned by the Advanced eXtensible Interface, the handshake signal PREADY of the Advanced Peripheral Bus Interface is set to 1, and the result detected by BRESP is sent to the Advanced Peripheral Bus Interface.

[0123] When PSEL is valid and PWRITE is invalid, the interface conversion device will perform the transmission of the read address sub-channel. At this time, the read address valid signal ARVALID is set to 1, and the advanced peripheral bus interface sends the read address to the advanced extensible interface. The advanced peripheral bus interface will also wait for the read address handshake signal ARREADY returned by the advanced extensible interface to be valid. After the advanced peripheral bus interface receives the read address handshake signal ARREADY returned by the advanced extensible interface, it will start the transmission of the read data sub-channel. At this time, the read handshake signal RERADY is set to 1, and it waits for the read data valid signal RVALID returned by the advanced extensible interface to be valid, as well as the read data read. When the advanced peripheral bus interface receives that the read data valid signal RVALID returned by the advanced extensible interface is 1, it will perform the transmission of the response channel. At this time, the handshake port signal PREADY of the advanced peripheral bus interface is set to 1, and at the same time, the result detected by RRESP is sent to the advanced peripheral bus interface.

[0124] Obviously, through the technical solution provided by this embodiment, the data reading and writing between the advanced peripheral bus interface and the advanced extensible interface can be controlled and transmitted.

[0125] Based on the above embodiment, this embodiment further describes and optimizes the technical solution. As a preferred implementation manner, the above conversion device can also be connected to a peripheral device with an advanced extensible interface.

[0126] When a peripheral device with an advanced extensible interface is connected to the interface conversion device, the interface conversion device can realize the operation and access to these peripheral devices, so as to further broaden the application scope of the interface conversion device provided by this application in practical applications.

[0127] Specifically, in practical applications, the peripheral device with an advanced extensible interface can be set as a memory, a DSP (Digital Signal Processor), an FPGA (Field Programmable Gate Array), and so on.

[0128] An interface conversion device provided by an embodiment of the present invention can also use a state machine to control the data transmission process from the advanced peripheral bus interface to the advanced extensible interface. Please refer to Figure 7 , Figure 7 which is a schematic diagram of using a state machine to control the data transmission process from the advanced peripheral bus interface to the advanced extensible interface.

[0129] The interface conversion device is in an idle state in the initial state. When the interface conversion device receives a data access request from the high-speed peripheral bus interface, it first determines whether the access request is a read operation or a write operation, and then enters different state machine processing flows according to the type of the access request.

[0130] If the interface conversion device receives a write request sent by the high-speed peripheral bus interface, the interface conversion device will enter the write waiting state and cache the data after bit width conversion into the cache. When the amount of data in the cache reaches the data length when the high-speed peripheral bus interface initiates a burst transfer to the advanced extensible interface, and these addresses are all consecutive and the time interval between two adjacent written data does not exceed the maximum interval time stored in the waiting time transfer register, the interface conversion device will enter the write transfer state. Or, when the addresses for the high-speed peripheral bus interface to write data to the advanced extensible interface are not consecutive and the time interval between two adjacent written data does not exceed the maximum interval time stored in the waiting time transfer register, the interface conversion device will also enter the write transfer state.

[0131] When the high-speed peripheral bus interface writes data to the advanced extensible interface, if the time interval between two consecutive data written by the high-speed peripheral bus interface to the advanced extensible interface exceeds the maximum interval time stored in the waiting time transfer register, or there is no data in the cache to be written to the advanced extensible interface, the interface conversion device will jump to the idle state. Otherwise, it will return to the write waiting state.

[0132] If the interface conversion device receives a read request sent by the high-speed peripheral bus interface, the interface conversion device will enter the read transfer state, and write the read-back data into the read cache according to the read address output by the address generation module, the data length when the high-speed peripheral bus interface initiates a pre-read operation to the advanced extensible interface stored in the read pre-storage quantity register, and the invalidation time when the high-speed peripheral bus interface reads pre-read data from the advanced extensible interface stored in the read invalidation time register. Then, the read cache processing state will use the bit width conversion module to perform bit width conversion on the read data in the read cache and convert it into data recognizable by the advanced extensible interface, thereby realizing the protocol conversion from APB to AXI.

[0133] Correspondingly, an embodiment of the present invention further provides a system on a chip, including an interface conversion device as disclosed above.

[0134] The system on a chip provided by the embodiment of the present invention has the beneficial effects of the interface conversion device disclosed above.

[0135] The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. Professionals can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0136] The above has introduced in detail an interface conversion device and a system on a chip provided by the present invention. Specific examples are used herein to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. An interface conversion device, characterized in that: include: An interface control module, used for performing cross-clock domain processing on data on both sides of the advanced peripheral bus interface and the advanced extensible interface, so as to keep the data on both sides consistent with the clock; An address generation module, used for remapping the base address of the advanced extensible interface according to a preset mapping relationship; A state configuration module, used to determine the access address of the advanced peripheral bus interface in the advanced extensible interface according to the preset mapping relationship, and configure and record the data interaction process between the two sides; A bit width conversion module, used for performing bit width conversion on the read and write data of the advanced peripheral bus interface and the advanced extensible interface; The transmission control module is used to transmit the control signals of the advanced peripheral bus interface and the advanced extensible interface, and transmit the read and write data of the advanced peripheral bus interface and the advanced extensible interface according to the configuration data of the state configuration module, so as to trigger the bit width conversion module to complete the data interaction on both sides.

2. An interface conversion device according to claim 1, characterized in that: The interface control module is specifically an asynchronous first-in first-out queue.

3. An interface conversion device according to claim 2, characterized in that: The interface control module also includes: The arbiter is used to determine the priority of the multiple advanced peripheral bus interfaces when the multiple advanced peripheral bus interfaces access the advanced extensible interface.

4. The interface conversion device according to claim 1, characterized in that: The address generation module comprises: A storage register, used to store the preset mapping relationship; An adder unit is used to remap the base address of the advanced extensible interface according to the preset mapping relationship.

5. The interface conversion device according to claim 1, characterized in that: The bit width conversion module comprises: a write register, used for caching write data from the advanced peripheral bus interface to the advanced extensible interface when the advanced peripheral bus interface initiates a write operation to the advanced extensible interface, intercepting data with the same data bit width as the advanced extensible interface from the write data to obtain first intercepted data, forwarding the first intercepted data to the advanced extensible interface, and updating the cached data in itself after the first intercepted data is forwarded to the advanced extensible interface; a read register, used for caching the read data of the advanced extensible interface when the advanced peripheral bus interface initiates a read operation to the advanced extensible interface, intercepting data with the same data bit width as the advanced peripheral bus interface from the read data to obtain second intercepted data, forwarding the second intercepted data to the advanced peripheral bus interface, and updating the cached data in itself after the second intercepted data is forwarded to the advanced peripheral bus interface.

6. The interface conversion device according to claim 1, characterized in that: The state configuration module includes: an address register, used for determining, when the advanced peripheral bus interface accesses the advanced extensible interface, an access address of the advanced peripheral bus interface to the advanced extensible interface according to the preset mapping relationship, obtaining a target access address, and storing the target access address to implement cross-segment access of the advanced peripheral bus interface to the advanced extensible interface; A read pre-stored quantity register is used to store the data length when the advanced peripheral bus interface initiates a pre-read operation on the advanced extensible interface; A write threshold register, used to store the data length when the advanced peripheral bus interface initiates a burst transmission to the advanced extensible interface; A read failure time register, used to store the failure time of the advanced peripheral bus interface when reading pre-data from the advanced extensible interface; A waiting time transmission register, used for storing a maximum interval time when the advanced peripheral bus interface writes first data and second data into the advanced extensible interface; the first data and the second data are two adjacent write data; The error status register is used to record the error transmission signal between the advanced peripheral bus interface and the advanced extensible interface.

7. An interface conversion device according to claim 6, characterized in that: The transmission control module comprises: An address channel, used for completing the transmission of address information according to a signal returned by the advanced extensible interface when the advanced peripheral bus interface initiates a read operation or a write operation to the advanced extensible interface; a data channel, used for transmitting read data from the advanced peripheral bus interface to the advanced extensible interface, or transmitting write data from the advanced peripheral bus interface to the advanced extensible interface, after the address channel completes transmitting the read address or the write address; The response channel is used to parse the response data of the advanced extensible interface, return the parsing result to the advanced peripheral bus interface, and store the error information in the parsing result to the error status register.

8. An interface conversion device according to claim 7, characterized in that: The address channel includes: a read address subchannel, used to set the read address channel signal of the advanced extensible interface to be valid when the write operation signal is invalid, and to determine that the read address channel handshake between the advanced peripheral bus interface and the advanced extensible interface is completed when the read address handshake signal returned by the advanced extensible interface is valid; The write address subchannel is used to set the write address channel signal of the advanced extensible interface to be valid when the write operation signal is valid, and to determine whether the write address channel handshake between the advanced peripheral bus interface and the advanced extensible interface is completed when the write address handshake signal returned by the advanced extensible interface is valid.

9. An interface conversion device according to claim 8, characterized in that: The data channel includes: a read data subchannel, for transmitting read data from the advanced peripheral bus interface to the advanced extensible interface according to the data length when the advanced peripheral bus interface initiates a pre-read operation on the advanced extensible interface and the failure time when the advanced peripheral bus interface reads data from the advanced extensible interface, when receiving the read address handshake signal returned by the advanced extensible interface as valid; a write data subchannel, for transmitting the write data from the advanced peripheral bus interface to the advanced extensible interface according to the data length when the advanced peripheral bus interface initiates a burst transmission to the advanced extensible interface and the maximum time interval when the advanced peripheral bus interface writes the first data and the second data into the advanced extensible interface, when receiving a valid write address handshake signal returned by the advanced extensible interface.

10. A system on chip, characterized in that: It comprises an interface conversion device as described in any one of claims 1 to 9.

Images