Method and module capable of defending dead time attack of gated detector

Abstract

The invention provides a method for defending the dead time attack of a gated detector in a QKD (quantum key distribution) system and a corresponding detection module capable of defending the dead time attack of the gated detector, which are characterized in that after any detection channel detects and generates an avalanche signal, a control unit simultaneously controls a double-channel delay unit of a multi-channel detector not to be enabled; a gate control signal (narrow pulse) is not generated any more, so that all detection channels of the multi-channel detector enter a dead time state at the same time; and when the dead time is ended, the control unit simultaneously controls the enabling of the double-path delay unit of the multi-channel detector, so that the (narrow pulse) gating signal is generated again, and all the detection channels of the multi-channel detector simultaneously exit from the dead time state. Wherein the difference between different detection channels is particularly considered, and an action time range for dead time synchronization control of the multi-channel gating detector is provided, so that the consistency of the detection efficiency of a plurality of detection channels is ensured.

Description

Technical Field

[0001] The present invention relates to the field of quantum technology, and more particularly to a method for defending against dead-time attacks of gated detectors in a QKD system, and a detection module for defending against dead-time attacks of gated detectors implemented thereby. Background Art

[0002] A quantum key distribution (QKD) system consists of multiple components. A single-photon detector is a very important component among them. Its manufacturing principle makes it have some potential risks of being attacked. Taking Figure 1 a typical receiving-end decoding detection module structure of a polarization-coded QKD system based on the decoy-state BB84 protocol shown as an example, after the optical pulse signal containing four polarization states H, V, P, and N prepared by the sending end is transmitted through the optical fiber channel and reaches the receiving end, the random basis selection is completed through the beam splitter in the decoding detection module, and then it passes through the polarization controller and the polarization beam splitter and reaches the H, V, P, and N four-channel single-photon detectors.

[0003] According to the BB84 protocol, when the sending end and the receiving end complete the calibration of the polarization state detection link using the polarization controller, the probabilities of the optical pulse signal with the polarization state of |H> reaching the H, V, P, and N four-channel single-photon detectors after passing through the beam splitter and the polarization beam splitter will be close to 50%, 0%, 25%, and 25% respectively, and the same is true for the other three polarization states.

[0004] There are many types of detectors for realizing single-photon detection. Practical QKD systems mostly use single-photon avalanche photodiodes (APDs) to realize single-photon detection. To successfully detect the extremely weak single-photon signal received, the APD must work in the Geiger mode to obtain a sufficiently high gain. In the Geiger mode, when a photon is detected incident, an avalanche current will be generated in the APD and continue spontaneously. Being in the avalanche state for a long time will affect the service life and stability of the APD. Therefore, after triggering an avalanche once, the reverse bias voltage of the APD needs to be reduced below the avalanche voltage by an active or passive method to exit the Geiger mode and quench the avalanche current. In addition, the carriers generated during the APD avalanche process are trapped due to defects and impurities in the multiplication layer and then released with a delay, resulting in a small amount of additional avalanche signals (i.e., afterpulse effect), which will cause false counting and reduce the secure key generation rate of the QKD system. For this reason, after each successful detection of an optical pulse, the reverse bias voltage of the APD needs to be reduced below the avalanche voltage and maintained for a period of time to force the APD to exit the Geiger mode and enter the linear mode. At this time, a single-photon incidence will not be able to trigger an effective detection signal. This period of time is called the dead time, and the time length is generally from dozens of nanoseconds to dozens of microseconds.

[0005] The dead time attack makes use of the dead time effect of the above-mentioned single-photon detector. The attacker injects a strong pulsed light with a fixed polarization (e.g., |H>-state polarized light) into the optical fiber channel before the real optical pulse signal, triggering detections in three of the four detectors H, V, P, and N (except for the target detector, e.g., the V-channel detector) with a high probability and causing them to be in the dead time and blinded. Only the target detector remains in the normal response mode. Based on this, the attacker can control the response of the detectors at the receiving end. If a detection event occurs at the receiving end at this time, the attacker can accurately judge the detection result at the receiving end. Since the key data mapped by each detector is fixed, the attacker can successfully steal the key data.

[0006] In the QKD system, the prevention of dead time attacks requires that all channel detectors "enter the dead time simultaneously and exit the dead time simultaneously" to close the dead time attack vulnerability. As Figure 2 shown, for the dead time attack, in an existing defense scheme, a software dead time synchronization scheme is adopted. First, a software dead time duration is set at the receiving end. By the period in which the detection event occurs, if it is within the defined software dead time region, it is called the invalid detection time, and if it is outside the defined software dead time region, it is called the valid detection time. The valid and invalid detection times are distinguished in terms of time. The detection events in the valid detection time are retained, and whether to extend the dead time of the detector is determined according to the detection events in the invalid detection time. It is a software-based dynamic dead time scheme based on detection event judgment.

[0007] This software-based attack defense scheme does not consider the mechanism for controlling the dead time of different types of detectors. During the dead time judgment period, the detector working mode is not switched to the linear mode, and the detector can still perform single-photon detection. During the actual dead time period, multi-channel detectors can continuously respond to single-photon detection. During the multi-channel dead time synchronization process, the duration of the detector's dead time will be not fixed and will be continuously extended dynamically, reducing the effective count of the detector and thus reducing the key generation rate of the QKD system.

[0008] In another existing defense scheme, a scheme for implementing dead time synchronization control based on hardware is proposed, but it does not consider the problem of the consistency of the detection efficiency of multi-channel detectors. Summary of the Invention

[0009] In view of the above deficiencies of the prior art, the present invention proposes a method for defending against dead-time attacks of gated detectors in a QKD system, and a detection module for defending against dead-time attacks of gated detectors implemented thereby. After an avalanche signal is detected and generated in any one of the detection channels, the control unit simultaneously controls the two-channel delay units of the multi-channel detector to be disabled, so that no (narrow pulse) gating signal is generated anymore, and thus all detection channels of the multi-channel detector simultaneously enter the dead-time state. When the dead time ends, the control unit simultaneously controls the two-channel delay units of the multi-channel detector to be enabled, so that the (narrow pulse) gating signal is generated again, and thus all detection channels of the multi-channel detector simultaneously exit the dead-time state. Among them, the differences between different detection channels are particularly considered, and an action time range for dead-time synchronization control of the multi-channel gated detector is provided, thereby ensuring the consistency of the detection efficiency of multiple detection channels.

[0010] Specifically, a first aspect of the present invention relates to a method for defending against dead-time attacks of gated detectors, which includes an avalanche signal monitoring step and a dead-time control step:

[0011] The avalanche signal monitoring step is used to monitor whether an avalanche signal is generated by the multi-channel gated detector;

[0012] The dead-time control step is used to send a dead-time control signal for making the multi-channel gated detector enter the dead-time state when an avalanche signal is detected in any channel i of the multi-channel gated detector;

[0013] Among them, the duration of the dead-time control signal is set according to a preset dead-time length, and the start time of the dead-time control signal is between the falling edge of the latest gating signal of the multi-channel gated detector in the current detection period and the rising edge of the earliest gating signal of the multi-channel gated detector in the next detection period, and the end time of the dead-time control signal is between the falling edge of the latest gating signal of the multi-channel gated detector in the detection period before the end of the dead-time state and the rising edge of the earliest gating signal of the multi-channel gated detector in the detection period after the end of the dead-time state.

[0014] Furthermore, the control unit is used to monitor whether an avalanche signal is generated by the multi-channel gated detector.

[0015] Still further, an avalanche signal extraction unit in the multi-channel gated detector is used to generate a detection pulse signal according to the avalanche signal output by the single-photon avalanche photodiode; and,

[0016] The control unit determines whether an avalanche signal is generated by the multi-channel gated detector by monitoring the detection pulse signal.

[0017] Further, the multi-channel gated detector includes multiple single-photon avalanche photodiodes, and corresponding multiple dual-channel delay units and multiple AND gate logic units;

[0018] The dual-channel delay unit is used to output two signals to the AND gate logic unit;

[0019] The AND gate logic unit is used to send a gating signal to the single-photon avalanche photodiode by means of the AND operation of the two signals; and,

[0020] The dead time control signal is used to disable the dual-channel delay unit.

[0021] Further, the dead time control signal is timed by the dead time timing working clock, and the dead time timing working clock is homologous to the clock signal used for the gating signal. Among them, the dead time control signal can be generated by controlling the enable signal for the dual-channel delay unit.

[0022] The second aspect of the present invention relates to a detection module for defending against dead time attacks of a gated detector for a QKD system, which includes a control unit and a multi-channel gated detector;

[0023] The control unit is configured to send a dead time control signal for making it enter the dead time state to the multi-channel gated detector when it monitors that any channel i in the multi-channel gated detector generates an avalanche signal;

[0024] Among them, the duration of the dead time control signal is set according to a preset dead time length, and the start time of the dead time control signal is between the falling edge of the latest gating signal in the current detection period of the multi-channel gated detector and the rising edge of the earliest gating signal in the next detection period of the multi-channel gated detector, and the end time of the dead time control signal is between the falling edge of the latest gating signal in the detection period before the end of the dead time state of the multi-channel gated detector and the rising edge of the earliest gating signal in the detection period after the end of the dead time state of the multi-channel gated detector.

[0025] Further, the multi-channel gated detector includes multiple single-photon avalanche photodiodes, and corresponding multiple dual-channel delay units, multiple AND gate logic units and multiple avalanche signal extraction units;

[0026] The dual-channel delay unit is used to output two signals to the AND gate logic unit;

[0027] The AND gate logic unit is used to send a gating signal to the single-photon avalanche photodiode by means of the AND operation of the two signals;

[0028] The avalanche signal extraction unit is used to generate a detection pulse signal according to the avalanche signal output by the single-photon avalanche photodiode; and,

[0029] The control unit is configured to monitor the detection pulse signal.

[0030] Furthermore, the detection module of the present invention may further include a clock signal generation module for simultaneously providing clock signals to the control unit and the multi-channel gated detector.

[0031] Preferably, the control unit is configured to control the multi-channel gated detector to enter or exit the dead time state by using the method for defending against the dead time attack of the gated detector as described above. Description of the Drawings

[0032] Figure 1 Schematically shows a typical receiving-end decoding detection module structure of a polarization-coded QKD system based on the decoy-state BB84 protocol in the prior art;

[0033] Figure 2 Schematically shows a dead time attack defense scheme implemented based on software in the prior art;

[0034] Figure 3 Schematically shows a circuit schematic diagram of an example of a detection module capable of defending against the dead time attack of a gated detector according to the present invention;

[0035] Figure 4 Shows an example of a main flowchart of a method for defending against the dead time attack of a gated detector according to the present invention;

[0036] Figure 5 Schematically shows an example of a signal timing diagram for entering the dead time state in the method for defending against the dead time attack of a gated detector according to the present invention;

[0037] Figure 6 Schematically shows an example of the action time range for entering the dead time state according to the present invention;

[0038] Figure 7 Schematically shows an example of the action time range for exiting the dead time state according to the present invention. Detailed Description of the Embodiments

[0039] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example to fully convey the spirit of the present invention to those skilled in the art to which the present invention pertains. Therefore, the present invention is not limited to the embodiments disclosed herein.

[0040] Figure 3 Shows a circuit schematic diagram of an example of a detection module capable of defending against the dead time attack of a gated detector according to the present invention.

[0041] As Figure 3As shown, the detection module of the present invention may include a clock signal generation module, a multi-channel gated detector, and a control unit. Among them, the control unit may be a programmable chip such as an FPGA, a DSP, or an ARM. In this embodiment, the FPGA unit is taken as an example for illustration.

[0042] The clock signal generation module is used to provide a homologous clock signal for the FPGA unit and the multi-channel gated detector.

[0043] In the present invention, the clock signal generation module may include a phase-locked loop, as well as a plurality of single-channel delay units and a plurality of dual-channel buffer distribution units corresponding to the number of detection channels of the detector. For example, in Figure 3 the example of

[0044] When applied to a 4-channel gated detector, 4 single-channel delay units and 4 dual-channel buffer distribution units can be correspondingly configured in the clock signal generation module. The phase-locked loop is used to utilize the input clock signal (such as 100KHz) to output a plurality of (such as 5) working clock signals through phase-locked frequency multiplication. The frequencies of these working clock signals are adapted to the working frequency of the gated detector (such as 40MHz). Among them, one of the clock signals output by the phase-locked loop will be provided to the FPGA unit as the working clock for dead time counting (such as 40MHz_DeadTime_clk); the other (such as 4) clock signals will be processed by the corresponding single-channel delay units and dual-channel buffer distribution units respectively, and then the dual-channel buffer distribution unit will output two homologous clock signals to the corresponding detection channels as the clock signals for the gating signals of the detection channels.

[0045] The multi-channel gated detector is used to detect optical signals. Each detection channel may include a corresponding APD, a plurality of dual-channel delay units, an AND logic unit, and an avalanche signal extraction unit.

[0046] The APD is used to generate an avalanche signal in response to the input optical signal.

[0047] The avalanche signal extraction unit is used to generate a detection pulse signal according to the avalanche signal output by the APD so as to allow the FPGA unit to identify.

[0048] The dual-channel delay unit is used to output two signals to the AND logic unit. As an example, the dual-channel delay unit can set different delays for the two output signals, for example, controlling the delay difference between the two signals to be 1ns.

[0049] In the present invention, the dual-channel delay unit can be in an enabled or disabled state based on the control of the enable signal, and output / not output signals.

[0050] For example, in Figure 3In the example, the DeadTime_EN_X signal is the enable signal for the dual-channel delay unit for detecting channel X, where: when the DeadTime_EN_X signal is at a low level, the dual-channel delay unit is not enabled, and at this time, the dual-channel delay unit has no output; when the DeadTime_EN_X signal is at a high level, the dual-channel delay unit is enabled, and at this time, the dual-channel delay unit outputs two delay signals.

[0051] The AND logic unit is used to perform an "AND" operation on the two signals provided by the dual-channel delay unit to output and load a gating signal (for example, in the form of a narrow pulse) to the corresponding APD. As an example, the AND logic unit can be implemented by means of a high-speed AND gate circuit.

[0052] The FPGA unit is used to send a dead time control signal to the multi-channel gating detector when it detects that any detection channel i in the multi-channel gating detector generates an avalanche signal (for example, receives a detection pulse signal corresponding to detection channel i), so as to control all detection channels of the multi-channel gating detector to enter the dead time state simultaneously.

[0053] For example, in Figure 3 In the example, the dead time control signal can be generated by setting the enable signal DeadTime_EN_X to a low level, so that the dual-channel delay unit is not enabled when receiving the dead time control signal, that is, there is no output.

[0054] To better understand the working principle of the detection module of the present invention, the method for defending against dead time attacks of the gating detector of the present invention will be further described below in conjunction with Figures 4-7 The method can ensure that multiple detection channels in the multi-channel gating detector have consistent detection efficiency while implementing dead time control of the gating detector based on hardware.

[0055] Figure 4 Fig. shows an example of the main flowchart of the method for defending against dead time attacks of the gating detector according to the present invention.

[0056] According to the present invention, the method for defending against dead time attacks of the gating detector may include an avalanche signal monitoring step and a dead time control step.

[0057] The avalanche signal monitoring step is used to monitor whether the multi-channel gating detector generates an avalanche signal by using the FPGA unit in the normal detection state. For example, the FPGA unit monitors whether it receives a detection pulse signal output from any detection channel i in the detector.

[0058] When an avalanche signal is detected during the avalanche signal monitoring step, for example, when the FPGA unit receives a detection pulse signal corresponding to a certain detection channel i, the dead time control step can be used to provide a dead time control signal to the detector to switch all detection channels of the multi-channel gated detector from the normal detection state to the dead time state, and switch all detection channels back to the normal detection state when the dead time control signal ends.

[0059] In the present invention, the duration of the dead time control signal can be set according to the dead time length preset in the FPGA unit.

[0060] As Figure 4 shown in the example of, in the dead time control step, the FPGA unit can set the enable signal DeadTime_EN_X to a low level and provide it to the multi-channel gated detector as the dead time control signal; under the action of this dead time control signal, all dual-channel delay units in the multi-channel gated detector are disabled and have no output, and then all AND logic units no longer generate (narrow pulse) gating signals, so that the reverse voltage across all APDs is lower than the avalanche voltage, and the APD enters the linear mode and no longer responds to single-photon signals, and the multi-channel gated detector enters the dead time state.

[0061] Subsequently, the FPGA unit starts timing the dead time state based on the dead time timing working clock. When the preset dead time length timing ends, the FPGA unit can set the enable signal DeadTime_EN_X to a high level and stop providing the dead time control signal to the multi-channel gated detector, that is, the dead time control signal ends. At this time, all dual-channel delay units in the multi-channel gated detector are enabled to output two delay signals, and then all AND logic units generate (narrow pulse) gating signals, so that the reverse voltage across all APDs is higher than the avalanche voltage, the APD enters the Geiger mode and can normally respond to single-photon signals, and all detection channels of the multi-channel gated detector simultaneously exit the dead time state and enter the normal detection state.

[0062] Thus, the switching between the dead time state and the normal detection state of all detection channels of the multi-channel gated detector is realized simultaneously by means of the hardware circuit.

[0063] Figure 5Schematically shown is an example of the signal timing diagram when entering the dead time state in the method for defending against dead time attacks of the gated detector of the present invention, where: DetGate_X is the (narrow pulse) gating signal of detection channel X of the gated detector; the dashed area is the area where no (narrow pulse) gating signal is generated under the action of the dead time control signal; DetPulse_X is the detection pulse signal corresponding to detection channel X; DeadTime_Clk is the dead time timing working clock for dead time counting; DeadTime_En_X is the dead time control signal of detection channel X.

[0064] Furthermore, in the process of dead time control of the multi-channel gated detector, the present invention particularly proposes the concept of setting the action time range for entering the dead time state and the action time range for exiting the dead time state, thereby overcoming the problem that the detection efficiencies of each detection channel may be inconsistent in the dead time control process due to the delay difference between the gating signals of multiple detection channels of the multi-channel gated detector not being considered in the existing solutions.

[0065] As described above, when the detection pulse signal is first generated in a certain detection channel i in the gated detector, it is necessary to make all detection channels in the gated detector enter the dead time state simultaneously. In this process, the following two times need to be considered, namely:

[0066] (1) Time T1, which is the interval duration between the generation moment of the detection pulse signal of detection channel i and the rising edge of the next gating signal in detection channel i. Therefore, it is necessary to complete the action of entering the dead time state within time T1 and turn off the gating signal of the next detection cycle.

[0067] (2) Time T2, which is the interval duration between the generation moment of the detection pulse signal of detection channel i and the falling edge of the latest gating signal in the multi-channel gated detector in the current detection cycle. Therefore, within time T2, the action of entering the dead time state simultaneously cannot be performed to avoid the gating signals of different detection channels being suppressed by the dead time, resulting in inconsistent detection efficiencies of different detection channels.

[0068] Based on the above analysis, it can be concluded that in order to avoid inconsistent detection efficiencies of multiple detection channels, the action time range for entering the dead time state that allows the action of entering the dead time state simultaneously can be set to be between after time T2 and before the end of time T1. Therefore, the starting time of the dead time control signal can be set to be between the falling edge of the latest gating signal in the multi-channel gated detector in the current detection cycle and the rising edge of the earliest gating signal in the multi-channel gated detector in the next detection cycle.

[0069] Figure 6Schematically shows an example of entering the action time range from the dead time state according to the present invention, taking the simultaneous entry of a 4-channel gated detector into the dead time state as an example.

[0070] As Figure 6 shown, when the detection pulse signal DetPulse_1 is first generated in detection channel 1 (based on the gated signal DetGate_1), time T1 is the interval duration between the generation moment of the detection pulse signal DetPulse_1 and the rising edge of the next gated signal in detection channel 1, and T2 is the interval duration between the generation moment of the detection pulse signal DetPulse_1 and the latest gated signal DetGate_4 within the current detection period. At this time, the entry action time range from the dead time state can be set within the time range of ΔT1 = T1 - T2, that is, the FPGA unit can set the enable signal DeadTime_En_X to a low level within this time range to generate a dead time control signal.

[0071] Similarly, when all detection channels of the gated detector are to exit the dead time state simultaneously, to ensure that the detection efficiency of all detection channels in the two detection periods before and after the exit is consistent, it is necessary to make all detection channels be in the non-open state before the end of the dead time state and in the open state after the end of the dead time state. For this purpose, the end time of the dead time control signal can be set to be between the falling edge of the latest gated signal in the detection period before the end of the dead time state of the multi-channel gated detector and the rising edge of the earliest gated signal in the detection period after the end of the dead time state of the multi-channel gated detector, thereby completing the setting of the exit action time range from the dead time state.

[0072] Figure 7 Schematically shows an example of the exit action time range from the dead time state according to the present invention, which corresponds to Figure 6 the example of

[0073] As Figure 7 shown, the exit action from the dead time state can be set to be between the falling edge of the latest gated signal in the detection period before the end of the dead time state of the multi-channel gated detector and the rising edge of the earliest gated signal in the detection period after the end of the dead time state of the multi-channel gated detector, that is, the exit action time range from the dead time state is set within the time range of ΔT2. Therefore, the FPGA unit can set the enable signal DeadTime_En_X to a high level within this time range to stop providing the dead time control signal.

[0074] In summary, for the receiving end of a QKD system that includes a multi-channel gated detector, the present invention proposes a hardware-implemented dead time control scheme. After an avalanche signal is detected in any one of the detection channels, the control unit simultaneously controls the two-channel delay units of the multi-channel detector to be disabled, so that no (narrow pulse) gating signal is generated, thereby causing all detection channels of the multi-channel detector to enter the dead time state simultaneously; when the dead time ends, the control unit simultaneously controls the two-channel delay units of the multi-channel detector to be enabled, so that the (narrow pulse) gating signal is generated again, thereby causing all detection channels of the multi-channel detector to exit the dead time state simultaneously. Thus, in the solution of the present invention, the multi-channel detector can be turned off to the linear mode simultaneously, and restored from the linear mode to the Geiger mode simultaneously, and the dead time length is fixed. The dead time length does not change with the communication distance of the QKD system, the detector count size, etc., and can improve the effective counting rate of the detector and the performance of the QKD system. Among them, the differences between different detection channels are particularly considered, and an action time range for dead time synchronization control of the multi-channel gated detector is provided, thereby ensuring the consistency of the detection efficiency of multiple detection channels.

[0075] In addition, the solution proposed by the present invention does not require an increase in hardware cost, has a simple design and is easy to implement in engineering, and does not reduce the performance of the QKD system. It is particularly suitable for the synchronous dead time control of multi-channel gated detectors and does not limit parameters such as the detector gating frequency, the number of channels, and the gate width. And although the above mainly describes that the solution of the present invention is applicable to the defense against dead time attacks at the detection end of the QKD system, those skilled in the art can understand that the present invention can also be used for independent dead time control or synchronous control requirements in other scenarios.

[0076] Although the present invention has been described above in conjunction with specific embodiments with reference to the accompanying drawings, it is easy for those skilled in the art to recognize that the above embodiments are merely exemplary and are used to illustrate the principle of the present invention, which will not limit the scope of the present invention. Those skilled in the art can make various combinations, modifications, and equivalent replacements of the above embodiments without departing from the spirit and scope of the present invention.

Claims

1. A method for defending against dead-time attacks of a gated detector, which includes an avalanche signal monitoring step and a dead-time control step: The avalanche signal monitoring step is used to monitor whether an avalanche signal is generated by a multi-channel gated detector; The dead-time control step is used to send a dead-time control signal for making the multi-channel gated detector enter the dead-time state when it is monitored that any channel i in the multi-channel gated detector generates an avalanche signal; Among them, Set the duration of the dead-time control signal according to a preset dead-time length, and the start time of the dead-time control signal is between the falling edge of the latest gating signal in the current detection cycle of the multi-channel gated detector and the rising edge of the earliest gating signal in the next detection cycle of the multi-channel gated detector, and the end time of the dead-time control signal is between the falling edge of the latest gating signal in the detection cycle before the end of the dead-time state of the multi-channel gated detector and the rising edge of the earliest gating signal in the detection cycle after the end of the dead-time state of the multi-channel gated detector.

2. The method for defending a gated detector against dead time attacks as claimed in claim 1, wherein, Use a control unit to monitor whether an avalanche signal is generated by a multi-channel gated detector.

3. The method for defending against dead time attacks of a gated detector as claimed in claim 2, wherein, Use an avalanche signal extraction unit in the multi-channel gated detector to generate a detection pulse signal according to the avalanche signal output by a single-photon avalanche photodiode; And, The control unit determines whether an avalanche signal is generated by the multi-channel gated detector by monitoring the detection pulse signal.

4. The method for defending a gated detector against dead time attacks as described in claim 1, wherein, The multi-channel gated detector includes multiple single-photon avalanche photodiodes and corresponding multiple two-way delay units and multiple AND logic units; The two-way delay unit is used to output two signals to the AND logic unit; The AND logic unit is used to send a gating signal to the single-photon avalanche photodiode by means of an AND operation of the two signals; and, Use the dead-time control signal to make the two-way delay unit in a disabled state.

5. The method for defending against dead time attacks of a gated detector as claimed in claim 1, wherein, Use a dead-time timing working clock to time the dead-time control signal, and the dead-time timing working clock is homologous to the clock signal for the gating signal.

6. The method for defending against dead time attacks of a gated detector as claimed in claim 4, wherein, Generate a dead-time control signal by controlling the enable signal for the two-way delay unit.

7. A detection module for defending against dead-time attacks of a gated detector for a QKD system, which includes a control unit and a multi-channel gated detector; The control unit is configured to send a dead-time control signal for making the multi-channel gated detector enter the dead-time state when it is monitored that any channel i in the multi-channel gated detector generates an avalanche signal; Among them, Set the duration of the dead-time control signal according to a preset dead-time length, and the start time of the dead-time control signal is between the falling edge of the latest gating signal in the current detection cycle of the multi-channel gated detector and the rising edge of the earliest gating signal in the next detection cycle of the multi-channel gated detector, and the end time of the dead-time control signal is between the falling edge of the latest gating signal in the detection cycle before the end of the dead-time state of the multi-channel gated detector and the rising edge of the earliest gating signal in the detection cycle after the end of the dead-time state of the multi-channel gated detector.

8. The detection module according to claim 7, wherein The multi-channel gated detector includes multiple single-photon avalanche photodiodes and corresponding multiple two-way delay units, multiple AND logic units and multiple avalanche signal extraction units; The dual-channel delay unit is used to output two signals to the AND logic unit; The AND logic unit is used to send a gating signal to the single-photon avalanche photodiode by means of the AND operation of the two signals; The avalanche signal extraction unit is used to generate a detection pulse signal according to the avalanche signal output by the single-photon avalanche photodiode; And, The control unit is arranged to monitor the detection pulse signal.

9. The detection module according to claim 7, further comprising a clock signal generation module for simultaneously providing a clock signal for the control unit and the multi-channel gating detector.

10. The detection module according to claim 7, wherein, The control unit is arranged to control the multi-channel gating detector to enter or exit the dead time state by using the method for defending against the dead time attack of the gating detector according to any one of claims 1-6.

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