GPU test device and GPU test system comprising same

Abstract

The embodiment of the invention provides a GPU test device and a GPU test system comprising the same. The device comprises at least one first test chip and at least one first connector in communication connection with the first test chip, wherein the first connector comprises at least one first pin for transmitting a first to-be-tested signal; each first pin is in communication connection with a second pin on the substrate; the first to-be-tested signal comprises a to-be-tested SERDES signal; the second pin receives a to-be-tested SERDES signal sent by the first to-be-tested system, and sends the to-be-tested SERDES signal to the first test chip through the first pin; the first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested; wherein the first to-be-tested system determines the connectivity of the SERDES link between the first to-be-tested system and the GPU based on the first feedback signal, so that the GPU testing device can be used for testing the connectivity of the SERDES link between the first to-be-tested system and the GPU.

Description

Technical Field

[0001] This application relates to the field of computers, and particularly to a GPU testing device and a GPU testing system including the device. Background Art

[0002] In order to ensure the compatibility between an electronic device or an electronic module and a Graphics Processing Unit (GPU), before the GPU is installed in the electronic device or the electronic module, it is necessary to test the link connectivity between the electronic device or the electronic module and the GPU.

[0003] In the related art, a GPU verification device can be used to replace the actual GPU to test the link connectivity between the electronic device or the electronic module and the GPU.

[0004] However, the GPU verification device cannot complete the test of the SERDES link connectivity between the electronic device or the electronic module and the GPU. Summary of the Invention

[0005] An embodiment of this application provides a GPU testing device and a GPU testing system including the device, so as to achieve the effect that the device can be used to test the SERDES link connectivity between an electronic device or an electronic module and a GPU.

[0006] In a first aspect, an embodiment of this application provides a GPU testing device. The GPU testing device is communicatively connected to a substrate. The GPU testing device includes:

[0007] At least one first test chip and at least one first connector communicatively connected to the first test chip. The first connector includes at least one first pin for transmitting a first signal to be tested. Each first pin is communicatively connected to a second pin on the substrate. The first signal to be tested includes a SERDES signal to be tested.

[0008] The second pin receives the SERDES signal to be tested sent by a first system to be tested, and sends the SERDES signal to be tested to the first test chip through the first pin.

[0009] The first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested. Wherein, the first system to be tested determines the connectivity of the SERDES link between the first system to be tested and the GPU based on the first feedback signal.

[0010] In a possible implementation, the first test chip generates a first feedback signal for the SERDES signal to be tested and sends the first feedback signal to the first system to be tested, including:

[0011] The first test chip generates the first feedback signal by performing self-loopback on the SERDES signal to be tested;

[0012] The first test chip sends the first feedback signal to the first system to be tested through the SERDES signal path formed by the first pin and the second pin.

[0013] In a possible implementation, it further includes: at least one second connector communicatively connected to the first test chip;

[0014] The second connector is communicatively connected to a first cable through a signal conversion module, and the first cable is connected to the first system to be tested;

[0015] And the first test chip sends the first feedback signal to the first system to be tested, including:

[0016] The first test chip sends the first feedback signal to the first system to be tested through the SERDES signal path formed by the second connector, the signal conversion module, and the first cable.

[0017] In a possible implementation, the signal conversion module includes a hot-swappable optical module.

[0018] In a possible implementation, the SERDES signal to be tested is obtained by encoding a first data packet to be tested acquired by the first system to be tested;

[0019] The first system to be tested determines the connectivity of the SERDES link between the first system to be tested and the GPU based on the first feedback signal, including:

[0020] The first system to be tested decodes the first feedback signal to obtain a first data packet to be verified;

[0021] If the first data packet to be verified is consistent with the expected data packet of the first data packet to be tested, the first system to be tested determines that the SERDES link between the first system to be tested and the GPU is connected.

[0022] In a possible implementation, it further includes: at least one second test chip, wherein each of the second test chips is communicatively connected to at least one third pin on the substrate through the first connector;

[0023] The at least one third pin receives a second signal to be tested sent by at least one second system to be tested, and sends the second signal to be tested to the corresponding second test chip;

[0024] The second test chip generates a second feedback signal according to the second signal to be tested, and sends the second feedback signal to the second system to be tested, so that the second system to be tested determines the connectivity of the link for transmitting the second signal to be tested between the second system to be tested and the GPU based on the second feedback signal.

[0025] In a possible implementation manner, the second signal to be tested includes one or more of a PCIE link test signal, a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

[0026] In a possible implementation manner, the first test chip includes a retimer;

[0027] The second test chip includes: a PCIE endpoint device simulation chip for receiving a PCIE link test signal, and / or a complex programmable logic device for receiving a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

[0028] In a possible implementation manner, the first system to be tested and the second system to be tested include:

[0029] Different functional modules located on the same server;

[0030] Or, different functional modules located on different servers.

[0031] In a second aspect, an embodiment of the present application provides a GPU test system, including: at least one first system to be tested, at least one second system to be tested, a substrate, and a plurality of GPU test devices as described in the first aspect and / or various possible implementations of the first aspect;

[0032] Wherein, the plurality of GPU test devices, each of the first systems to be tested, and each of the second systems to be tested are respectively communicatively connected to the substrate.

[0033] An embodiment of the present application provides a GPU test device and a GPU test system including the device. The GPU test device includes at least one first test chip and at least one first connector communicatively connected to the first test chip. The first connector includes at least one first pin for transmitting a first signal to be tested. Each first pin is communicatively connected to a second pin on a substrate. The first signal to be tested includes a SERDES signal to be tested. The second pin receives the SERDES signal to be tested sent by a first system to be tested, and sends the SERDES signal to be tested to the first test chip through the first pin. The first test chip generates a first feedback signal for the SERDES signal to be tested and sends the first feedback signal to the first system to be tested. Wherein, the first system to be tested determines the connectivity of the SERDES link between the first system to be tested and the GPU based on the first feedback signal.

[0034] Since the first system to be tested, the second pin, and the first pin and the first test chip in the GPU test device form a path for the SERDES signal, the GPU test device can be used to test the connectivity of the SERDES link between the first system to be tested and the GPU. Description of the Drawings

[0035] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0036] Figure 1 It is a schematic structural diagram of a connection between a first system to be tested and a GPU test device provided by the present application;

[0037] Figure 2 It is a schematic structural diagram of a GPU test device provided by the present application;

[0038] Figure 3 It is a schematic structural diagram of a connection between a first system to be tested and a second system to be tested and a GPU test device respectively provided by the present application;

[0039] Figure 4 It is another schematic structural diagram of a GPU test device provided by the present application;

[0040] Figure 5 It is a schematic structural diagram of a GPU test system provided by the present application.

[0041] Description of the Reference Numerals:

[0042] 1. GPU test device; 2. Substrate; 3. First system to be tested; 4. Signal conversion module; 5. First cable; 6. Second system to be tested;

[0043] 11. First test chip; 12. First connector; 13. Second connector; 14. Second test chip;

[0044] 21. Connector;

[0045] 1211. First pin; 1212. First pin; 1213. First pin; 1214. First pin; 1215. First pin; 1216. First pin; 1217. First pin;

[0046] 1221. PCIE pin;

[0047] 1231. Low-speed signal pin; 1232. Low-speed signal pin; 1233. Low-speed signal pin; 1234. Low-speed signal pin; 1235. Low-speed signal pin; 1236. Low-speed signal pin.

[0048] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. Detailed Description of the Embodiment

[0049] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] First, the terms involved in the present application are explained:

[0051] SERDES (Serializer / Deserializer, abbreviated as SERDES): It is a high-speed serial communication technology used to convert parallel data into high-speed serial data and convert the high-speed serial data back into parallel data at the receiving end;

[0052] PCIE (Peripheral Component Interconnect Express, abbreviated as PCIE): It is a high-speed serial computer expansion bus standard;

[0053] Physical Layer Retimer (PHY Retimer): A signal conditioning device for the physical layer, specifically designed for high-speed serial communication interfaces to extend the transmission distance, improve signal integrity, and reduce the bit error rate. The retimer has a self-loopback function. Among them, the self-loopback function is used to return the data packet received from the receiving end (Rx) to the receiving end (Rx) of the same retimer.

[0054] Complex Programmable Logic Device (CPLD): A programmable logic device that can be used to implement digital circuit functions;

[0055] Inter-Integrated Circuit (I2C): A two-way two-wire serial bus that can be used for short-distance communication between low-speed peripherals on the same circuit board;

[0056] Universal Asynchronous Receiver-Transmitter (UART): A universal asynchronous transceiver that can be used for point-to-point serial communication between two devices;

[0057] Joint Test Action Group (JTAG): A standardized interface and protocol;

[0058] Octal Small Form Factor Pluggable (OSFP module): A module for high-speed optical communication that can be used for high-speed interconnection in data centers and high-performance computing networks. The OSFP module has optoelectronic conversion functions, that is, converting electrical signals into optical signals (transmitting end) and converting optical signals into electrical signals (receiving end). The OSFP module can enhance signal integrity and anti-interference ability during signal transmission, and supports hot pluggability, facilitating maintenance and upgrade.

[0059] As GPUs are being updated more and more rapidly, it is necessary to develop a GPU test device to verify the link connectivity between the system under test and the GPU.

[0060] Using the GPU verification device provided by related technologies to verify the connectivity between the GPU and the system cannot achieve the test of the SERDES link connectivity between the GPU and the system.

[0061] This application provides a GPU test device and a GPU test system including the device to solve the above technical problems.

[0062] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below with reference to the accompanying drawings.

[0063] Figure 1 It is a schematic structural diagram of a connection between a first system to be tested and a GPU test device provided by the present application. As Figure 1 shown, the GPU test device 1 is communicatively connected to the substrate 2; the GPU test device 1 includes at least one first test chip 11 and at least one first connector 12 communicatively connected to the first test chip 11, and the first connector 12 includes at least one first pin for transmitting a first signal to be tested; each first pin is communicatively connected to a second pin on the substrate 2; the first signal to be tested includes a SERDES signal.

[0064] The second pin receives the SERDES signal to be tested sent by the first system to be tested 3, and sends the SERDES signal to be tested to the first test chip 11 through the first pin;

[0065] The first test chip 11 generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested 3; wherein, the first system to be tested 3 determines the connectivity of the SERDES link between the first system to be tested 3 and the GPU based on the first feedback signal.

[0066] In one example, the first system to be tested 3 includes different functional modules located on the same server; or different functional modules located on different servers.

[0067] In one example, the first test chip 11 includes a retimer.

[0068] In one example, the first test chip 11 generates a first feedback signal for the SERDES signal to be tested and sends the first feedback signal to the first system to be tested 3, including: the first test chip 11 generates a first feedback signal by performing self-loopback on the SERDES signal to be tested; the first test chip sends the first feedback signal to the first system to be tested 3 through the SERDES signal path formed by the first pin and the second pin.

[0069] In one example, the SERDES signal to be tested is obtained by encoding the first data packet to be tested acquired by the first system to be tested 3. The first system to be tested 3 determines the connectivity of the SERDES link between the first system to be tested 3 and the GPU based on the first feedback signal, including the following process:

[0070] The first system to be tested 3 decodes the first feedback signal to obtain a first data packet to be verified;

[0071] If the first data packet to be verified is consistent with the expected data packet of the first data packet to be tested, the first system to be tested 3 determines that the SERDES link between the first system to be tested 3 and the GPU is connected.

[0072] Exemplarily, Figure 2 is a schematic structural diagram of a GPU testing device provided by the present application, as Figure 2 shown, the GPU testing device 1 may include 4 first test chips 11 and 2 first connectors 12 soldered on a single board. Among them, each first test chip 11 is connected to the first connector 12 through PCB traces on the single board. The single board is, for example, a printed circuit board (Printed Circuit Board, abbreviated as PCB).

[0073] The first connector 12 may include, for example, but not limited to, one of a mirror mezzanine connector, a board-to-board connector, etc. The type of the first connector 12 is not limited in this embodiment, as long as it can achieve the same function as the connector in the GPU for testing connectivity with the first system to be tested 3.

[0074] As Figure 2 shown, each of the first pins 1211, 1212, 1213, 1214, 1215, 1216, 1217 corresponds to a SERDES link. Each first pin can be used for single-channel transmission of SERDES signals or multi-channel transmission of SERDES signals. Each first pin may include at least two pairs of physical pins, and each two pairs of physical pins correspond to one channel; among them, a pair of physical pins for transmitting differential signals (for example, TX+ pin and TX- pin) corresponding to one channel can be used to transmit SERDES signals, and another pair of physical pins for receiving differential signals (for example, RX+ pin and RX- pin) can be used to receive SERDES signals.

[0075] The number of physical pins in each first pin is not limited in this embodiment, as long as the physical pins corresponding to one channel can be used to transmit SERDES signals and / or receive SERDES signals.

[0076] When transmitting SERDES signals in multiple channels, there may be two possible implementation manners:

[0077] In the first possible implementation, the transmitting end may first cut the SERDES signal into multiple SERDES slice signals, then independently transmit each SERDES slice signal in parallel through multiple different channels, and finally recombine each SERDES slice signal at the receiving end to obtain the SERDES signal;

[0078] In another possible implementation, the transmitting end may independently transmit different SERDES signals in parallel through multiple different channels.

[0079] Therefore, when the first pin is used for multi-channel transmission of the SERDES signal, the multi-channel full-duplex communication SERDES signal transmission can be achieved.

[0080] This embodiment does not limit the implementation manner of multi-channel transmission of the SERDES signal, which can be determined according to the test requirements.

[0081] Figure 1 on the connector 21 in at least includes respectively Figure 2 Each of the first pins 1211, 1212, 1213, 1214, 1215, 1216, 1217 on the first connector 12 in can form the second pin of the SERDES link, that is, each of the first pins 1211, 1212, 1213, 1214, 1215, 1216, 1217 has a corresponding second pin, and both the first pin and the second pin are used to transmit the SERDES signal with the same number of channels and the same type.

[0082] Among them, the connector 21 may include but is not limited to one of a mirror sandwich connector, a board-to-board connector, etc., and is not limited here.

[0083] In one example, the connector 21 includes a second pin for transmitting the SERDES signal. The second pin can be understood to exist in the form of the female head of the connector 21. The first connector 12 includes a male head for transmitting the SERDES signal. The second pin and the male head for transmitting the SERDES signal in the first connector 12 are communicatively connected by plugging in and can be used to transmit the SERDES signal.

[0084] Such as Figure 1 As shown, the connector 21 can be soldered on the substrate 2 and connected to at least one first system to be tested 3 through the PCB traces on the substrate 2 and the cables connected to the PCB traces. Among them, the substrate 2 is, for example, a PCB or the like.

[0085] In one example, such as Figure 1As shown, each first system to be tested 3 can obtain a first data packet to be tested, and encode the first data packet to be tested to obtain a SERDES signal to be tested. Among them, the first data packet to be tested includes, for example, but is not limited to, a pseudo-random sequence or fixed pattern data, etc. The first data packet to be tested can be stored in the first system to be tested 3 or in other systems.

[0086] If the first system to be tested 3 can send the SERDES signal to be tested to the first test chip 11 connected to the first pin 1211 through the SERDES signal path formed by the connector 21, the second pin, the first connector 12, and the first pin 1211; the first test chip 11 connected to the first pin 1211 performs a self-loop on the SERDES signal to be tested, that is, the first test chip 11 connected to the first pin 1211 can decode the SERDES signal to be tested to obtain a first intermediate data packet, and then encode the first intermediate data packet to obtain a first feedback signal; and send the first feedback signal to the first system to be tested 3 through the SERDES signal path formed by the first pin 1211, the first connector 12, the second pin, and the connector 21.

[0087] Then the first system to be tested 3 decodes the first feedback signal to obtain a first data packet to be verified, and compares the first data packet to be verified with the expected data packet of the first data packet to be tested. If the comparison result is that the two are the same, the first system to be tested 3 determines that the SERDES link between the first system to be tested 3 corresponding to the first pin 1211 and the GPU test device 1 is connected; if the comparison result is that the two are different, or the first system to be tested 3 does not obtain the first data packet to be verified, the first system to be tested 3 determines that the SERDES link between the first system to be tested 3 corresponding to the first pin 1211 and the GPU test device 1 is not connected. Among them, the expected data packet of the first data packet to be tested is, for example, the first data packet to be tested.

[0088] Similarly, the connectivity of the SERDES links between the first systems to be tested 3 corresponding to the remaining first pins 1212, 1213, 1214, 1215, 1216, and 1217 and the GPU test device 1 can be tested separately. The specific implementation method is similar to the implementation method of testing the connectivity of the SERDES link between the first system to be tested 3 corresponding to the first pin 1211 and the GPU test device 1. For details, please refer to the above description and will not be elaborated here.

[0089] When testing the connectivity of the SERDES links between the first test systems 3 corresponding to the first pins 1211, 1212, 1213, 1214, 1215, 1216, and 1217 and the GPU test device 1 respectively, it can be parallel, serial, or only test the connectivity of the SERDES links between the first test systems 3 corresponding to some of the first pins and the GPU test device 1. This embodiment does not limit this and can be determined according to the test requirements.

[0090] Assume that the test requirement is to test the links corresponding to each of the first pins 1211, 1212, 1213, 1214, 1215, 1216, and 1217. If the test results of the SERDES links between the first test systems 3 corresponding to the first pins 1211, 1212, 1213, 1214, 1215, 1216, and 1217 and the GPU test device 1 are all connected, then the first test system 3 determines that the SERDES link between the first test system 3 and the GPU is connected.

[0091] An embodiment of the present application provides a GPU test device, including at least one first test chip and at least one first connector communicatively connected to the first test chip. The first connector includes at least one first pin for transmitting SERDES signals; each first pin is communicatively connected to a second pin on a substrate; the first test signal includes a to-be-tested SERDES signal; the second pin receives the to-be-tested SERDES signal sent by the first test system and sends the to-be-tested SERDES signal to the first test chip through the first pin; the first test chip generates a first feedback signal for the to-be-tested SERDES signal and sends the first feedback signal to the first test system; wherein, the first test system determines the connectivity of the SERDES link between the first test system and the GPU based on the first feedback signal.

[0092] Since the first test system, the second pin, and the first pin and the first test chip in the GPU test device form a path for the SERDES signal, the GPU test device can test the connectivity of the SERDES link between the first test system and the GPU.

[0093] Exemplarily, in scenarios such as high-performance computing, large-scale artificial intelligence model training and applications, and large-scale data processing and computing tasks in data centers, the first test system and the GPU can be connected through a signal conversion module and a cable to achieve high-bandwidth and low-latency transmission of a large amount of data. And the signal conversion module can enhance the integrity and anti-interference ability of the signal during the signal transmission process, and at the same time support hot plugging, which is convenient for maintenance and upgrading. Therefore, it is necessary to test the connectivity of the link between the first test system and the GPU connected through the signal conversion module and the cable.

[0094] Figure 3 A structural schematic diagram of a first system to be tested and a second system to be tested provided in this application, respectively connected to a GPU test device, as Figure 3 shown. In some implementation manners of this embodiment, the GPU test device 1 may further include at least one second connector 13 communicatively connected to the first test chip 11; the second connector 13 is communicatively connected to the first cable 5 through the signal conversion module 4, and the first cable 5 is connected to the first system to be tested 3;

[0095] And the first test chip 11 sends the first feedback signal to the first system to be tested 3, including:

[0096] The first test chip 11 sends the first feedback signal to the first system to be tested 3 through the SERDES signal path formed by the second connector 13, the signal conversion module 4 and the first cable 5.

[0097] In one example, the signal conversion module 4 includes a hot-pluggable optical module.

[0098] Exemplarily, Figure 4 Another structural schematic diagram of the GPU test device provided in this application, as Figure 4 shown. The GPU test device 1 further includes 4 second connectors 13 soldered on the single board. Among them, the second connector 13 includes, for example, but is not limited to, a high-density connector (High-Density Link Connector) or a high-speed backplane connector (Samtec Q Strip High-Speed Backplane Connector, abbreviated as Q Strip), etc. This embodiment does not limit the type of the second connector 13, as long as it can connect the first test chip 11 and the signal conversion module 4 and transmit SERDES signals. The second connector 13 is connected to the first test chip 11 through the PCB trace on the single board and is connected to the signal conversion module 4 by a cable; as Figure 3 shown, the signal conversion module 4 is connected to the first system to be tested 3 through the first cable 5.

[0099] Among them, the signal conversion module 4 can be, for example, an OSFP module, etc. The first cable 5 can be, for example, an optical fiber or a high-speed copper cable, etc. The signal conversion module 4 can identify whether the currently connected cable is an optical fiber or a high-speed copper cable, and automatically enable or disable the optoelectronic conversion function. That is, if the signal conversion module 4 detects that the currently connected cable is a high-speed copper cable, the signal conversion module 4 will automatically disable the optoelectronic conversion function and directly transmit the electrical signal; if the signal conversion module 4 detects that the currently connected cable is an optical fiber, the signal conversion module 4 will enable the optoelectronic conversion function to convert the electrical signal into an optical signal for transmission or convert the optical signal into an electrical signal for transmission.

[0100] For example, still adopting Figure 1 and Figure 2 the implementation method in the embodiment, after the first test chip 11 connected to the first pin 1211 generates a first feedback signal for the SERDES signal to be tested, as Figure 3 and Figure 4 shown, the first test chip 11 connected to the first pin 1211 sends the first feedback signal to the first system to be tested 3 through the SERDES signal path formed by the second connector 13 connected to the first test chip 11, the signal conversion module 4 connected to the second connector 13, and the first cable 5 connected to the signal conversion module 4 in sequence.

[0101] Subsequently, the implementation method for the first system to be tested 3 to determine the connectivity of the SERDES link between the first system to be tested 3 and the GPU based on the first feedback signal is similar to Figure 1 and Figure 2 the implementation method in the embodiment. For details, reference can be made to Figure 1 and Figure 2 the embodiment, which will not be elaborated here.

[0102] The SERDES signal path formed by the second connector, the signal conversion module, and the first cable can be used to test the connectivity of the SERDES link between the first system to be tested and the GPU when they are connected through the signal conversion module and the first cable in scenarios such as high-performance computing, large-scale artificial intelligence model training and applications, and large-scale data processing and computing tasks in data centers.

[0103] As Figure 3 shown, in some implementation manners of this embodiment, the GPU test device 1 further includes at least one second test chip 14, where each second test chip 14 is respectively communicatively connected to at least one third pin on the substrate 2 through the first connector 12;

[0104] At least one third pin receives the second signal to be tested sent by at least one second system to be tested 6 and sends the second signal to be tested to the corresponding second test chip 14;

[0105] The second test chip 14 generates a second feedback signal according to the second signal to be tested, and sends the second feedback signal to the second system to be tested 6, so that the second system to be tested 6 determines the connectivity of the link for transmitting the second signal to be tested between the second system to be tested 6 and the GPU based on the second feedback signal.

[0106] In one example, the second signal to be tested includes one or more of: a PCIE link test signal, a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

[0107] In one example, the second test chip includes: a PCIE terminal device simulation chip for receiving a PCIE link test signal, and / or a complex programmable logic device for receiving a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

[0108] In one example, the second system to be tested 6 includes: different functional modules located on the same server; or, different functional modules located on different servers.

[0109] Exemplarily, as Figure 4 shown, the two second test chips 14 soldered on the single board of the GPU test device 1 are respectively connected to the first connector 12 through the PCB traces on the single board. The first connector 12 may further include at least one PCIE pin 1221 for transmitting PCIE signals, wherein the PCIE pin 1221 is communicatively connected to the third pin on the substrate 2 in Figure 3 through the first connector 12; the third pin is connected to the second system to be tested 6 in Figure 3 through the PCB traces on the substrate 2 in Figure 3 and the cables connected to the PCB traces.

[0110] Each PCIE pin 1221 corresponds to a PCIE link. Each PCIE pin 1221 can be used for single-channel transmission of PCIE signals or multi-channel transmission of PCIE signals. Each PCIE pin 1221 may include at least two pairs of physical pins, and each two pairs of physical pins correspond to one channel; wherein, a pair of physical pins for transmitting differential signals (such as TX+ pin and TX- pin) corresponding to one channel can be used to transmit PCIE signals, and another pair of physical pins for receiving differential signals (such as RX+ pin and RX- pin) can be used to receive PCIE signals.

[0111] In this embodiment, the number of physical pins in each PCIE pin 1221 is not limited, as long as the physical pins corresponding to one channel can be used to transmit and / or receive PCIE signals.

[0112] When transmitting PCIE signals in multiple channels, the transmitting end can first cut the PCIE signal into multiple PCIE slice signals, and then independently transmit each PCIE slice signal in parallel through multiple different channels. Finally, at the receiving end, the PCIE slice signals are recombined to obtain the PCIE signal. Therefore, when transmitting PCIE signals in multiple channels, multi-channel full-duplex communication of PCIE signal transmission can be achieved. The implementation method of transmitting PCIE signals in multiple channels in this embodiment is not limited and can be determined according to test requirements.

[0113] Such as Figure 4 shown, the connector 21 further includes at least a third pin that can form a PCIE link with the PCIE pin 1221 on the first connector 12 in Figure 4 . That is, the PCIE pin 1221 has a corresponding third pin, and both the PCIE pin and the third pin are used to transmit the same-channel and same-type PCIE signals.

[0114] The connector 21 can also be connected to the second system under test 6 through the PCB traces and cables on the substrate 2.

[0115] In one example, the third pin can be understood to exist in the form of a female head of the connector 21. The first connector 12 further includes a male head for transmitting PCIE signals. The third pin and the male head for transmitting PCIE signals in the first connector 12 are connected through plug-in communication and can be used to transmit PCIE signals.

[0116] In one example, such as Figure 4 shown, the second test chip 14 connected to the PCIE pin 1221 can be a PCIE terminal device simulation core for receiving PCIE link test signals, such as a PCIE switch chip.

[0117] In one example, Figure 3 the second system under test 6 in Figure 4The PCIE pin 1221 in it sends the PCIE link test signal to the second test chip 14 connected to the PCIE pin 1221. The second test chip 14 connected to the PCIE pin 1221 decodes the PCIE link test signal to obtain the request to be verified, and according to the request to be verified, obtains the device information of the device from the second test chip 14 connected to the PCIE pin 1221 and encodes the device information to obtain the second feedback signal, and sends the second feedback signal to the second system to be tested 6 through the PCIE signal path formed by the PCIE pin 1221, the first connector 12, and the third pin; The second system to be tested 6 decodes the second feedback signal to obtain the device information to be verified;

[0118] Then the second system to be tested 6 can compare the device information to be verified with the expected device information. If the comparison result is that the two are consistent, it is determined that the PCIE link between the second system to be tested 6 and the GPU is connected. If the comparison result is that the two are inconsistent, or the second system to be tested 6 does not obtain the device information to be verified, it is determined that the PCIE link between the second system to be tested 6 and the GPU is not connected. Among them, the expected device information is the correct device information of the second test chip 14 connected to the PCIE pin 1221.

[0119] In the related art, when testing the connectivity of the PCIE link between the system and the GPU, a PCIE signal test link is formed through the PCIE slot in the GPU verification device and the PCIE device outside the GPU verification device connected to the PCIE slot. However, each time a test is performed, a PCIE device needs to be prepared, which is inconvenient to operate; moreover, the PCIE slot and the PCIE device may be damaged after being inserted and removed multiple times, and thus the connectivity test of the PCIE link between the system and the GPU cannot be performed; in addition, in a liquid-cooled electronic device, a cold plate is provided on the GPU to dissipate heat from the GPU. If the distance between the cold plate and the GPU verification device cannot insert the PCIE device, the connectivity test of the PCIE link between the system and the GPU cannot be performed either.

[0120] In this embodiment, when the second system to be tested tests the connectivity of the PCIE link between the second system to be tested and the GPU, a test link for PCIE signals is formed through the third pin, the first connector, the PCIE pins, and the second test chip connected to the PCIE pins. Since the second test chip is soldered in the GPU test device, there is no need to prepare a PCIE device or plug and unplug it, avoiding damage to the second test chip during the plugging and unplugging process. Moreover, since the GPU test device does not need to insert a PCIE device, it is not restricted by the distance between the cold plate and the GPU. Therefore, the GPU test device has better flexibility and stability when testing the connectivity of the PCIE link between the second system to be tested and the GPU.

[0121] In one example, as Figure 4 shown, the second test chip 14 respectively connected to the low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236 can be a complex programmable logic device for receiving universal asynchronous receiver / transmitter link test signals, inter-integrated circuit bus link test signals, and joint test action group link test signals. The complex programmable logic device communicates with at least one fourth pin on the substrate 2 in Figure 3 through the first connector 12;

[0122] As Figure 3 shown, the fourth pin receives one of the universal asynchronous receiver / transmitter link test signals, inter-integrated circuit bus link test signals, and joint test action group link test signals sent by the second system to be tested 6, and sends the low-speed signal to the second test chip 14 (hereinafter referred to as the complex programmable logic device) connected to the corresponding low-speed signal pin;

[0123] The complex programmable logic device generates a second feedback signal for the low-speed signal and sends the second feedback signal to the second system to be tested 6, so that the second system to be tested 6 determines the connectivity of the low-speed signal link between the second system to be tested 6 and the GPU according to the second feedback signal.

[0124] Exemplarily, as Figure 4 shown, the complex programmable logic device soldered on the single board of the GPU simulation test device 1 is connected to the first connector 12 through PCB traces on the single board. The first connector 12 may also include the low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236, where the low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236 are connected to Figure 3At least one fourth pin on the substrate 2 therein is communicatively connected through the first connector 12; a PCB trace on the substrate 2 and a cable connected to the PCB trace are connected between at least one fourth pin and the second system to be tested 6.

[0125] Each of the low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236 corresponds to one of the universal asynchronous receiver / transmitter test signal link, the inter-integrated circuit bus test signal link, and the joint test action group test signal link. Each low-speed signal pin can be used for single-channel full-duplex transmission of low-speed signals or single-channel half-duplex transmission of low-speed signals. Each low-speed signal pin may include at least two physical pins, respectively for transmitting low-speed signals and for receiving low-speed signals.

[0126] In this embodiment, the number of physical pins in each low-speed signal pin is not limited, as long as the physical pins corresponding to one channel can be used for transmitting low-speed signals and / or receiving low-speed signals.

[0127] As Figure 3 shown, the connector 21 further includes at least fourth pins that can form a low-speed signal link with the respective low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236 on the first connector 12, that is, each of the low-speed signal pins 1231, 1232, 1233, 1234, 1235, 1236 has a corresponding fourth pin, and the low-speed signal pin and the fourth pin are both used for transmitting low-speed signals of the same number of channels and the same type.

[0128] In one example, the fourth pin can be understood to exist in the form of a female head of the connector 21. The first connector 12 further includes a male head for transmitting low-speed signals. The fourth pin is communicatively connected to the male head for transmitting low-speed signals in the first connector 12 by plugging and can be used for transmitting low-speed signals.

[0129] In one example, assume Figure 4 that the low-speed signal pin 1231 therein is used for transmitting the asynchronous receiver / transmitter test signal, Figure 3 the second system to be tested 6 therein can first obtain a second data packet to be tested and encode the second data packet to obtain a to-be-tested asynchronous receiver / transmitter test signal; wherein, the second data packet to be tested includes, for example, but is not limited to, one or more of text data, control commands, and status information. The second data packet to be tested can be stored in the second system to be tested 6 or stored in other systems.

[0130] If the second system to be tested 6 can send the asynchronous transceiver test signal to be tested to the complex programmable logic device through the universal asynchronous receiver / transmitter test signal path formed by the connector 21, the fourth pin, the first connector 12, and the low-speed signal pin 1231, the complex programmable logic device decodes the asynchronous transceiver test signal to be tested to obtain a second intermediate data packet, processes the second intermediate data packet based on a first preset algorithm to obtain a data packet to be verified, encodes the data packet to be verified to obtain a second feedback signal, and sends the second feedback signal to the second system to be tested 6 through the asynchronous transceiver test signal path formed by the low-speed signal pin 1231, the first connector, the connector, and the fourth pin;

[0131] Then the second system to be tested 6 decodes the second feedback signal to obtain a second data packet to be verified, and compares the second data packet to be verified with the expected data packet of the second system to be tested. If the comparison result is that the two are the same, it is determined that the asynchronous transceiver test signal link corresponding to the low-speed signal pin 1231 between the second system to be tested 6 and the GPU test device 1 is connected. If the comparison result is that the two are different, or the second system to be tested 6 does not obtain the second data packet to be verified, it is determined that the asynchronous transceiver test signal link corresponding to the low-speed signal pin 1231 between the second system to be tested 6 and the GPU test device 1 is not connected. Among them, the expected data packet of the second system to be tested is, for example, the data packet obtained by processing the second system to be tested based on the first preset algorithm.

[0132] Similarly, the connectivity of the low-speed signal links between the second system to be tested 6 corresponding to the other low-speed signal pins 1232, 1233, 1234, 1235, and 1236 and the GPU test device 1 can be tested respectively. The specific implementation method is similar to the implementation method of testing the connectivity of the asynchronous transceiver test signal link between the second system to be tested 6 corresponding to the low-speed signal pin 1231 and the GPU test device 1 introduced above. For details, please refer to the above description and will not be elaborated here.

[0133] When testing the connectivity of the low-speed signal links between the second system to be tested 6 corresponding to the low-speed signal pins 1231, 1232, 1233, 1234, 1235, and 1236 and the GPU test device 1 respectively, it can be parallel, serial, or only test the connectivity of the low-speed signal links between the second system to be tested 6 corresponding to some low-speed signal pins and the GPU test device 1. This embodiment does not limit this and can be determined according to the test requirements.

[0134] Assume that the test requirement is to test the links corresponding to each of the low-speed signal pins 1231, 1232, 1233, 1234, 1235, and 1236. If the test results of the low-speed signal links between the second system to be tested 6 and the GPU test device 1 corresponding to each of the low-speed signal pins 1231, 1232, 1233, 1234, 1235, and 1236 are all connected, then the second system to be tested 6 determines that the low-speed signal link between the second system to be tested 6 and the GPU test device 1 is connected.

[0135] Since the connectors in the GPU verification device in the related art are directly plugged into the connectors in the system, the GPU verification device can only be used to test the connectivity of the PCIE link and / or the low-speed signal link between one system and the GPU at a time, and cannot test the connectivity of the PCIE link and / or the low-speed signal link between multiple systems and the GPU simultaneously.

[0136] As Figure 3 shown, the first system to be tested 3 and the second system to be tested 6 are respectively connected to the substrate 2 by cables. The substrate 2 is connected to the connector 21 through the PCB traces on the substrate 2. The connector 21 is plugged into the first connector 12 in the GPU test device 1. Moreover, there can be more first systems to be tested 3 or second systems to be tested 6 respectively connected to the substrate 2 by cables. Thus, it can achieve simultaneous testing of the connectivity of the SERDES links between multiple first systems to be tested 3 and multiple second systems to be tested 6 and / or the links for transmitting the second signals to be tested to the GPU, thereby improving the test efficiency.

[0137] Figure 5 This is a schematic structural diagram of the GPU test system provided by the present application. As Figure 5 shown, the GPU test system provided in this embodiment includes at least one first system to be tested 3, at least one second system to be tested 6, a substrate 2, and multiple GPU test devices 1. Among them, the multiple GPU test devices 1, each first system to be tested 3, and each second system to be tested 6 are respectively communicatively connected to the substrate 2. Its structure and technical effects are similar to those in the above method embodiment and will not be elaborated here.

[0138] Those skilled in the art will readily think of other implementation schemes of the present application after considering the specification and practicing the invention disclosed herein. The present application aims to cover any variations, uses, or adaptive changes of the present application. These variations, uses, or adaptive changes follow the general principles of the present application and include the common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the following claims.

[0139] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A GPU testing device, characterized in that, The GPU test device is communicatively connected to the substrate; the GPU test device includes: at least one first test chip and at least one first connector communicatively connected to the first test chip, the first connector including at least one first pin for transmitting a first signal to be tested; each of the first pins is communicatively connected to a second pin on the substrate; the first signal to be tested includes a SERDES signal to be tested. The second pin receives the SERDES signal to be tested sent by a first system to be tested, and sends the SERDES signal to be tested to the first test chip through the first pin. The first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested; wherein, the first system to be tested determines the connectivity of the SERDES link between the first system to be tested and the GPU based on the first feedback signal.

2. The GPU testing device according to claim 1, wherein The first test chip generates a first feedback signal for the SERDES signal to be tested, and sends the first feedback signal to the first system to be tested, including: The first test chip generates the first feedback signal by performing a self-loop on the SERDES signal to be tested. The first test chip sends the first feedback signal to the first system to be tested through the SERDES signal path formed by the first pin and the second pin.

3. The GPU testing device according to claim 1, wherein It further includes: At least one second connector communicatively connected to the first test chip; The second connector is communicatively connected to a first cable through a signal conversion module, and the first cable is connected to the first system to be tested; And the first test chip sends the first feedback signal to the first system to be tested, including: The first test chip sends the first feedback signal to the first system to be tested through the SERDES signal path formed by the second connector, the signal conversion module and the first cable.

4. The GPU testing device according to claim 3, wherein, The signal conversion module includes a hot-pluggable optical module.

5. The GPU testing device according to any one of claims 1-4, characterized in that, The SERDES signal to be tested is obtained by encoding a first data packet to be tested acquired by the first system to be tested; The first system to be tested determines the connectivity of the SERDES link between the first system to be tested and the GPU based on the first feedback signal, including: The first system to be tested decodes the first feedback signal to obtain a first data packet to be verified; If the first data packet to be verified is consistent with the expected data packet of the first data packet to be tested, the first system to be tested determines that the SERDES link between the first system to be tested and the GPU is connected.

6. The GPU testing device according to claim 1, characterized in that It further includes: At least one second test chip, wherein each of the second test chips is respectively communicatively connected to at least one third pin on the substrate through the first connector; The at least one third pin receives a second signal to be tested sent by at least one second system to be tested, and sends the second signal to be tested to the corresponding second test chip. The second test chip generates a second feedback signal according to the second signal to be tested, and sends the second feedback signal to the second system to be tested, so that the second system to be tested determines the connectivity of the link for transmitting the second signal to be tested between the second system to be tested and the GPU based on the second feedback signal.

7. The GPU testing device according to claim 6, wherein The second signal to be tested includes one or more of a PCIE link test signal, a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

8. The GPU testing device according to claim 7, wherein, The first test chip includes a retimer; The second test chip includes a PCIE terminal device simulation chip for receiving a PCIE link test signal, and / or a complex programmable logic device for receiving a universal asynchronous receiver / transmitter link test signal, an inter-integrated circuit bus link test signal, and a joint test action group link test signal.

9. The GPU testing device according to claim 6, wherein The first system to be tested and the second system to be tested include: Different functional modules located on the same server; Or, different functional modules located on different servers.

10. A GPU test system, characterized in that, Including: At least one first system to be tested, at least one second system to be tested, a substrate, and a plurality of GPU test devices as described in any one of claims 1-9; Wherein, the plurality of GPU test devices, each of the first systems to be tested, and each of the second systems to be tested are respectively communicatively connected to the substrate.

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