Time domain interleaving method, de-interleaving method, interleaver and de-interleaver

Abstract

The invention discloses a time domain interleaving method, a de-interleaving method, an interleaver and a de-interleaver, and the time domain interleaving method comprises the steps: carrying out the extension, code block segmentation and coding of a transmission block through the redundancy version number n used for interleaving, obtaining k coded code blocks, and writing the coded code blocks into a circulation memory; dividing redundancy versions and marking redundancy version numbers based on the bit length of each redundancy version of the coded code block in the cyclic memory; each subframe selects redundancy versions with the same redundancy version number in k code blocks, and the k redundancy versions are arranged according to a preset arrangement method and / or offset according to a preset offset method; according to the method provided by the invention, the problem that the existing time interleaving method for multiplexing HARQ storage amplifies selective fading of a frequency domain can be effectively solved, the anti-interference capability of a system is remarkably improved, the bit error rate of a code block caused by channel fading is reduced, and the performance of the system is improved. And the transmission quality and performance of the whole communication system are improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of communication technologies, and more particularly to a time-domain interleaving method, a deinterleaving method, an interleaver, and a deinterleaver. Background Art

[0002] With the rapid development of mobile communication technologies, broadcast technologies are being increasingly widely used in 5G and future communication networks, especially in Multimedia Broadcast Multicast Service (MBMS) that supports a large number of users. Broadcast and multicast communications can efficiently transmit the same data content to multiple end-users, greatly saving spectrum resources. However, the complexity of the wireless propagation environment makes broadcast signals face challenges such as signal attenuation, interference, and multipath effects under high-speed mobile conditions, resulting in difficult-to-guarantee signal reception quality. In high-speed mobile scenarios, the signal quality fluctuations will be even more obvious, leading to an increase in the Block Error Rate (BLER), which seriously affects the user experience.

[0003] To improve the performance of broadcast systems in high-speed mobile environments and enhance the robustness of signals, physical layer time interleaving technology has emerged and been widely applied. The time interleaving technology rearranges data according to the time dimension during data transmission, enabling the receiving end to receive signals at multiple different time points, thereby achieving time diversity gain. In high-speed mobile scenarios, this technology can significantly reduce the adverse effects of multipath effects and fast fading, thus greatly improving the reliability of signal transmission.

[0004] However, when existing time interleaving methods achieve time diversity, they usually require a substantial increase in the memory requirement of the Log Likelihood Ratio (LLR) cache at the receiving end. This may impose a significant burden on some receiving devices, especially low-power terminals or devices with limited resources. To this end, current solutions have proposed using a packet transmission algorithm based on the Hybrid Automatic Repeat reQuest (HARQ) mechanism at the transceiver and implementing time interleaving using the HARQ memory that is not yet used in MBMS, thereby avoiding additional resource occupation. Its physical resource mapping is as Figure 1 shown.

[0005] However, in the current time-frequency domain interleaving scheme, frequency domain interleaving is within one OFDM, and time domain interleaving is between multiple code blocks. Under the current HARQ-based time domain interleaving scheme, different redundancy versions (RV) belonging to the same code block will be input into the frequency domain interleaver in the same order when performing frequency domain interleaving, resulting in the corresponding data being mapped to the same frequency point, which exponentially amplifies the impact of frequency domain selective fading on a single code block. This will greatly affect the transmission effect of some code blocks, and thus affect the overall performance and stability of the system.

[0006] Therefore, how to avoid the amplification of frequency domain selective fading caused by time domain interleaving without increasing the resource burden is still a key problem that needs to be solved urgently in current technology. Summary of the invention

[0007] In order to solve the problem that the existing time domain interleaving technology of multiplexing HARQ storage amplifies frequency domain selective fading, the present application provides a time domain interleaving method, a deinterleaving method, an interleaver and a deinterleaver.

[0008] The present application provides an interleaving method, comprising the following steps:

[0009] The transmission block is expanded by using the redundant version number n used for interleaving, the code block is segmented and encoded, and the encoded k code blocks are obtained and written into the circular memory;

[0010] Based on the bit length of each redundant version of the encoded code block in the cyclic memory, the code blocks are divided into redundant versions and marked with redundant version numbers;

[0011] In each subframe, redundancy versions with the same redundancy version number are selected from k code blocks, and the k redundancy versions are arranged according to a predetermined arrangement method, and / or offset according to a predetermined offset method;

[0012] Processing is performed on the bits included in the arranged and / or shifted redundant version.

[0013] Optionally, the bit positions corresponding to the redundant versions in the cyclic memory are distributed in a continuous cyclic manner.

[0014] Optionally, the sum of the numbers of bits of the n redundant versions in each code block is equal to or less than the number of bits in the circular memory.

[0015] Optionally, the predetermined arrangement method is to arrange the redundant versions of the k code blocks in each subframe in sequence or reverse order according to the code block numbers, or to arrange them in any order.

[0016] Optionally, the predetermined offset method is to perform sequential / reverse cyclic offset on the redundant versions of k code blocks in a subframe in units of redundant versions, or to perform offset according to a given sequence number group.

[0017] Optionally, in a transmission period composed of n subframes, the n subframes are equally spaced.

[0018] A transmission period composed of n subframes completes the transmission of the corresponding bits of n redundant versions among k code blocks.

[0019] The present invention provides a time-domain deinterleaving method, which demodulates the received symbols to obtain the corresponding log-likelihood ratio and fills it into the corresponding position in the cyclic memory for processing.

[0020] The present invention provides a time-domain interleaver, including:

[0021] A processing unit that expands the transport block using the number of redundant versions n for interleaving, performs code block segmentation and encoding to obtain k encoded code blocks, and writes them into the cyclic memory;

[0022] Based on the bit lengths of the respective redundant versions of the encoded code blocks in the cyclic memory, they are divided into redundant versions and the redundant version numbers are marked;

[0023] Each subframe selects the redundant versions with the same redundant version number among the k code blocks, arranges the k redundant versions according to a predetermined arrangement method, and / or offsets them according to a predetermined offset method;

[0024] Process the bits included in the arranged and / or offset redundant versions;

[0025] A transmission unit that transmits the processed symbols.

[0026] The present invention provides a time-domain deinterleaver, including:

[0027] A receiving unit that receives the symbols transmitted through the channel;

[0028] A processing unit that demodulates the received symbols to obtain the corresponding log-likelihood ratio and fills it into the corresponding position in the cyclic memory for processing.

[0029] The present invention provides a computer-readable storage medium, including a computer program, which when executed by a processor enables the processor to implement the method described in any one of the above.

[0030] The method proposed by the present invention can effectively solve the problem of multiplying and amplifying the frequency-domain selective fading in the existing time-domain interleaving method for multiplexing HARQ storage, significantly improve the anti-interference ability of the system, reduce the bit error rate caused by channel fading, and improve the transmission quality and performance of the entire communication system. Description of the Drawings

[0031] With reference to the accompanying drawings and the following specific embodiments, the features, advantages, and aspects of the various embodiments of the present application will become more apparent. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the original elements and elements are not necessarily drawn to scale.

[0032] Figure 1 Schematic diagram of physical resource mapping for the prior art;

[0033] Figure 2 Flowchart of an interleaving method provided by the present invention;

[0034] Figure 3 Flowchart of a deinterleaving method provided by the present invention;

[0035] Figure 4 Schematic diagram of the structure of an interleaver provided by the present invention;

[0036] Figure 5 Schematic diagram of the structure of a deinterleaver provided by the present invention.

[0037] Figure 6 Flowchart of an interleaving method provided by the present invention;

[0038] Figure 7 Schematic diagram of physical resource mapping for the interleaving method provided in Embodiment 1 of the present application;

[0039] Figure 8 Schematic diagram of physical resource mapping for the interleaving method provided in Embodiment 2 of the present application;

[0040] Figure 9 Schematic diagram of physical resource mapping for the interleaving method provided in Embodiment 3 of the present application;

[0041] Figure 10 Schematic diagram of physical resource mapping for the interleaving method provided in Embodiment 4 of the present application;

[0042] Figure 11 Schematic diagram of physical resource mapping for the interleaving method provided in Embodiment 5 of the present application; Specific Embodiments

[0043] The following further elaborates on the present application in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the present application and not for limiting the present application. Additionally, it should be noted that for the sake of description, only the parts related to the present application rather than all the structures are shown in the drawings.

[0044] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0045] In addition, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.

[0046] The present application will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only for explaining the present application, rather than limiting the present application. Additionally, it should be noted that for ease of description, only parts related to the present application rather than all structures are shown in the drawings.

[0047] Before discussing the exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but it can also have additional steps not included in the figures. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0048] It should be noted that the concepts such as "first" and "second" mentioned in the embodiments of the present application are only used to distinguish different devices, modules, units, or other objects, and are not used to limit the order of functions performed by these devices, modules, units, or other objects or their interdependent relationships.

[0049] In addition, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other.

[0050] Considering the existing time-domain interleaving method as Figure 1 shown, in each subframe, the redundancy versions (RVs) of different code blocks are input into the frequency-domain interleaver in the same relative order (such as Figure 1 in the first two subframes, RV 00 and RV 10 , RV 01 and RV 11, first input the redundant version of the first code block and then input the redundant version of the second code block). Eventually, different redundant versions of the same code block are mapped onto the same subcarriers. This will cause the impact of frequency-domain selective fading on a single code block to be amplified multiplicatively, affecting the interleaving effect and reducing the transmission performance.

[0051] The present invention proposes a time-domain interleaving method for cross-transport blocks (TBs) that helps code blocks combat frequency-domain selective fading and reuses the HARQ cyclic memory. The core lies in performing channel coding on the data of multiple TBs simultaneously, and intercepting the encoded bit sequence with a specific starting position and length to generate data segments with different combinations of information bits and parity bits, namely RVs. Transmit different redundant versions of the same code block within multiple subframe times, thereby achieving the effect of time-domain interleaving. At the same time, arrange and offset the redundant versions from different code blocks within the same subframe, so that different redundant versions of each code block are as evenly distributed as possible across the entire system bandwidth, thereby achieving better performance in frequency-domain interleaving.

[0052] The time-domain interleaving method provided by the present invention, as Figure 2 shown, includes the following steps:

[0053] Use the number of redundant versions n used for interleaving to expand the transport block, perform code block segmentation and coding to obtain k encoded code blocks, and write them into the cyclic memory;

[0054] Based on the bit lengths of the redundant versions of the encoded code blocks in the cyclic memory, divide them into redundant versions and mark the redundant version numbers;

[0055] Select the redundant versions with the same redundant version number from the k code blocks in each subframe, arrange the k redundant versions according to a predetermined arrangement method, and / or offset them according to a predetermined offset method;

[0056] Process the bits included in the arranged and / or offset redundant versions.

[0057] Among them, the steps of transport block expansion, code block segmentation and coding include: using the number of redundant versions n used for interleaving to expand the original transport block size to approximately n times the original. The expanded transport block is segmented into k code blocks in the existing manner, and then each code block is channel-coded to obtain the corresponding information bits and parity bits.

[0058] Among them, the step of writing into the cyclic memory includes: performing rate matching-related operations on the k encoded code blocks and then writing the encoded bit sequence into the cyclic memory in the existing manner.

[0059] Among them, the redundant versions include two forms: continuous redundant versions and discontinuous redundant versions. For continuous redundant versions, the starting pointer of the redundant version of each code block can be specified as the next position of the ending pointer of the previous redundant version, and the pointer increment is fixed at 1. Discontinuous redundant versions can be generated in the existing manner.

[0060] Among them, for each subframe, the redundant versions with the same redundant version number among the k code blocks are selected. Within the range across subframes, the order of the redundant version numbers selected for each subframe can be sequential / reverse or any order (for example, on the premise that 4 redundant versions are divided for each code block, the order of the redundant version numbers across subframes can be 0, 2, 3, 1).

[0061] Among them, the predetermined arrangement method includes arranging the redundant versions of the k code blocks within each subframe in sequential or reverse order according to the code block numbers, or arranging them in any order.

[0062] Among them, the predetermined offset method includes performing sequential / reverse cyclic offset on the redundant versions of the k code blocks within a subframe in units of redundant versions, or offsetting according to a given sequence number group. It should be noted that performing permutation operations can be included according to any given sequence number group.

[0063] Among them, processing the bits included in the redundant versions in sequence includes: constellation mapping, that is, mapping the bit sequence included in the redundant versions to complex symbols in sequence, then converting the modulation symbols into time-domain signals and adding a cyclic prefix, and finally completing transmission and sending.

[0064] Regarding the technical solution of generating, arranging, and offsetting redundant versions of the present invention, first, redundant versions are generated for each code block, and the redundant versions include two forms: continuous redundant versions and discontinuous redundant versions.

[0065] Subsequently, in each subframe, redundant versions with the same redundant version number are respectively selected from different code blocks, and are arranged in a predetermined arrangement method, such as arranging the redundant versions of different code blocks in sequential / reverse or any given order, and within the subframe, the redundant versions of different code blocks are offset in a predetermined offset method in units of redundant versions; the offset methods include sequential offset, reverse offset, and offsetting according to a given sequence number group.

[0066] It should be noted that the ways of arranging the redundant versions within the subframe according to the predetermined arrangement method here include sequential arrangement, reverse arrangement, and arrangement in any order, etc.

[0067] Optionally, the bit positions corresponding to each redundant version in the cyclic memory are continuously cyclically distributed.

[0068] Optionally, the sum of the number of bits of the n redundant versions in each code block is equal to or less than the number of bits in the cyclic memory;

[0069] Optionally, the predetermined arrangement method is to arrange the k redundant versions from k code blocks in a subframe in sequence.

[0070] Optionally, the predetermined arrangement method is to arrange the k redundant versions from k code blocks in a subframe in reverse order.

[0071] Optionally, the predetermined arrangement method is to arrange the k redundant versions from k code blocks in a subframe in any order.

[0072] Optionally, in the transmission period composed of n subframes, the n subframes are equally spaced;

[0073] The transmission period composed of n subframes completes the transmission of the corresponding bits of n redundant versions among k code blocks.

[0074] After arrangement, within each subframe, the redundant versions from different code blocks are offset according to a predetermined scheme in units of redundant versions;

[0075] It should be noted that the method of offsetting the redundant versions within the subframe according to the predetermined scheme here includes sequential cyclic offset, reverse cyclic offset, offset according to a given sequence number group, etc. Among them, the offset according to a given sequence number group includes permutation according to any given sequence number group.

[0076] Optionally, the predetermined offset method is to perform a sequential cyclic offset on the redundant versions.

[0077] It should be noted that the offset amount of the sequential cyclic offset here can be 1, or 2, or 3, or any non - negative integer less than k.

[0078] Optionally, the predetermined offset method is to perform a reverse cyclic offset on the redundant versions.

[0079] It should be noted that the offset amount of the reverse cyclic offset here can be 1, or 2, or 3, or any non - negative integer less than k.

[0080] Optionally, the predetermined offset method is to perform an offset according to a given sequence number group.

[0081] It should be noted that the arbitrary given sequence number group here can be a permutation operation, or other operations.

[0082] In each frame, according to the arrangement and / or offset situation, subsequent baseband processing and transmission are performed on the processed redundant versions.

[0083] This technical solution is more simplified. Compared with the existing time - interleaving technology of the multiplexing HARQ mechanism, it can effectively avoid the problem of amplifying the influence of time - domain interleaving on frequency - domain selective fading.

[0084] The time-domain interleaving scheme provided by the present invention can effectively solve the problem of amplified influence on frequency-domain selective fading after time-domain interleaving, significantly improve the anti-interference ability of the system, reduce the bit error rate caused by frequency-domain selective fading, and ultimately improve the transmission quality and performance of the entire communication system.

[0085] In particular, the present invention provides a technical solution for generating, arranging, and offsetting redundant versions, such as Figure 3 As shown, the present invention also provides a time-domain deinterleaving method, which demodulates the received symbols to obtain the corresponding log-likelihood ratio, fills them in the corresponding positions in the cyclic memory, and performs processing.

[0086] In particular, the present invention provides a technical solution for generating, arranging, and offsetting redundant versions, such as Figure 4 As shown, the present invention also provides a time-domain interleaver, including:

[0087] A processing unit 100 that expands the transport block using the number of redundant versions n for interleaving, performs code block segmentation and coding to obtain k encoded code blocks

[0088] Performs rate matching-related operations on the k encoded code blocks and writes them into the cyclic memory;

[0089] Based on the bit lengths of the redundant versions of the encoded code blocks in the cyclic memory, they are divided into redundant versions and the redundant version numbers are marked; for each subframe, k redundant versions with the same redundant version number are selected from the k code blocks, and the k redundant versions are arranged according to a predetermined arrangement method and / or offset according to a predetermined offset method; the bits included in the arranged and / or offset redundant versions are processed.

[0090] A transmitting unit 200 that transmits the data symbols after baseband processing.

[0091] In particular, the present invention provides a technical solution for generating and arranging redundant versions, such as Figure 5 As shown, the present invention also provides a time-domain deinterleaver, including:

[0092] A receiving unit 300 that receives the symbols transmitted through the channel;

[0093] A processing unit 400 that demodulates the received symbols to obtain the corresponding log-likelihood ratio and fills them in the corresponding positions in the cyclic memory;

[0094] Performs de-rate matching-related operations and decoding processing;

[0095] Aggregates the decoded code blocks into transport blocks.

[0096] Specifically, for the technical solutions of redundant version generation, arrangement, and offset, the following steps may be included:

[0097] Encode the code blocks to obtain encoded code blocks;

[0098] Perform rate matching related operations on the encoded code blocks;

[0099] Based on the bit lengths of each redundant version of the encoded code blocks in the cyclic memory, divide them into redundant versions and mark the redundant version numbers; perform constellation mapping to map the bit sequence to complex symbols;

[0100] Convert the modulated symbols into time-domain signals and add a cyclic prefix;

[0101] Transmit the time-domain signal after adding the cyclic prefix.

[0102] Optionally, before encoding the code blocks, it includes:

[0103] Expand the transport block according to the number of redundant versions, perform code block segmentation and encoding to obtain code blocks;

[0104] Optionally, the process of performing rate matching related operations on the encoded code blocks includes:

[0105] Perform rate matching internal block interleaving processing and write to the cyclic memory for the code blocks.

[0106] Optionally, based on the bit lengths of each redundant version of the encoded code blocks in the cyclic memory, divide them into redundant versions and mark the redundant version numbers;

[0107] Subsequently, for each subframe, select the redundant versions with the same redundant version number among the k code blocks, arrange the redundant versions from different code blocks in the subframe in ascending / descending order, or any order, and / or perform cyclic offset on the redundant versions from different code blocks in the subframe in ascending / descending order in units of redundant versions, or perform offset according to a given sequence number group, and process the bits included in the arranged and / or offset redundant versions.

[0108] Specifically, the interleaving method provided by the present invention can actually include: 7 steps such as transport block size (TBS) expansion, code block segmentation, channel coding, rate matching related operations, redundant version generation and physical resource mapping, constellation mapping, symbol generation and transmission, as Figure 6 shown, thus forming a complete cross-transport block time interleaving technical solution. Therefore, each step is described in detail as follows:

[0109] 1. Transport block size expansion

[0110] To ensure that the transmission throughput is consistent with non-interleaved transmission, the transport block size is appropriately extended according to the preset number of redundancy versions. Based on the system configuration and channel conditions, the transport block size TBS before extension is obtained. ori , then the extended transport block size can be expressed as:

[0111] TBS extended =round(TBS ori ×n)

[0112] where the round(·) operation means selecting the transport block size closest to {TBS ori ×n} that is legal for the 5G broadcast standard, and n is the preset number of redundancy versions.

[0113] 2. Code Block Segmentation

[0114] The extended transport block will be segmented into multiple code blocks (CBs) to meet the input requirements of the channel encoder. According to the interleaving algorithm specified by 3GPP, two interleaving parameters f1 and f2 correspond to a fixed coding block length. Therefore, the input length of the channel encoder must be two legal lengths (minimum 40 bits, maximum 6144 bits). Define the number of segments with segment lengths K plus and K minus as C plus and C minus . The code block segmentation rule is:

[0115]

[0116] where N CB is the number of code blocks. Padding bits are used for supplementation if necessary.

[0117] 3. Channel Coding

[0118] Channel coding is performed on each code block to add redundant bits to improve the anti-interference ability. Any channel coding scheme (such as Turbo coding, LDPC coding, etc.) can be arbitrarily selected. The coded code block contains information bits and parity bits, and the channel coding rate is:

[0119]

[0120] where T is the length of the information bits and N is the total length of the coded bits.

[0121] 4. Rate Matching Related Operations

[0122] The encoded code blocks need to undergo rate matching related operations, that is, adjust the length of the encoded bit sequence to adapt to the physical resource limitations. Specifically, the information bits and parity bits output by the encoder need to undergo block interleaving processing inside the rate matching and then be written into the cyclic memory.

[0123] 5. Redundancy version generation and physical resource mapping, including the technical solution of redundancy version arrangement

[0124] Based on the bit lengths of each redundancy version of the encoded code blocks in the cyclic memory, they are divided into redundancy versions and the redundancy version numbers are marked; among them, the redundancy versions include two forms: continuous redundancy versions and discontinuous redundancy versions. For continuous redundancy versions, it is stipulated that the starting pointer of the redundancy version of each code block is the next position of the ending pointer of the previous redundancy version, and the pointer increment is fixed at 1; for discontinuous redundancy versions, they are generated in the existing manner.

[0125] The present invention proposes a method for arranging and offsetting redundancy versions in the same subframe.

[0126] This method arranges the redundancy versions from different code blocks in the subframe in sequential / reverse or any order, and / or cyclically offsets the redundancy versions from different code blocks in sequential / reverse order in units of redundancy versions, or offsets them according to a given sequence number group. Subsequently, the redundancy versions are read sequentially in the order of arrangement and / or offset to achieve physical resource mapping, where the offset amount of the above sequential / reverse cyclic offset can be any non - negative integer less than the number of code blocks. The specific steps are as follows:

[0127] First, each code block generates redundancy versions. Among them, the redundancy versions include two forms: continuous redundancy versions and discontinuous redundancy versions. For continuous redundancy versions, it is stipulated that the starting pointer of the redundancy version of each code block is the next position of the ending pointer of the previous redundancy version, and the pointer increment is fixed at 1; discontinuous redundancy versions can be generated in the existing manner. At this time, the calculation method for the length of each redundancy version of each code block is: (1) If the previous step is to expand the transport block with the redundancy version number n, perform code block segmentation and encoding, then the length of the redundancy version of each code block is (2) If the previous step is to perform code block segmentation and encoding on n transport blocks with the redundancy version number, then the length of the redundancy version of each code block is Or where k represents the total number of code blocks, and the remaining variables and related calculation rules are consistent with TS 36.212.

[0128] Each subframe selects the redundancy versions with the same redundancy version number from k code blocks, arranges the k redundancy versions in sequential / reverse or any order, and / or cyclically offsets the redundancy versions in sequential / reverse order in units of redundancy versions, or offsets them according to a given sequence number group.

[0129] Here, as an example, the redundant versions within a subframe are arranged in sequence and a sequential cyclic shift is performed. The shift amount of the sequential cyclic shift is selected based on the corresponding subframe number to ensure that the redundant versions from the same code block do not overlap in the system bandwidth after frequency-domain interleaving.

[0130] In the first subframe, the redundant versions with code block number 0 for each code block are selected for transmission. The transmitted redundant versions are arranged in sequence, and the shift amount of the sequential cyclic shift is taken as 0. That is, within this subframe, the m-th transmitted redundant version comes from the (m - 1)-th code block, corresponding to RV (m-1)0 , and the (m + 1)-th transmitted redundant version comes from the m-th code block, corresponding to RV m0 .

[0131] In the n-th subframe, the redundant versions with code block number n - 1 for each code block are selected for transmission. The transmitted redundant versions are arranged in sequence, and the shift amount of the sequential cyclic shift is taken as n - 1. That is, within this subframe, the m-th transmitted redundant version comes from the ((m + n - 2) mod k)-th code block, corresponding to RV [(m+n-2)mod k](n-1) , and the (m + 1)-th transmitted redundant version comes from the ((m + n - 1) mod k)-th code block, corresponding to RV [(m+n-1)mod k](n-1) .

[0132] The arrangement and shift method of the redundant versions in the remaining subframes are the same by analogy.

[0133] This method arranges the redundant versions within the same subframe in sequence / reverse sequence, or in any order, and takes the redundant versions as units to perform cyclic shifts on the redundant versions of different code blocks in sequence / reverse sequence, or shift according to a given sequence number group. In this way, different redundant versions from the same code block are effectively and dispersedly mapped onto different subcarriers after frequency-domain interleaving, which can effectively avoid the amplification problem of time-domain interleaving on frequency-domain selective fading, thus significantly optimizing the robustness and reliability of transmission.

[0134] 6. Constellation Mapping

[0135] Adopt modulation schemes such as QPSK, 16QAM, or 64QAM to map the bit sequence into complex symbols. The mapping rule can be dynamically adjusted according to the system configuration and channel conditions.

[0136] 7. Symbol Generation and Transmission

[0137] Adopt an appropriate modulation method to convert the modulated symbols into time-domain signals and add a cyclic prefix. Dynamically adjust the transmission power and antenna configuration according to the channel state information, and transmit through the transmit antennas.

[0138] After the symbol transmission is completed, the receiving end stores the log-likelihood ratio corresponding to each redundant version in the reverse process of the transmitting end, and decodes after all redundant versions are received.

[0139] In summary, through the innovatively designed cross-transport block time-domain interleaving method, the present invention not only ensures the stability of transmission throughput, but also realizes the non-overlapping arrangement in the frequency domain after frequency-domain interleaving of different redundancy versions of the same code block, effectively reducing the amplification of time-domain interleaving on frequency-domain selective fading, and providing an effective solution for improving the reliability and efficiency of wireless broadcast transmission.

[0140] Specifically, for the time-domain interleaving technology of multiplexing HARQ cyclic storage proposed by the present invention, it can be implemented through the following data processing methods.

[0141] First, in order to ensure the same throughput as non-interleaved transmission, the transport block size TBS is appropriately expanded according to the preset number of redundancy versions n. Assuming that the number of redundancy versions of each code block is n, the expanded transport block size is:

[0142] TBS′ = round(n × TBS)

[0143] where round(·) represents selecting the transport block size closest to the legal 5G broadcast standard. The expanded transport block is segmented into K code blocks through code block segmentation.

[0144] Subsequently, the K code blocks are respectively subjected to channel coding to obtain the information bits and parity bits of each code block. Subsequently, each code block performs rate matching-related operations and is written into the cyclic buffer. Subsequently, the present invention generates the redundancy versions of each code block by a predetermined method, arranges and offsets the redundancy versions within the same subframe by a predetermined method, and uses the arranged and offset redundancy version sequence as the transmission data of the current subframe to ensure that different redundancy versions of the same code block can be evenly distributed in the frequency domain.

[0145] Then, it is successively sent to the transmitting antenna through operations such as physical mapping, constellation mapping, OFDM symbol generation and transmission. The receiving end stores the log-likelihood ratio (LLR) of each redundancy version through the reverse process of the transmitting end, and performs decoding after all redundancy versions are received, avoiding increasing the memory requirement of the LLR buffer. The above time-domain interleaving process is shown in Figure 6 is shown.

[0146] The present invention mainly focuses on how to arrange and offset the redundancy versions from different code blocks within a subframe after time-domain interleaving, so that different redundancy versions of the same code block have no overlap in the frequency domain after frequency-domain interleaving, reducing the amplification of the impact of time-domain interleaving on frequency-domain selective fading. For this purpose, the present invention proposes a method for arranging and offsetting the redundancy versions within a subframe. The specific implementation method at this time can be divided into the following preferred embodiments.

[0147] Embodiment 1:

[0148] AsFigure 7 As shown, it demonstrates the specific implementation manner of the method for generating, arranging, and offsetting redundant versions of each code block. In this embodiment, each code block is successively written into the cyclic buffer after operations related to channel coding and rate matching. To reduce the implementation complexity of time-domain interleaving, we use the redundant version as the basic time-domain operation unit, that is, based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, divide them into redundant versions and mark the redundant version numbers. Subsequently, for the k code blocks in each subframe, select the redundant versions with the same redundant version number (within the range of cross-subframes, the order of the redundant version numbers selected for each subframe can be sequential / reverse or any order. For example, on the premise that each code block is divided into 4 redundant versions, the order of the redundant version numbers across subframes can be 0, 2, 3, 1). This embodiment takes dividing continuous redundant versions, sequentially selecting redundant version numbers (i.e., 0, 1, 2, 3) within the cross-subframe range, and performing sequential arrangement and sequential cyclic offset on the redundant versions within the same subframe as an example. Optionally, the redundant versions within the same subframe can be arranged in sequential / reverse or any order, and optionally, sequential cyclic offset (and the offset amount can be any non-negative integer less than the number of code blocks K), reverse cyclic offset (and the offset amount can be any non-negative integer less than the number of code blocks K), or offset according to a given sequence group can be performed on the redundant versions within the same subframe.

[0149] Suppose each code block CB generates n consecutive redundant versions. In this embodiment, n = 4 is taken as an example. Set the starting pointer position (i.e., the bit label in the cyclic buffer) of the i-th redundant version of the k-th code block as M k,i , i = 0, 1,..., n - 1. Among them, M k,i is the bit length of this redundant version. Let be the total bit length after rate matching of the k-th code block. It is required that M k,i is the largest integer that satisfies . Set the pointer increment to 1, that is, the bit sequence of each redundant version increases sequentially from the starting pointer position. At this time, the k-th code block generates 4 consecutive redundant versions, which are respectively denoted as RV k0 , RV k1 , RV k2 , RV k3 , k = 0, 1,..., K - 1, and K represents the total number of code blocks. This embodiment takes K = 4 as an example.

[0150] Next, the K redundant versions from K code blocks within a subframe are arranged in sequence according to the code block numbers, and a sequential cyclic shift is performed within the subframe. The shift amount of the sequential cyclic shift should be such that the redundant versions of the same code block after shifting in all subframes are evenly distributed at different positions within the subframe. According to the order of arrangement and shift of the redundant versions within each subframe, physical resource mapping is performed on the redundant versions. Specifically, the redundant versions selected for the first subframe are [RV 00 ,RV 10 ,RV 20 ,…,RV (K-1)0 , the redundant versions selected for the second subframe are [RV (K-1)1 ,RV 01 ,RV 11 ,…,RV (K-2)1 , and the redundant versions selected for the idx sf -th subframe are . Among them, mod(·) represents the modulo operation. By analogy, the arrangement and physical resource mapping of the redundant versions transmitted in each subframe can be achieved.

[0151] Through the above method, different redundant versions of the same code block can be non-overlappingly arranged in the frequency domain after frequency-domain interleaving, reducing the impact of frequency-domain selective fading on a specific code block. Thus, the robustness and reliability of the transmission are optimized.

[0152] Embodiment 2:

[0153] As Figure 8 shown, the specific implementation manners of the generation, arrangement, and shift methods of the redundant versions of each code block are presented. In this embodiment, each code block undergoes channel coding and rate matching-related operations in sequence and is then written into a cyclic buffer. To reduce the implementation complexity of time-domain interleaving, we use the redundant versions as the basic time-domain operation units, that is, based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, they are divided into redundant versions and marked with redundant version numbers. This embodiment takes the division of continuous redundant versions as an example, and within the range of multiple subframes, redundant version numbers are sequentially selected (i.e., 0, 1, 2, 3), and the redundant versions within the same subframe are arranged in reverse order and reverse cyclic shifted. Optionally, the redundant versions within the same subframe can be arranged in sequential / reverse order or any order, and optionally, the redundant versions within the same subframe can be sequentially cyclic shifted (and the shift amount can be any non-negative integer less than the number of code blocks K), reverse cyclic shifted (and the shift amount can be any non-negative integer less than the number of code blocks K), or shifted according to a given sequence group.

[0154] Suppose each code block CB generates n consecutive redundant versions. In this embodiment, n = 4 is taken as an example. Let the starting pointer position (i.e., the bit label in the cyclic buffer) of the i-th redundant version of the k-th code block be M k,i, i = 0, 1, …, n - 1. Wherein, M k,i is the bit length of the redundant version. Let be the total bit length after rate matching of the k-th code block. It is required that M k,i is the largest integer that satisfies . The pointer increment is set to 1, that is, the bit sequences of each redundant version are incremented sequentially from the starting pointer position. At this time, the k-th code block generates 4 consecutive redundant versions, which are respectively denoted as RV k0 , RV k1 , RV k2 , RV k3 , k = 0, 1, …, K - 1, and K represents the total number of code blocks. In this embodiment, K = 4 is taken as an example.

[0155] Next, the K redundant versions from K code blocks within a subframe are arranged in reverse order according to the code block numbers, and a reverse cyclic shift is performed within the subframe. The offset of the reverse cyclic shift should be such that the redundant versions of the same code block after offset in all subframes are evenly distributed at different positions in the subframe. According to the order of the redundant versions after arrangement and offset within each subframe, physical resource mapping is performed on the redundant versions. Specifically, the redundant versions selected for the first subframe are RV (K-1)0 , RV (K-2)0 , RV (K-3)0 , …, RV 00 , and the redundant versions selected for the second subframe are [RV (K-2)1 , RV (K-3)1 , RV (K-4)1 , …, RV (K-1)1 . The redundant versions selected for the idx sf -th subframe are . Wherein, mod(·) represents the modulo operation. By analogy, the arrangement and physical resource mapping of the redundant versions transmitted in each subframe can be realized.

[0156] Through the above method, different redundant versions of the same code block can be non-overlappingly arranged in the frequency domain after frequency domain interleaving, reducing the influence of frequency domain selective fading on a specific code block. Thus, the robustness and reliability of the transmission are optimized.

[0157] Embodiment 3:

[0158] As Figure 9As shown, it demonstrates the specific implementation of the method for generating, arranging, and offsetting redundant versions of each code block. In this embodiment, each code block is successively written into the cyclic buffer after operations related to channel coding and rate matching. To reduce the implementation complexity of time-domain interleaving, we use the redundant version as the basic time-domain operation unit, that is, based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, they are divided into redundant versions and marked with redundant version numbers. This embodiment takes the division of consecutive redundant versions as an example, and within the subframe range, the redundant version numbers are sequentially selected (i.e., 0, 1, 2, 3), and the redundant versions within the same subframe are arranged in sequence and offset in reverse order cyclically. Optionally, the redundant versions within the same subframe can be arranged in sequence / reverse order or any order, and optionally, the redundant versions within the same subframe can be offset cyclically in sequence (and the offset amount can be any non-negative integer less than the number of code blocks K), offset cyclically in reverse order (and the offset amount can be any non-negative integer less than the number of code blocks K), or offset according to a given sequence number group.

[0159] Assume that each code block CB generates n consecutive redundant versions. In this embodiment, n = 4 is taken as an example. Set the starting pointer position (i.e., the bit label in the cyclic buffer) of the i-th redundant version of the k-th code block as M k,i , i = 0, 1, …, n - 1. Among them, M k,i is the bit length of this redundant version. Let be the total bit length after rate matching of the k-th code block. It is required that M k,i is the largest integer that satisfies . The pointer increment is set to 1, that is, the bit sequence of each redundant version increases sequentially from the starting pointer position. At this time, the k-th code block generates 4 consecutive redundant versions, which are respectively denoted as RV k0 , RV k1 , RV k2 , RV k3 , k = 0, 1, …, K - 1, and K represents the total number of code blocks. This embodiment takes K = 4 as an example.

[0160] Next, the K redundant versions from K code blocks within the subframe are arranged in sequence according to the code block numbers, and a reverse cyclic offset is performed within the subframe. The offset amount of the reverse cyclic offset should be such that after offsetting all subframes, the redundant versions of the same code block are evenly distributed at different positions within the subframe. According to the order of arrangement and offset of the redundant versions within each subframe, physical resource mapping is performed on the redundant versions. Specifically, the redundant versions selected for the first subframe are [RV 00 , RV 10 , RV 20 , …, RV (K-1)0 , and the redundant versions selected for the second subframe are [RV 11 , RV 21 , RV31 , …, RV 01 , the idx sf th subframe selects the redundancy version as where mod(·) represents the modulo operation. And so on, the arrangement of the redundancy versions transmitted by each subframe and the physical resource mapping can be realized.

[0161] Through the above method, different redundancy versions of the same code block can be non-overlappingly arranged in the frequency domain after frequency-domain interleaving, reducing the impact of frequency-domain selective fading on a specific code block. Thus, the robustness and reliability of the transmission are optimized.

[0162] Embodiment 4:

[0163] As Figure 10 shown, it shows the specific implementation manner of the generation, arrangement, and offset methods of the redundancy versions of each code block. In this embodiment, each code block is successively written into the cyclic buffer after channel coding and rate matching-related operations. To reduce the implementation complexity of time-domain interleaving, we use the redundancy version as the basic time-domain operation unit, that is, based on the bit lengths of the redundancy versions of the coded code blocks in the cyclic memory, they are divided into redundancy versions and marked redundancy version numbers. This embodiment takes dividing continuous redundancy versions, sequentially selecting redundancy version numbers (i.e., 0, 1, 2, 3) within the subframe range and inversely arranging and sequentially circularly offsetting the redundancy versions within the same subframe as an example. Optionally, the redundancy versions within the same subframe can be arranged in ascending / descending order or any order, and optionally, the redundancy versions within the same subframe can be sequentially circularly offset (and the offset amount can be any non-negative integer less than the number of code blocks K), inversely circularly offset (and the offset amount can be any non-negative integer less than the number of code blocks K), or offset according to a given sequence number group.

[0164] Suppose each code block CB generates n consecutive redundancy versions. In this embodiment, n = 4 is taken as an example. Set the starting pointer position (i.e., the bit label in the cyclic buffer) of the i-th redundancy version of the k-th code block as M k,i , i = 0, 1, …, n - 1. Where M k,i is the bit length of this redundancy version. Let be the total bit length after rate matching of the k-th code block. It is required that M k,i is the largest integer that satisfies . The pointer increment is set to 1, that is, the bit sequence of each redundancy version increases sequentially from the starting pointer position. At this time, the k-th code block generates 4 consecutive redundancy versions, which are respectively represented as RV k0 , RV k1 , RV k2 , RV k3 , k = 0, 1, …, K - 1, and K represents the total number of code blocks. In this embodiment, K = 4 is taken as an example.

[0165] Next, reverse the order of the K redundant versions from K code blocks within a subframe according to the code block numbers, and perform a sequential cyclic shift within the subframe. The shift amount of the sequential cyclic shift should be such that the redundant versions of the same code block are evenly distributed at different positions in the subframe after all subframes are shifted. According to the order of the redundant versions after arrangement and shift within each subframe, perform physical resource mapping on the redundant versions. Specifically, the redundant versions selected for the first subframe are [RV (K-1)0 , RV (K-2)0 , RV (K-3)0 , …, RV 00 , the redundant versions selected for the second subframe are [RV 01 , RV (K-1)1 , RV (K-2)1 , …, RV 11 , and the redundant versions selected for the idx sf -th subframe are where mod(·) represents the modulo operation. And so on, the arrangement and physical resource mapping of the redundant versions transmitted by each subframe can be realized.

[0166] Through the above method, different redundant versions of the same code block can be arranged without overlap in the frequency domain after frequency domain interleaving, reducing the impact of frequency domain selective fading on a specific code block. Thus, the robustness and reliability of the transmission are optimized.

[0167] Example 5:

[0168] As Figure 11 shown, it shows the specific implementation manner of the method for generating, arranging, and shifting the redundant versions of each code block. In this example, each code block is successively written into the cyclic buffer after channel coding and rate matching related operations. To reduce the implementation complexity of time domain interleaving, we use the redundant version as the basic time domain operation unit, that is, based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, divide them into redundant versions and mark the redundant version numbers. This example takes dividing continuous redundant versions, sequentially selecting redundant version numbers (i.e., 0, 1, 2, 3) within the range across subframes, arranging the redundant versions within the same subframe in any order, and shifting them according to a given sequence group as an example. Optionally, the redundant versions within the same subframe can be arranged in sequential / reverse or any order, and optionally, the redundant versions within the same subframe can be sequentially cyclically shifted (and the shift amount can be any non-negative integer less than the number of code blocks K), inversely cyclically shifted (and the shift amount can be any non-negative integer less than the number of code blocks K), or shifted according to a given sequence group.

[0169] Let each code block CB generate n consecutive redundant versions. In this embodiment, n = 4 is taken as an example. The starting pointer position (i.e., the bit label in the cyclic buffer) of the i-th redundant version of the k-th code block is set to M k,i , i = 0, 1, …, n - 1. Among them, M k,i is the bit length of this redundant version. Let be the total bit length after rate matching of the k-th code block. It is required that M k,i is the largest integer that satisfies . The pointer increment is set to 1, that is, the bit sequence of each redundant version increases sequentially from the starting pointer position. At this time, the k-th code block generates 4 consecutive redundant versions, which are respectively denoted as RV k0 , RV k1 , RV k2 , RV k3 , k = 0, 1, …, K - 1, and K represents the total number of code blocks. In this embodiment, K = 4 is taken as an example.

[0170] Next, the K redundant versions from the K code blocks within the subframe are arranged in any order, and the redundant versions are offset according to any given sequence number group. According to the order of the redundant version arrangement and offset within each subframe, physical resource mapping is performed on the redundant versions. Among them, the arbitrarily given sequence number group used for offset should preferably satisfy that the redundant versions of the same code block after offset in all subframes are evenly distributed at different positions in the subframe, so as to make the redundant versions more evenly distributed in the frequency domain.

[0171] This embodiment takes the following given arrangement order and sequence number group as an example, that is: the redundant versions selected for the first subframe are [RV 00 , RV 30 , RV 10 , RV 20 , the redundant versions selected for the second subframe are [RV 21 , RV 11 , RV 01 , RV 31 , the redundant versions selected for the third subframe are [RV 12 , RV 22 , RV 32 , RV 02 , and the redundant versions selected for the fourth subframe are [RV 33 , RV 03 , RV 23 , RV 13 . Finally, the arrangement and physical resource mapping of the redundant versions are completed.

[0172] Through the above method, it can be ensured that different redundant versions of the same code block can be arranged without overlap in the frequency domain, thereby effectively improving the robustness of the system in a frequency-selective fading environment.

[0173] This application also provides a network device, including a processor and a memory. The memory is configured to store a computer program. When the computer program is executed by the processor, the processor is caused to implement the interleaving method as described above.

[0174] This application also provides a user equipment, including a processor and a memory. The memory is configured to store a computer program. When the computer program is executed by the processor, the processor is caused to implement the deinterleaving method as described above.

[0175] This application also provides a computer-readable storage medium, including a computer program. When the computer program is executed by the processor, the processor is caused to implement any one of the methods.

[0176] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0177] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0178] The above are only the preferred embodiments of the present application, and do not limit the embodiments and protection scope of the present application. For those skilled in the art, it should be realized that all the solutions obtained by equivalent substitution and obvious changes made by using the description and illustrations of the present application should be included in the protection scope of the present application.

Claims

1. A time-domain interleaving method, characterized in that, The method includes the following steps: The transport block is extended by using the number of redundant versions n used for interleaving, code block segmentation and coding are performed to obtain k coded code blocks, and the coded code blocks are written into a cyclic memory; Based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, they are divided into redundant versions and the redundant version numbers are marked; For each subframe, the redundant versions with the same redundant version number among the k code blocks are selected, and the k redundant versions are arranged according to a predetermined arrangement method and / or offset according to a predetermined offset method; Processing is performed on the bits included in the arranged and / or offset redundant versions.

2. The time-domain interleaving method according to claim 1, characterized in that: The bit positions corresponding to the redundant versions in the cyclic memory are continuously cyclically distributed.

3. The time-domain interleaving method according to claim 1, characterized in that: The sum of the number of bits of the n redundant versions in each code block is equal to or less than the number of bits in the cyclic memory.

4. The time-domain interleaving method according to claim 1, characterized in that: The predetermined arrangement method is to arrange the redundant versions of the k code blocks in each subframe in ascending or descending order according to the code block numbers, or arrange them in any order.

5. The time-domain interleaving method according to claim 1, characterized in that: The predetermined offset method is to perform sequential / reverse cyclic offset on the redundant versions of the k code blocks in the subframe in units of redundant versions, or offset according to a given sequence number group.

6. The time-domain interleaving method according to claim 1, characterized in that: In a transmission period composed of n subframes, the n subframes are equally spaced; In a transmission period composed of n subframes, the transmission of the bits corresponding to the n redundant versions in the k code blocks is completed.

7. A time-domain deinterleaving method, characterized in that, The received symbols are baseband demodulated to obtain the corresponding log-likelihood ratio, and are filled in the corresponding positions in the cyclic memory for processing.

8. A time domain interleaver, characterized in that, It includes: A processing unit that extends the transport block by using the number of redundant versions n used for interleaving, performs code block segmentation and coding to obtain k coded code blocks, and writes the coded code blocks into a cyclic memory; Based on the bit lengths of the redundant versions of the coded code blocks in the cyclic memory, they are divided into redundant versions and the redundant version numbers are marked; For each subframe, the redundant versions with the same redundant version number among the k code blocks are selected, and the k redundant versions are arranged according to a predetermined arrangement method and / or offset according to a predetermined offset method; Processing is performed on the bits included in the arranged and / or offset redundant versions; A transmission unit that transmits the processed symbols.

9. A time-domain deinterleaver, characterized in that, It includes: A receiving unit that receives the symbols transmitted through the channel; A processing unit that baseband demodulates the received symbols to obtain the corresponding log-likelihood ratio, and fills it in the corresponding positions in the cyclic memory for processing.

10. A computer-readable storage medium includes a computer program, and when the computer program is executed by a processor, the processor is caused to implement the method according to any one of claims 1-6.

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