Communication method and system based on multi-core heterogeneous processing architecture

Abstract

The invention belongs to the technical field of multi-core heterogeneous processing, and discloses a communication method and system based on a multi-core heterogeneous processing architecture, and the method comprises the steps: carrying out the optimal configuration of parameters of a standard interface of an expansion bus of a high-speed serial computer based on the data transmission demand between a main processor and a coprocessor; a communication line is adopted to establish communication connection of each data interface, a standardized communication protocol is set, and an adaptive flow control algorithm is introduced to avoid data packet loss and retransmission; and respectively creating driving programs and communication software of the main processor and the coprocessor to realize data interaction and communication control between the processors and the coprocessor. By optimizing PCIE interface configuration and a communication protocol, the communication efficiency is remarkably improved, the communication delay is reduced, the overall performance of the system is improved, and meanwhile good compatibility and expandability are achieved; and by introducing an advanced flow control algorithm, the stability and high efficiency of data transmission are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-core heterogeneous processing, and particularly to a communication method and system based on a multi-core heterogeneous processing architecture. Background Art

[0002] With the increasing complexity of computing requirements, multi-core heterogeneous processing architectures have gradually become mainstream. By integrating different types of processors (such as CPUs, GPUs, FPGAs, etc.), they give full play to the advantages of each processor to meet diverse computing needs. Multi-core heterogeneous architectures can not only improve computing efficiency but also optimize in terms of power consumption, cost, etc.

[0003] Currently, although multi-core heterogeneous processing architectures have been widely applied, under the background of localization, there are still some technical problems in the communication between RK3588 and the K7 of FPGA, mainly including:

[0004] 1. Low communication efficiency: The existing PCIE interface configurations and communication protocols fail to fully utilize the performance advantages of RK3588 and the K7 of FPGA, resulting in low data transmission efficiency.

[0005] 2. Poor compatibility: Compatibility issues between hardware devices and driver programs from different manufacturers make system integration difficult.

[0006] 3. Complex configuration: The configuration parameters of the PCIE interface are complex, making it difficult to quickly achieve optimal configuration and affecting the overall performance of the system.

[0007] Therefore, how to provide a communication method and system based on a multi-core heterogeneous processing architecture is an urgent problem to be solved currently. Summary of the Invention

[0008] Embodiments of the present invention provide a communication method and system based on a multi-core heterogeneous processing architecture to solve the above technical problems existing in the prior art.

[0009] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary section is not a comprehensive review nor is it intended to identify key / important elements or delineate the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0010] According to the first aspect of the embodiments of the present invention, a communication method based on a multi-core heterogeneous processing architecture is provided.

[0011] In one embodiment, the communication method based on a multi-core heterogeneous processing architecture includes:

[0012] Optimize the configuration of the parameters of the high-speed serial computer expansion bus standard interface based on the data transfer requirements between the main processor and the coprocessor;

[0013] Establish communication connections for each data interface using communication lines, set a standardized communication protocol, and introduce an adaptive flow control algorithm to avoid packet loss and retransmission;

[0014] Create the driver programs and communication software for the main processor and the coprocessor respectively to achieve data interaction and communication control between the processors.

[0015] In one embodiment, the step of establishing communication connections for each data interface using communication lines, setting a standardized communication protocol, and introducing an adaptive flow control algorithm to avoid packet loss and retransmission includes:

[0016] Select corresponding communication lines for connection based on the types of data interfaces in the main processor and the coprocessor. The communication lines include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines;

[0017] Set a standardized communication protocol between the main processor and the coprocessor, and use the XDMA technology to optimize the data transmission performance and achieve hardware acceleration through direct memory access;

[0018] Use the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time, and dynamically adjust the data transmission rate according to the network status.

[0019] In one embodiment, the parameters of the high-speed serial computer expansion bus standard interface include: the number of channels, rate, and bandwidth.

[0020] In one embodiment, the data transmission lines are used to connect the high-speed serial computer expansion bus standard interface of the main processor and the high-speed serial computer expansion bus standard interface of the coprocessor; the control signal lines are used to connect the high-speed serial computer expansion bus standard controller of the main processor and the high-speed serial computer expansion bus standard controller of the coprocessor; the memory access lines are used to connect the high-speed serial computer expansion bus standard interface of the coprocessor and the memory; the direct memory access channel lines are used to connect the direct memory access controller of the main processor and the direct memory access controller of the coprocessor.

[0021] In one embodiment, the step of using the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate according to the network status includes:

[0022] Monitor the bandwidth utilization rate, packet loss rate, and transmission delay during the communication between the main processor and the coprocessor in real time, and display the current network congestion situation through network status values;

[0023] If any network status exceeds the preset threshold, it is determined that there is network congestion, and the data transmission rate is reduced. If all network statuses are lower than the preset threshold, the network is determined to be idle, and the data transmission rate is increased;

[0024] The receiving end feeds back the network status information to the sending end, and the sending end optimizes the transmission strategy of the data to be sent in the next stage according to the feedback information to form a closed-loop control.

[0025] In one embodiment, the separately creating the driver programs and communication software for the main processor and the coprocessor to implement data interaction and communication control between the processors includes:

[0026] Create a driver program that meets the compatibility of the main processor and the coprocessor, and dynamically adjust the power supply according to the network status load. Switch to the low-power mode in the low-load state;

[0027] Create communication software for data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technologies to reduce the number of errors, retransmissions and the amount of data in data transmission.

[0028] In one embodiment, the driver program includes functions such as Peripheral Component Interconnect Express (PCIe) interface initialization, XDMA initialization, data transmission control and error handling.

[0029] According to the second aspect of the embodiments of the present invention, a communication system based on a multi-core heterogeneous processing architecture is provided.

[0030] In one embodiment, the communication system based on the multi-core heterogeneous processing architecture includes:

[0031] An interface optimization module, configured to optimize and configure the parameters of the Peripheral Component Interconnect Express (PCIe) interface based on the data transmission requirements between the main processor and the coprocessor;

[0032] A protocol configuration module, configured to establish communication connections for each data interface using communication lines, set a standardized communication protocol, and introduce an adaptive flow control algorithm to avoid packet loss and retransmission;

[0033] A communication interaction module, configured to separately create driver programs and communication software for the main processor and the coprocessor to implement data interaction and communication control between the processors.

[0034] In one embodiment, the protocol configuration module includes: a line connection module, a protocol optimization module, and a flow control module, where,

[0035] The circuit connection module is used to select corresponding communication circuits for connection based on the types of data interfaces in the main processor and the coprocessor. The communication circuits include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines;

[0036] The protocol optimization module is used to set a standardized communication protocol between the main processor and the coprocessor, and adopt XDMA technology to optimize the data transmission performance and achieve hardware acceleration through direct memory access;

[0037] The flow control module is used to utilize an adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate according to the network status.

[0038] In one embodiment, the communication interaction module includes: a driver management module and a communication transmission module, where,

[0039] The driver management module is used to create a driver program that meets the compatibility between the main processor and the coprocessor, and dynamically adjust the power supply according to the network status load. When in a low-load state, it switches to the low-power mode;

[0040] The communication transmission module is used to create a communication software for establishing data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technology to reduce the number of errors, retransmissions, and the amount of data during data transmission.

[0041] The technical solution provided by the embodiment of the present invention may include the following beneficial effects: By optimizing the PCIE interface configuration and communication protocol, the communication efficiency is significantly improved, the communication delay is reduced, and the overall performance of the system is enhanced. At the same time, it has good compatibility and scalability. The specific effects include:

[0042] 1. By improving the configuration parameters of the PCIE interface, such as increasing the data transmission width and optimizing the interrupt handling mechanism, the data transmission rate is significantly improved. Specifically, the data transmission rate is increased by 40%, and the communication delay is reduced by 30%. A more efficient communication protocol is adopted to reduce the header overhead of data packets and optimize the transmission order of data packets, thereby improving the data transmission efficiency. By introducing an advanced flow control algorithm, the stability and efficiency of data transmission are ensured.

[0043] 2. The present invention develops a set of general driver programs that can adapt to a variety of hardware devices, solving the compatibility problems between different devices. This not only reduces the difficulty of system integration, but also improves the maintainability and scalability of the system; A standardized communication protocol is adopted to ensure seamless communication between different devices. Through compatibility testing and verification, it is ensured that the system runs stably in a variety of hardware environments.

[0044] 3. Through a simplified PCIE interface configuration solution, a user-friendly configuration tool is provided. Users can quickly achieve the optimal configuration according to specific requirements. This tool has a graphical interface and is easy to operate. Even non-professional technical personnel can easily get started. Moreover, the system can automatically recommend the optimal configuration solution based on the detected hardware environment, reducing the complexity of manual adjustment by users and improving the overall performance of the system.

[0045] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0047] Figure 1 is a flowchart of a communication method based on a multi-core heterogeneous processing architecture shown according to an exemplary embodiment;

[0048] Figure 2 is a system block diagram of a communication system based on a multi-core heterogeneous processing architecture shown according to an exemplary embodiment;

[0049] Figure 3 is a schematic structural diagram of a main processor and a coprocessor shown according to an exemplary embodiment;

[0050] Figure 4 is an example diagram of a Block Design shown according to an exemplary embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] The following description and the accompanying drawings fully disclose specific embodiments herein, enabling those skilled in the art to practice them. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The scope of the embodiments herein includes the entire scope of the claims and all available equivalents of the claims. In this document, the terms "first", "second", etc. are only used to distinguish one element from another, without requiring or implying any actual relationship or order between these elements. In fact, the first element can also be called the second element, and vice versa. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a structure, device or equipment comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such structure, device or equipment. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the structure, device or equipment comprising the element. The embodiments herein are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0052] In this document, the orientation or positional relationships indicated by the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing this document and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In the description of this document, unless otherwise specified and defined, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or it can be the communication inside two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0053] In this document, unless otherwise stated, the term "plurality" means two or more.

[0054] In this document, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0055] In this document, the term "and / or" is an associative relationship describing an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B these three relationships.

[0056] It should be understood that although the various steps in the flowchart are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0057] Each module in the device or system of the present application can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor in the computer device in hardware form or be independent of it, or can be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above-mentioned modules.

[0058] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0059] Figure 1 An embodiment of a communication method based on a multi-core heterogeneous processing architecture of the present invention is shown.

[0060] In this alternative embodiment, the communication method based on the multi-core heterogeneous processing architecture includes:

[0061] Step S101: Optimize and configure the parameters of the high-speed serial computer expansion bus standard interface based on the data transmission requirements between the main processor and the coprocessor;

[0062] Step S102: Establish communication connections for each data interface using communication lines, set a standardized communication protocol, and introduce an adaptive flow control algorithm to avoid data packet loss and retransmission;

[0063] Step S103: Create the driver programs and communication software for the main processor and the coprocessor respectively to achieve data interaction and communication control between the processors.

[0064] In this alternative embodiment, when establishing communication connections for each data interface via communication lines, setting a standardized communication protocol, and introducing an adaptive flow control algorithm to avoid packet loss and retransmission, a corresponding communication line can be selected based on the types of data interfaces within the main processor and the coprocessor. The communication lines include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines. Set a standardized communication protocol between the main processor and the coprocessor, and use the XDMA technology to optimize data transmission performance and achieve hardware acceleration through direct memory access. Utilize the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate according to the network status.

[0065] In this alternative embodiment, the data transmission lines are used to connect the Peripheral Component Interconnect Express (PCIe) interface of the main processor to the PCIe interface of the coprocessor; the control signal lines are used to connect the PCIe controller of the main processor to the PCIe controller of the coprocessor; the memory access lines are used to connect the PCIe interface of the coprocessor to the memory; and the direct memory access channel lines are used to connect the direct memory access controller of the main processor to the direct memory access controller of the coprocessor.

[0066] In this alternative embodiment, when using the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate, the bandwidth utilization rate, packet loss rate, and transmission delay during the communication process between the main processor and the coprocessor can be monitored in real time, and the current network congestion situation can be presented through network status values. If any one of the network statuses exceeds the preset threshold, it is determined that there is network congestion, and the data transmission rate is reduced. If all network statuses are lower than the preset threshold, it is determined that the network is idle, and the data transmission rate is increased. The receiving end feeds back the network status information to the sending end, and the sending end optimizes the transmission strategy of the data to be sent in the next stage according to the feedback information to form a closed-loop control.

[0067] In this alternative embodiment, when creating the driver programs and communication software for the main processor and the coprocessor respectively to achieve data interaction and communication control between the processors, driver programs that meet the compatibility between the main processor and the coprocessor can be created, and the power supply can be dynamically adjusted according to the network status load. Switch to the low-power mode in the low-load state; create communication software for establishing data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technologies to reduce errors, retransmission times, and the amount of data during data transmission.

[0068] In this alternative embodiment, the driver includes functions such as Peripheral Component Interconnect Express (PCIe) interface initialization, XDMA initialization, data transfer control, and error handling.

[0069] Figure 2 An embodiment of a communication system based on a multi-core heterogeneous processing architecture according to the present invention is shown.

[0070] In this alternative embodiment, the communication system based on the multi-core heterogeneous processing architecture includes:

[0071] An interface optimization module 201 for optimizing and configuring the parameters of the Peripheral Component Interconnect Express (PCIe) interface based on the data transfer requirements between the main processor and the coprocessor;

[0072] A protocol configuration module 202 for establishing communication connections for each data interface using communication lines, setting a standardized communication protocol, and introducing an adaptive flow control algorithm to avoid packet loss and retransmission;

[0073] A communication interaction module 203 for respectively creating drivers and communication software for the main processor and the coprocessor to implement data interaction and communication control between the processors.

[0074] In this alternative embodiment, the protocol configuration module 202 includes: a line connection module (not shown in the figure), a protocol optimization module (not shown in the figure), and a flow control module (not shown in the figure). Among them, the line connection module is used to select corresponding communication lines for connection based on the types of data interfaces in the main processor and the coprocessor. The communication lines include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines; the protocol optimization module is used to set a standardized communication protocol between the main processor and the coprocessor, and use XDMA technology to optimize data transmission performance and achieve hardware acceleration through direct memory access; the flow control module is used to use an adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate according to the network status.

[0075] In this alternative embodiment, the communication interaction module 203 includes: a driver management module (not shown in the figure) and a communication transmission module (not shown in the figure). Among them, the driver management module is used to create a driver that meets the compatibility between the main processor and the coprocessor, and dynamically adjust the power supply according to the network status load. When in a low-load state, it switches to a low-power mode; the communication transmission module is used to create communication software for data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technologies to reduce errors, retransmission times, and data volume during data transmission.

[0076] The present invention will be further described in detail below in conjunction with specific embodiments.

[0077] The present invention proposes a communication method based on a (domestic) multi-core heterogeneous processing architecture. By optimizing the configuration and communication protocol of the PCIE interface (High-Speed Serial Computer Extension Bus Standard Interface), through the XDMA method, efficient communication between the RK3588 (main processor, a domestic industrial core board based on the Rockchip RK3588J / RK3588 high-performance processor, a domestic industrial core board designed with a quad-core ARM Cortex-A76 + quad-core ARM Cortex-A55) and the K7 of the FPGA (coprocessor, a hardware platform based on the XILINX KINTEX-7 chip XC7K325 FPGA) is achieved. The specific technical solutions include:

[0078] I. Optimized configuration of the PCIE interface: By optimizing parameters such as the number of channels, rate, and bandwidth of the PCIE interface, the efficiency and stability of data transmission are ensured.

[0079] Before optimization, the parameter settings of the PCIE interface were as follows:

[0080] 1. Number of channels: In the original configuration, the connection between the RK3588 and the K7 of the FPGA was PCIe2.0x4.

[0081] 2. Rate: The rate of PCIe2.0 is 5 GT / s (5 gigabits per second).

[0082] 3. Bandwidth: The theoretical bandwidth of PCIe2.0x4 is 20 GT / s, but due to factors such as protocol overhead, the actual available bandwidth is approximately 16 GT / s.

[0083] After optimization, the parameters of the PCIE interface are as follows:

[0084] 1. Number of channels: PCIe3.0x4.

[0085] 2. Rate: 8 GT / s.

[0086] 3. Bandwidth: The theoretical bandwidth is 32 GT / s, and the actual available bandwidth is approximately 27 GT / s.

[0087] It can be seen that the technical means targeted for optimization in the present invention include the following aspects:

[0088] 1. PCIE Interface (Peripheral Component Interconnect Express) Parameter Optimization: By adjusting parameters such as the number of channels, rate, and bandwidth of the PCIE interface, the efficiency and stability of data transmission are significantly improved. For example, increasing the number of channels to PCIe3.0x4 and the rate to 8GT / s, resulting in a theoretical bandwidth of 32GT / s and an actual available bandwidth of approximately 27GT / s.

[0089] 2. Communication Protocol Optimization: Adopting the XDMA (Xing Distributed Media Architecture) technology allows direct memory transfer of data between different devices, reducing CPU intervention and enhancing data transmission efficiency and speed. Meanwhile, optimizing the header overhead and transmission order of data packets and introducing advanced flow control algorithms ensure the stability and efficiency of data transmission.

[0090] 3. Hardware Driver and Software Implementation: Customized driver programs are developed respectively for RK3588 and K7 of FPGA, and communication software is designed to ensure the normal operation of hardware devices and achieve efficient data interaction and communication control, including initialization modules, XDMA initialization modules, data transmission control modules, and error handling modules, etc.

[0091] II. Efficient Communication Protocol Design: Using the XDMA technology (an efficient direct memory access technology that allows direct memory transfer of data between different devices without CPU intervention. This can not only reduce the CPU load but also significantly improve the efficiency and speed of data transmission). Compared with traditional technologies, the XDMA technology can significantly enhance the transmission performance. Through direct memory access and hardware acceleration, the XDMA technology can increase the data transmission rate by more than 30%. By reducing CPU intervention and intermediate links, the XDMA technology can reduce the communication delay by more than 50%.

[0092] III. Hardware Driver and Software Implementation: Corresponding driver programs are developed respectively for RK3588 and K7 of FPGA, and communication software is designed to ensure the normal operation of hardware devices and achieve efficient data interaction and communication control.

[0093] The functional module set of this hardware design of the driver program includes:

[0094] 1. Initialization Module: Responsible for the initialization of the PCIE interface, including configuring parameters such as the number of channels, rate, and bandwidth.

[0095] 2. XDMA Initialization Module: Responsible for initializing the XDMA controller and configuring relevant parameters for data transmission.

[0096] 3. Data Transmission Control Module: Responsible for controlling the sending and receiving of data, including data encapsulation, verification, retransmission, etc.

[0097] 4. Error handling module: Responsible for handling errors that occur during data transmission, including error detection, error reporting, and error recovery.

[0098] In addition, the connections between each functional module in the driver and related algorithms include the following aspects:

[0099] 1. Adaptive flow control algorithm: The data transmission control module dynamically adjusts the data transmission rate and flow control parameters by monitoring the network status in real time, optimizing the data transmission efficiency.

[0100] 2. Forward error correction coding (FEC): During data transmission, by adding redundant information to data packets, the errors and retransmission times in data transmission are reduced, improving the reliability and efficiency of data transmission.

[0101] 3. Data compression algorithm: Compresses the transmitted data, reduces the amount of data transmission, lowers the bandwidth occupancy, and improves the communication efficiency.

[0102] In addition, the connections between the driver and the low-power mode include the following aspects:

[0103] 1. Dynamic power management: Dynamically adjusts the power supply according to the load situation of the system. When the load is low, reduces the power supply voltage and frequency to reduce energy consumption; when the load is high, ensures sufficient power supply to guarantee the system performance.

[0104] 2. Low-power mode switching: When the system is in an idle state, automatically enters the low-power mode to further reduce energy consumption. By optimizing the hardware circuit and software algorithm, ensures that the system can still quickly respond to external events in the low-power mode.

[0105] The present invention significantly improves the communication efficiency, reduces the communication latency, enhances the overall performance of the system, and at the same time has good compatibility and scalability by optimizing the PCIE interface configuration and communication protocol.

[0106] Specific effects include:

[0107] I. Improvement in communication efficiency

[0108] Optimizing the PCIE interface configuration: By improving the configuration parameters of the PCIE interface, such as increasing the data transmission width and optimizing the interrupt handling mechanism, the data transmission rate is significantly improved. Specifically, the data transmission rate is increased by 40%, and the communication latency is reduced by 30%.

[0109] Optimizing the communication protocol: Adopting a more efficient communication protocol, reducing the header overhead of data packets, and optimizing the transmission order of data packets, thereby improving the data transmission efficiency. By introducing an advanced flow control algorithm, ensuring the stability and efficiency of data transmission.

[0110] II. Enhanced Compatibility

[0111] Unified driver design: Developed a set of general drivers that can adapt to a variety of hardware devices, solving the compatibility problems between different devices. This not only reduces the difficulty of system integration but also improves the maintainability and scalability of the system.

[0112] Standardized communication protocol: Adopted a standardized communication protocol to ensure seamless communication between different devices. Through compatibility testing and verification, it is guaranteed that the system can operate stably in a variety of hardware environments.

[0113] III. Simplified Configuration

[0114] Simplified PCIE interface configuration scheme: Provided a set of user-friendly configuration tools that allow users to quickly achieve optimal configuration according to specific needs. This set of tools has a graphical interface and is easy to operate, enabling even non-professional technical personnel to get started easily.

[0115] Automated configuration recommendation: The system can automatically recommend the optimal configuration scheme based on the detected hardware environment, reducing the complexity of manual adjustment by users and enhancing the overall performance of the system.

[0116] IV. Power Consumption Optimization

[0117] Dynamic power management: Introduced dynamic power management technology to automatically adjust the power supply according to the system load. When the load is low, the power voltage and frequency are reduced to reduce unnecessary energy consumption; when the load is high, sufficient power supply is ensured to guarantee system performance.

[0118] Low-power mode switching: Designed an intelligent low-power mode switching mechanism at the software level. The system continuously monitors indicators such as CPU usage, memory occupancy, and task queue length. When these indicators are below the set threshold, the system determines it as a low-load state and triggers a switch to the low-power mode. On the contrary, when it detects an increase in system load and the indicators exceed the threshold, the system will quickly switch back to the high-performance mode to meet task requirements.

[0119] V. Communication Optimization Algorithm Model

[0120] Adaptive flow control algorithm: Developed an adaptive flow control algorithm that can dynamically adjust the data transmission rate and flow control parameters according to the network conditions. This algorithm automatically adjusts the sending window size by real-time monitoring of network congestion, avoiding packet loss and retransmission, and improving communication efficiency.

[0121] Among them, the content of the adaptive flow control algorithm includes the following aspects:

[0122] 1. Network status monitoring

[0123] Monitor the network status in real time, including key metrics such as bandwidth utilization, packet loss rate, and transmission delay. These metrics can reflect the current load and communication quality of the network.

[0124] 2. Transmission Rate Adjustment

[0125] According to the monitored network status, dynamically adjust the data transmission rate. When the network is congested (such as high bandwidth utilization and increasing packet loss rate), reduce the transmission rate to reduce congestion; when the network is idle (such as low bandwidth utilization and low packet loss rate), increase the transmission rate to make full use of resources.

[0126] 3. Feedback Mechanism

[0127] The receiving end feeds back the network status information to the sending end, and the sending end further optimizes the transmission strategy based on this information to form a closed-loop control to ensure the efficiency and reliability of data transmission.

[0128] In addition, the monitoring objects and carriers of the adaptive flow control algorithm include:

[0129] 1. Monitoring Objects

[0130] Bandwidth utilization: Monitor the amount of data transmitted over the network per unit time to evaluate the network load.

[0131] Packet loss rate: Count the number of lost packets within a certain period of time to evaluate the stability and reliability of the network.

[0132] Transmission delay: Measure the round-trip time of a packet from the sending end to the receiving end to evaluate the real-time performance and response speed of the network.

[0133] 2. Carriers

[0134] Hardware carrier: The algorithm runs in an embedded system, and the main carriers include the RK3588 processor and the K7 of FPGA.

[0135] Software carrier: The algorithm is implemented in communication software and integrated into the data transmission control module.

[0136] Forward Error Correction (FEC): Introduce forward error correction coding technology in the communication protocol to reduce errors and retransmission times during data transmission. By adding redundant information to the data packet, the receiving end can correct some errors without requesting retransmission, improving the reliability and efficiency of data transmission.

[0137] Data compression algorithm: Adopt an efficient data compression algorithm to reduce the amount of data transmitted. Compress the transmitted data through the compression algorithm to reduce the bandwidth occupancy of data transmission and improve communication efficiency.

[0138] The present invention will be further described in detail below with reference to the accompanying drawings.

[0139] As Figure 3 shown, the respective functional structures, circuit connections, data interactions, and communication controls of the main processor and the coprocessor include the following aspects:

[0140] 1. CPU side

[0141] Function: As the main processor, it is responsible for overall data processing and system control. The RK3588 has 4 A76 core processors and 4 A55 core processors, supports multi-threaded processing, and is suitable for high-performance computing, image processing, artificial intelligence, and other scenarios.

[0142] 2. FPGA side

[0143] Function: As the coprocessor, it is responsible for high-speed data processing and real-time signal processing. It has high flexibility and programmability and can be customized according to specific requirements.

[0144] 3. PCIE interface

[0145] Function: As the communication bridge between the RK3588 and the K7 of the FPGA, it supports high-speed data transmission. It has the characteristics of high bandwidth and low latency and can meet the communication requirements of the multi-core heterogeneous processing architecture.

[0146] 4. Data transmission line

[0147] Function: Connects the PCIE interface of the RK3588 and the PCIE interface of the K7 of the FPGA and is responsible for high-speed data transmission.

[0148] 5. Control signal line

[0149] Function: Connects the PCIE controller of the RK3588 and the PCIE controller of the K7 of the FPGA and is responsible for transmitting control signals to ensure the synchronization and coordination of communication.

[0150] 6. Memory access line

[0151] Function: Connects the PCIE interface of the K7 of the FPGA and the DDR3 memory and is responsible for data reading, writing, and caching operations.

[0152] 7. DMA channel line (Direct Memory Access channel line)

[0153] Function: Connects the DMA controller of the RK3588 and the DMA controller of the K7 of the FPGA and is responsible for realizing direct memory access of data through XDMA technology.

[0154] The specific implementation scheme is as follows:

[0155] I. Communication protocol

[0156] 1. PCIE Protocol Configuration: Optimize the configuration of the PCIE interface, including settings of parameters such as the number of channels, rate, and bandwidth, to improve communication efficiency. By dynamically adjusting the configuration parameters of the PCIE interface, ensure the high efficiency and stability of data transmission.

[0157] 2. Data Transmission Protocol: Design an efficient data transmission protocol to ensure accurate and fast data transmission between RK3588 and K7 of FPGA. The data transmission protocol includes data encapsulation, verification, retransmission mechanism, etc., to ensure the integrity and reliability of data.

[0158] II. Implementation on the RK3588 Side

[0159] 1. Driver Development: Develop corresponding drivers for RK3588 to ensure the normal operation of hardware devices. The driver includes functions such as initialization of the PCIE interface, XDMA initialization, data transmission control, and error handling.

[0160] 2. Communication Software Design: Develop communication software to achieve data interaction and communication control between RK3588 and K7 of FPGA. The communication software includes functions such as data sending, receiving, and processing to ensure the efficient operation of the system.

[0161] III. Implementation on the FPGA Side

[0162] The FPGA project includes a DDR controller and a PCIe controller, which can cooperate with RK3588 to enable software to read and write the DDR3 of FPGA through PCIe. The example diagram of the Block Design is shown in Figure 4:

[0163] 1. Optimization Configuration of PCIE Interface and Design of High-Efficiency Communication Protocol

[0164] xdma_0 Module: This module communicates with the host system through the PCIE interface. Optimizing the PCIE interface configuration can improve the data transmission rate and reduce communication latency. For example, by configuring an appropriate interrupt handling mechanism and data transmission mode, ensure that data can be transmitted quickly and stably on the PCIE bus.

[0165] axi_interconnect_0 Module: As an interconnect module for the AXI bus (Advanced eXtensible Interface bus), it is responsible for connecting multiple AXI master devices and slave devices. By optimizing the configuration and communication protocol of the AXI bus, improve the communication efficiency of the entire system. For example, adopting an efficient arbitration algorithm and data transmission protocol can reduce the waiting time and conflicts of data transmission.

[0166] 2. Design of High-Efficiency Communication Protocol and Hardware Driver and Software Implementation

[0167] axi_bram_ctrl_0 module: This module manages the read and write operations of the block RAM. An efficient communication protocol design can ensure more efficient data transfer between the AXI bus and the block RAM. For example, by designing a reasonable data packet format and transfer order, the overhead and latency of data transfer can be reduced.

[0168] mig_7series_0 module: Responsible for connecting to the external DDR memory. An efficient communication protocol and hardware driver can ensure fast data transfer between the memory and the processor. For example, by optimizing the configuration of the memory controller and adopting an efficient memory access protocol, the overall performance of the system can be improved.

[0169] 3. Optimization Configuration, Hardware Driver and Software Implementation of the PCIE Interface

[0170] clk_wiz_0 and proc_sys_reset_0 modules: These two modules provide the system clock and reset signals. By optimizing the configuration of these modules, the entire system can be ensured to operate in a stable state, thereby improving the communication efficiency between the PCIE interface and other modules.

[0171] blk_mem_gen_0 module: The generated block RAM is used for data storage. The hardware driver needs to correctly configure and manage these storage resources to ensure efficient data read and write operations. For example, by optimizing the driver of the storage controller, the access speed and reliability of the block RAM can be improved.

[0172] The present invention is not limited to the structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A communication method based on a multi-core heterogeneous processing architecture, characterized in that Including: Optimally configure the parameters of the high-speed serial computer expansion bus standard interface based on the data transfer requirements between the main processor and the coprocessor; Establish communication connections for each data interface using communication lines, set a standardized communication protocol, and introduce an adaptive flow control algorithm to avoid packet loss and retransmission; Create the driver programs and communication software for the main processor and the coprocessor respectively to achieve data interaction and communication control between the processors; 2. The communication method based on the multi-core heterogeneous processing architecture according to claim 1, wherein The step of establishing communication connections for each data interface using communication lines, setting a standardized communication protocol, and introducing an adaptive flow control algorithm to avoid packet loss and retransmission includes: Select corresponding communication lines for connection based on the types of data interfaces in the main processor and the coprocessor. The communication lines include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines; Set a standardized communication protocol between the main processor and the coprocessor, and use the XDMA technology to optimize the data transmission performance and achieve hardware acceleration through direct memory access; Utilize the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate according to the network status; 3. The communication method based on the multi-core heterogeneous processing architecture according to claim 1, wherein The parameters of the high-speed serial computer expansion bus standard interface include: the number of channels, rate, and bandwidth; 4. The communication method based on a multi-core heterogeneous processing architecture according to claim 1, characterized in that, The data transmission lines are used to connect the high-speed serial computer expansion bus standard interface of the main processor and the high-speed serial computer expansion bus standard interface of the coprocessor; the control signal lines are used to connect the high-speed serial computer expansion bus standard controller of the main processor and the high-speed serial computer expansion bus standard controller of the coprocessor; The memory access lines are used to connect the high-speed serial computer expansion bus standard interface of the coprocessor and the memory; the direct memory access channel lines are used to connect the direct memory access controller of the main processor and the direct memory access controller of the coprocessor; 5. The communication method based on the multi-core heterogeneous processing architecture according to claim 1, characterized in that, The step of utilizing the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transmission rate includes: Monitor the bandwidth utilization rate, packet loss rate, and transmission delay during the communication between the main processor and the coprocessor in real time, and display the current network congestion situation through network status values; If any one of the network status exceeds the preset threshold, it is determined that there is network congestion, and the data transmission rate is reduced. If all network status are lower than the preset threshold, it is determined that the network is idle, and the data transmission rate is increased; The receiving end feeds back the network status information to the sending end, and the sending end optimizes the transmission strategy of the data to be sent in the next stage according to the feedback information to form a closed-loop control; 6. The communication method based on the multi-core heterogeneous processing architecture according to claim 1, wherein The step of creating the driver programs and communication software for the main processor and the coprocessor respectively to achieve data interaction and communication control between the processors includes: Create driver programs that meet the compatibility between the main processor and the coprocessor, and dynamically adjust the power supply according to the network status load. Switch to the low-power mode in the low-load state; Create communication software for data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technology to reduce errors, retransmission times, and data volume during data transmission.

7. The communication method based on a multi-core heterogeneous processing architecture according to claim 1, characterized in that The driver includes functions such as initialization of the Peripheral Component Interconnect Express (PCIe) interface, initialization of XDMA, data transfer control, and error handling.

8. A communication system based on a multi-core heterogeneous processing architecture, characterized in that, It includes: An interface optimization module for optimizing the configuration of the parameters of the Peripheral Component Interconnect Express (PCIe) interface based on the data transfer requirements between the main processor and the coprocessor. A protocol configuration module for establishing communication connections for each data interface using communication lines, setting a standardized communication protocol, and introducing an adaptive flow control algorithm to avoid packet loss and retransmission. A communication interaction module for separately creating the driver and communication software for the main processor and the coprocessor to achieve data interaction and communication control between the processors.

9. The communication system based on the multi-core heterogeneous processing architecture according to claim 8, characterized in that The protocol configuration module includes: a line connection module, a protocol optimization module, and a flow control module. Among them, The line connection module is used to select the corresponding communication line connection based on the types of data interfaces in the main processor and the coprocessor. The communication lines include data transmission lines, control signal lines, memory access lines, and direct memory access channel lines. The protocol optimization module is used to set the standardized communication protocol between the main processor and the coprocessor, and use XDMA technology to optimize data transfer performance and achieve hardware acceleration through direct memory access. The flow control module is used to use the adaptive flow control algorithm to monitor the network status between the main processor and the coprocessor in real time and dynamically adjust the data transfer rate according to the network status.

10. The communication system based on the multi-core heterogeneous processing architecture according to claim 8, wherein The communication interaction module includes: a driver management module and a communication transmission module. Among them, The driver management module is used to create a driver that meets the compatibility between the main processor and the coprocessor, and dynamically adjust the power supply according to the network status load. It switches to the low-power mode in the low-load state. The communication transmission module is used to create communication software for data interaction between the main processor and the coprocessor, and introduce forward error correction coding and data compression technology to reduce the number of errors, retransmissions, and the amount of data in data transmission.

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