On-chip power-on initialization method and device, and chip

Abstract

The application provides a chip power-on initialization method and device and a chip. The method is applied to the chip. The method comprises the following steps: after the chip is powered on and waits for the POR reset to end, automatically reading the pre-stored initialization program instruction into the user-specified address segment in the register through the one-time programmable memory or the read-only memory; the initialization program instruction is set by the user according to the actual application scenario; based on the initialization program instruction written in the address segment, the initialization program is automatically triggered to execute, and the power-on initialization of the chip is completed; the initialization program execution is used for adopting a pipeline architecture, starting serial instruction analysis processing from a starting address after a trigger signal is detected, and stopping the instruction analysis processing when an ending address is identified. The application can guarantee high efficiency, reliability and low cost, and provide high programmability and flexibility to meet the diversified needs of modern integrated circuit design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a chip power-on initialization method, apparatus and chip. Background Technology

[0002] In modern integrated circuit design, chip power-on initialization is a crucial step. The rationality and efficiency of the initialization process directly affect the chip's performance, stability, and startup time. Traditional chip initialization processes typically rely on fixed hardware logic or external control signals. While these methods are simple to implement, they suffer from limitations such as lack of flexibility, poor scalability, long development cycles, and inadequate error handling mechanisms. To address these issues, the industry has proposed several improvement schemes. For example, using microcontrollers (MCUs) to implement some initialization operations and improving flexibility through software control, or a small number of high-end chips using programmable logic devices (such as FPGAs) to implement the initialization process. However, these approaches still struggle to balance flexibility, scalability, development efficiency, and cost control. Summary of the Invention

[0003] The purpose of this application is to provide a chip power-on initialization method, apparatus, and chip that can provide high programmability and flexibility while ensuring high efficiency, reliability, and low cost, so as to meet the diverse needs of modern integrated circuit design.

[0004] In a first aspect, this application provides a chip power-on initialization method, which is applied to a chip; the method includes: after the chip is powered on and waits for a POR reset, automatically reading back the pre-stored initialization program instructions into a user-specified address segment in a register through a one-time programmable memory or read-only memory; the initialization program instructions are set by the user according to the actual application scenario; based on the initialization program instructions written to the address segment, the initialization program is automatically triggered to complete the power-on initialization of the chip; the initialization program execution is used to adopt a pipelined architecture, and after detecting a trigger signal, serial instruction parsing and processing is performed starting from the start address, and instruction parsing and processing is stopped when the end address is identified.

[0005] Furthermore, the aforementioned initialization program instructions include multiple subroutine instructions; the fields corresponding to each subroutine instruction include three parts: instruction synchronization header, instruction number, and instruction mode.

[0006] Furthermore, before the step of automatically reading back the pre-stored initialization program instructions to the user-specified address segment in the register via a one-time programmable memory or read-only memory, the method further includes: in response to the user's initialization program configuration operation based on the actual application scenario, storing the user-edited initialization program in a one-time programmable memory or read-only memory.

[0007] Furthermore, the steps for automatically triggering the execution of the initialization program based on the initialization program instruction written to the address segment include: performing serial instruction parsing processing starting from the starting address, sequentially identifying and parsing multiple subroutine instructions included in the initialization program instruction, and stopping instruction parsing processing until the end address is identified.

[0008] Furthermore, after completing the power-on initialization steps of the chip, the process also includes: responding to the user's configuration operations on the start and end addresses of the target program segment in the registers, as well as a manual trigger operation, to execute the target program segment in order to complete the function corresponding to the target program segment.

[0009] Furthermore, the bit width of the data stored at each of the above addresses is determined according to the specific data bus width used, including 8 bits, 16 bits, or 32 bits.

[0010] Furthermore, the above instruction mode includes at least one of the following: sequential serial write operation instructions, sequential serial read operation instructions, counting and waiting instructions to complete the corresponding clock cycle according to the configuration, waiting instructions by querying at fixed cycles and comparing with the target value to see if they are consistent, sequential periodic loop operation instructions, entering general arithmetic operation instructions, entering immediate value arithmetic operation instructions, entering unconditional address jump operation instructions, and entering conditional address jump operation instructions.

[0011] Furthermore, the instruction content for the sequential serial write operation instructions mentioned above includes: base address, offset address, and write data, wherein the offset address and write data appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, and storage index, wherein the offset address and storage index appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address based on the data read from the storage index; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, readback data storage index, and number of write addresses; these four pieces of information appear only once in the instruction, indicating that the logic completes the writing of the corresponding configuration to the corresponding address based on the data read from the readback data storage index and the number of write addresses.

[0012] Secondly, this application also provides a chip power-on initialization device, which is applied to a chip; the device includes: a program readback module, used to automatically read back the pre-stored initialization program instructions to the user-specified address segment in the register through a one-time programmable memory or read-only memory after the chip is powered on and waiting for POR reset; the initialization program instructions are set by the user according to the actual application scenario; an initialization module, used to automatically trigger the execution of the initialization program based on the initialization program instructions written to the address segment, to complete the power-on initialization of the chip; the initialization program execution adopts a pipelined architecture, and performs serial instruction parsing processing from the start address after detecting the trigger signal, and stops instruction parsing processing when the end address is identified.

[0013] Thirdly, this application also provides a chip for performing the chip power-on initialization method as described in the first aspect.

[0014] The chip power-on initialization method, apparatus, and chip provided in this application are applied to a chip. The method includes: after the chip is powered on and waits for a POR reset, automatically reading back the pre-stored initialization program instructions into a user-specified address segment in a register via a one-time programmable memory or read-only memory; the initialization program instructions are set by the user according to the actual application scenario; based on the initialization program instructions written to the address segment, the initialization program is automatically triggered to complete the chip's power-on initialization; the initialization program execution uses a pipelined architecture, performing serial instruction parsing processing from the start address after detecting a trigger signal, and stopping instruction parsing processing when the end address is identified. In this application, users can pre-store the corresponding initialization program instructions in a one-time programmable memory or read-only memory according to the actual application scenario requirements, and complete the power-on initialization process that meets the user's needs through program reading and execution. This provides high programmability and flexibility while ensuring high efficiency, reliability, and low cost, to meet the diverse needs of modern integrated circuit design. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 A flowchart illustrating a chip power-on initialization method provided in this application embodiment;

[0017] Figure 2 A schematic diagram of an initialization process provided in an embodiment of this application;

[0018] Figure 3 A schematic diagram illustrating a chip power-on initialization process provided in an embodiment of this application;

[0019] Figure 4 A schematic diagram of an instruction mode provided for an embodiment of this application;

[0020] Figure 5 This is a structural block diagram of a chip power-on initialization method apparatus provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Traditional chip initialization processes typically rely on fixed hardware logic or external control signals. While these methods are simple and easy to implement, they have the following limitations:

[0023] (1) Lack of flexibility: Traditional initialization processes are usually fixed by hardware logic and cannot be adjusted according to different application scenarios.

[0024] (2) Poor scalability: As chip functions become more complex, the types and number of peripheral modules continue to increase. Traditional initialization methods are unable to support diverse peripheral configurations, resulting in low development efficiency.

[0025] (3) Long development cycle: Each modification to the initialization process requires redesigning the hardware logic or adjusting the external control signals, which increases the development cycle and cost.

[0026] (4) Inadequate error handling mechanism: Traditional initialization processes often lack a complete status feedback and error handling mechanism. If an error occurs during initialization, the system may not be able to detect it in time and take corresponding measures, causing the chip to malfunction.

[0027] To address these issues, the industry has proposed several improvements. For example, using a microcontroller (MCU) to perform some initialization operations and improving flexibility through software control. However, this method requires internal integration of the MCU and corresponding software adaptation, necessitating additional hardware resources. Furthermore, MCU loading requires the use of Flash memory; integrating Flash on-chip increases system complexity and cost, while off-chip integration reduces the chip's integration density and ease of use. On the other hand, software-executed initialization processes are relatively slow, impacting chip power-on startup time. Additionally, a small number of high-end chips use programmable logic devices (such as FPGAs) to implement the initialization process. However, while this method improves flexibility, it results in significant cost waste and is unsuitable for low-cost chips requiring mass production. Moreover, the configuration interface needs to be exposed to customers, increasing the complexity of the delivery process and reducing usability.

[0028] In summary, existing chip power-on initialization technologies struggle to balance flexibility, scalability, development efficiency, and cost control.

[0029] Based on this, embodiments of this application provide a chip power-on initialization method, apparatus, and chip, which can provide high programmability and flexibility while ensuring high efficiency, reliability, and low cost, to meet the diverse needs of modern integrated circuit design. To facilitate understanding of this embodiment, a chip power-on initialization method disclosed in this application will first be described in detail.

[0030] Figure 1 This application provides a chip power-on initialization method and flowchart, which is applied to a chip; the method specifically includes the following steps:

[0031] Step S102: After the chip is powered on and waits for the POR reset to complete, the pre-stored initialization program instructions are automatically read back to the user-specified address segment in the register through a one-time programmable memory or read-only memory; the initialization program instructions are set by the user according to the actual application scenario.

[0032] The above-mentioned chip power-on and wait for the POR reset to finish is an automatic detection method for the initialization trigger signal. In actual use, manual initialization trigger signals can also be implemented. For example, the initialization trigger signal generated by manual operation can be received through SPI. At this time, the pre-stored initialization program instructions will also be automatically read back to the user-specified address segment in the register through the one-time programmable memory or read-only memory.

[0033] Step S104: Based on the initialization program instruction written to the address segment, the initialization program is automatically triggered to complete the power-on initialization of the chip. The initialization program is executed using a pipelined architecture. After detecting the trigger signal, it performs serial instruction parsing and processing from the start address and stops instruction parsing and processing when the end address is identified.

[0034] The execution process of the initialization program is as follows: Figure 2 As shown, a pipelined architecture is adopted. After the trigger signal is detected, serial instruction parsing and processing begins from the start address (start_addr). When the end address (end_addr) is detected, instruction parsing and processing stops. The bit width of the data stored at each address can be determined according to the specific data bus width used (such as 8-bit / 16-bit / 32-bit).

[0035] In other words, the steps for automatically triggering the execution of the initialization program based on the initialization program instruction written to the address segment include: starting from the starting address, performing serial instruction parsing and processing, sequentially identifying and parsing multiple subroutine instructions included in the initialization program instruction, and stopping instruction parsing and processing until the ending address is identified, thereby completing the automatic power-on initialization.

[0036] The above initialization program instructions include multiple subroutine instructions; the fields corresponding to each subroutine instruction include three parts: instruction synchronization header Instr_syn 0xF1 (the data read from the corresponding address is 0xF1, which means the instruction synchronization header has been found, and it can also be customized), instruction number Instr_idx (the rule is that the high 4 bits and the low 4 bits are reversed, and 0x00 is an illegal instruction), and instruction mode Instr_sub (stores the specific instruction mode to be executed).

[0037] The chip power-on initialization method provided in this application is a programmable automatic power-on initialization method suitable for various chip designs that require automatic initialization upon power-on. Compared with traditional solutions, it has a simple structure, high integration, and flexible programmability and functional expandability. It can be customized with minimal hardware resource consumption by combining EFUSE or ROM storage units according to specific application scenarios.

[0038] See Figure 3 As shown, the above automatic initialization process and method are used in the following scenarios:

[0039] (1) The initialization program instructions are pre-written into EFUSE (one-time programmable memory) or ROM (read-only memory) according to the functional requirements. After the chip is powered on, after waiting for the POR reset to finish, EFUSE automatically reads back the initialization program instructions to the register address segment specified by the user and triggers the initialization process to complete the power-on initialization of the chip.

[0040] In practical applications, before the above-mentioned EFUSE automatically reads back the initialization program instructions to the user-specified register address segment and triggers the initialization process, it also includes: responding to the user's initialization program instruction configuration operation according to the actual application scenario, and storing the user-edited initialization program instructions into a one-time programmable memory or read-only memory.

[0041] In practice, users can pre-write the initialization program instructions into EFUSE (One-Time Programmable Memory) or ROM (Read-Only Memory) according to the functional requirements of the actual application scenario.

[0042] (2) This initialization process also supports scenarios that require reconfiguration after power-on initialization. You only need to configure the start and end addresses of the program segment through the register and complete other functional requirements by manually triggering it.

[0043] That is, after the above-mentioned steps of power-on initialization of the chip, it also includes: responding to the user's configuration operation of the start address and end address of the target program segment in the register, as well as the manual trigger operation, executing the target program segment to complete the function corresponding to the target program segment.

[0044] This embodiment supports a rich set of instruction modes (Instr_sub), which users can combine according to their actual application scenarios. These modes include, but are not limited to, the following (taking 8 bits of data per address as an example, which can be expanded to 16 bits / 32 bits). That is, the above instruction modes include at least one of the following: sequential serial write operation instructions, sequential serial read operation instructions, counting and waiting instructions to complete the corresponding clock cycle according to the configuration, waiting instructions by querying at fixed intervals and comparing with the target value to see if they are consistent, sequential periodic loop operation instructions, entering general arithmetic operation instructions, entering immediate value arithmetic operation instructions, entering unconditional address jump operation instructions, and entering conditional address jump operation instructions.

[0045] Furthermore, the instruction content for the sequential serial write operation instructions mentioned above includes: base address, offset address, and write data, wherein the offset address and write data appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, and storage index, wherein the offset address and storage index appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address based on the data read from the storage index; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, readback data storage index, and number of write addresses; these four pieces of information appear only once in the instruction, indicating that the logic completes the writing of the corresponding configuration to the corresponding address based on the data read from the readback data storage index and the number of write addresses.

[0046] See Figure 4 As shown, the specific details of the various instruction modes are as follows:

[0047] (1) Single write instruction: Indicates that serial write operations are performed sequentially. The instruction content includes the base address (the high 7 bits of the 15-bit address, which appears only once in a set of instructions), the offset address (the low 8 bits of the 15-bit address), and the write data. The offset address and the write data appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address.

[0048] (2) Single read instruction: Indicates that serial read operation is performed sequentially. The instruction content includes the base address (the high 7 bits of the 15-bit address, which appears only once in a set of instructions), the offset address (the low 8 bits of the 15-bit address), and the index for storing the read data. The offset address and the storage index appear in pairs, indicating that the logical record reports the data at the corresponding address.

[0049] (3) wait_td instruction: The instruction completes the counting wait for the corresponding clock cycle according to the configuration. The instruction content is the counting clock cycle setting, which is fixed at 4 8 bits. The total waiting time is 4 8 bits concatenated. After the counting wait is completed, the subsequent instruction processing will continue.

[0050] (4) wait_if instruction: Waits by querying and comparing the target value at fixed intervals (e.g., once per clock cycle, configurable). Instruction content: base address (the high 7 bits of a 15-bit address, appearing only once in a set of instructions), offset address (the low 8 bits of a 15-bit address), and the target value to be compared with the readback information. Since the read operation is asynchronous, at least two consistent operations are required to ensure that the exit condition is met. Once the above conditions are met, the wait instruction exits and subsequent instructions are parsed and processed. To prevent infinite waiting, a counter is performed synchronously. If the waiting period exceeds the set value, the wait instruction exits abnormally and subsequent instructions are processed, while the abnormal information is reported.

[0051] (5) Single write idx instruction: Indicates to perform serial write operations sequentially. The instruction content includes the base address (the high 7 bits of the 15-bit address, which appears only once in a set of instructions), the offset address (the low 8 bits of the 15-bit address), and the storage index (indicating the storage of readback and reporting data). The offset address and the storage index appear in pairs, and the instruction logic writes the corresponding configuration to the corresponding address based on the data read from the storage index.

[0052] (6) Multi Write IDX instruction: Indicates that serial write operations are performed sequentially. The instruction content includes the base address (the high 7 bits of the 15-bit address), the offset address (the low 8 bits of the 15-bit address), the index for storing readback data, and the number of write addresses. The above information appears only once in the instruction. The logic completes the writing of the corresponding configuration to the corresponding address based on the data read from the storage index and the number of writeback data.

[0053] (7) cyc trig instruction: Instructs to perform cyclic operation in sequence. The instruction content includes the cycle period setting (fixed to 3 8-bit, but can also be configured according to requirements), the address segment start address (including the base address (the high 7 bits of the 15-bit address) and the offset address (the low 8 bits of the 15-bit address)), the address segment end address (including the base address (the high 7 bits of the 15-bit address) and the offset address (the low 8 bits of the 15-bit address), and the logic completes the cyclic operation of the corresponding address segment according to the cycle period information and the address segment information.

[0054] (8) count_r instruction: Indicates entry into general arithmetic operations. The instruction content includes the index for storing the operation result (the high 4 bits of the 8-bit data), the operation mode selection (the low 4 bits of the 8-bit data, 4'b0000: ADD (addition), 4'b0001: SUB (subtraction), 4'b0010: SLL (left shift), 4'b0011: SLT (signed number a / b comparison, set to 1 if a is less than b, otherwise set to zero), 4'b0100: SLTU (no operation). Comparison of signed numbers a / b (set to 1 if a is less than b, otherwise set to 0), 4'b0101: XOR (bitwise exclusive OR), 4'b0110: SRL (unsigned right shift), 4'b0111: SRA (signed right shift), 4'b1000: OR (bitwise OR), 4'b1001: AND (bitwise AND), operand index (the lower 4 bits of the 8-bit data correspond to the index of operand 1, and the higher 4 bits of the 8-bit data correspond to the index of operand 2);

[0055] (9) `count_i` instruction: Indicates entry into immediate operation. The instruction content includes the index for storing the operation result (the high 4 bits of the 8-bit data), the operation mode selection (the low 4 bits of the 8-bit data, 4'b0000: ADDI (addition), 4'b0011: SLTI (signed number a / immediate comparison, a is set to 1 if less than the immediate number, otherwise it is set to zero), 4'b0100: SLTIU (unsigned number a / immediate comparison, a is set to 1 if less than the immediate number, otherwise it is set to zero), 4 'b0101: XORI (bitwise XOR), 4'b1000: ORI (bitwise OR), 4'b1001: ANDI (bitwise AND), 4'b0010: SLLI (left shift immediate), 4'b0110: SRLI (unsigned right shift immediate), 4'b0111: SRAI (signed right shift immediate), operand index (the lower 4 bits of the 8-bit data are stored as the index corresponding to the value of operand 1, and the higher 4 bits of the 8-bit data are invalid), immediate value;

[0056] (10) uncond_jump instruction: indicates to enter an unconditional address jump operation. The instruction content is the jump address configuration (including the base address (the high 7 bits of the 15-bit address) and the offset address (the low 8 bits of the 15-bit address)).

[0057] (11) cond_jump instruction: Indicates entry into conditional address jump operation. The instruction content includes the operation mode selection (lower 4 bits of 8-bit data, 4'b0000: BEQ (jump if a / b are equal), 4'b0001: BNE (jump if a / b are not equal), 4'b0010: BLT (jump if signed number a is less than signed number b), 4'b0011: BGE (jump if signed number a is less than or equal to signed number b), 4'b0100: BLTU (jump if unsigned number a is less than unsigned number b), 4'b0101: BGEU (jump if unsigned number a is less than or equal to unsigned number b)) and jump address configuration (including base address (higher 7 bits of 15-bit address) and offset address (lower 8 bits of 15-bit address)).

[0058] All of the above instruction modes support free combination and customized modification. Other instruction modes for specific application scenarios can also be extended based on this method.

[0059] Compared with the prior art, the chip power-on initialization method provided in this application has the following advantages: programmability and functional scalability, high frequency upper limit under pipeline structure, simple structure, strong robustness, and can complete the initialization process with minimal hardware resource overhead.

[0060] Based on the above method embodiments, this application also provides a chip power-on initialization device, which is applied to a chip; see also Figure 5 As shown, the device includes: a program readback module 52, used to automatically read back the pre-stored initialization program instructions to the user-specified address segment in the register via a one-time programmable memory or read-only memory after the chip is powered on and waiting for the POR reset; the initialization program instructions are set by the user according to the actual application scenario; an initialization module 54, used to automatically trigger the execution of the initialization program based on the initialization program instructions written to the address segment, to complete the power-on initialization of the chip; the initialization program execution adopts a pipelined architecture, and after detecting the trigger signal, it performs serial instruction parsing processing from the start address, and stops instruction parsing processing when the end address is identified.

[0061] Furthermore, the aforementioned initialization program instructions include multiple subroutine instructions; the fields corresponding to each subroutine instruction include three parts: instruction synchronization header, instruction number, and instruction mode.

[0062] Furthermore, the above-mentioned device also includes: a configuration module, used to, in response to the user's initialization program configuration operation according to the actual application scenario, store the user-edited initialization program in the one-time programmable memory or read-only memory before the step of automatically reading back the pre-stored initialization program instructions to the user-specified address segment in the register via the one-time programmable memory or read-only memory.

[0063] Furthermore, the aforementioned initialization module 54 is used to perform serial instruction parsing processing starting from the start address, sequentially identifying and parsing multiple subroutine instructions included in the initialization program instructions, until the end address is identified and instruction parsing processing stops.

[0064] Furthermore, the configuration module described above is also used to respond to user configuration operations on the start and end addresses of the target program segment in the registers, as well as manual triggering operations, after the power-on initialization of the chip is completed, to execute the target program segment in order to complete the function corresponding to the target program segment.

[0065] Furthermore, the bit width of the data stored at each of the above addresses is determined according to the specific data bus width used, including 8 bits, 16 bits, or 32 bits.

[0066] Furthermore, the above instruction mode includes at least one of the following: sequential serial write operation instructions, sequential serial read operation instructions, counting and waiting instructions to complete the corresponding clock cycle according to the configuration, waiting instructions by querying at fixed cycles and comparing with the target value to see if they are consistent, sequential periodic loop operation instructions, entering general arithmetic operation instructions, entering immediate value arithmetic operation instructions, entering unconditional address jump operation instructions, and entering conditional address jump operation instructions.

[0067] Furthermore, the instruction content for the sequential serial write operation instructions mentioned above includes: base address, offset address, and write data, wherein the offset address and write data appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, and storage index, wherein the offset address and storage index appear in pairs, indicating that the logic writes the corresponding configuration to the corresponding address based on the data read from the storage index; or, the instruction content for the sequential serial write operation instructions includes: base address, offset address, readback data storage index, and number of write addresses; these four pieces of information appear only once in the instruction, indicating that the logic completes the writing of the corresponding configuration to the corresponding address based on the data read from the readback data storage index and the number of write addresses.

[0068] The device provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts of the device embodiment not mentioned can be referred to the corresponding content in the aforementioned method embodiment.

[0069] Based on the above method embodiments, this application also provides a chip for executing the chip power-on initialization method as described in the foregoing method embodiments.

[0070] The chip provided in this application embodiment has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the chip embodiment section can be referred to the corresponding content in the aforementioned method embodiment.

[0071] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method of on-chip power initialization, the method comprising: The method is applied to a chip; the method comprises: After the chip is powered on and after POR reset is completed, pre-stored initialization program instructions are automatically read back to a user-specified address segment in a register through one-time programmable memory or read-only memory; the initialization program instructions are set by a user according to an actual application scenario; Based on the initialization program instructions in the address segment, initialization program execution is automatically triggered to complete power-on initialization of the chip; the initialization program execution is used to adopt a pipeline architecture to perform serial instruction parsing processing from a start address after a trigger signal is detected, and instruction parsing processing is stopped when an end address is identified. The initialization program instructions include a plurality of sub-program instructions; a field corresponding to each sub-program instruction includes three parts: an instruction synchronization header, an instruction number, and an instruction mode.

2. The method of claim 1, wherein, Before the step of automatically reading back the pre-stored initialization program instructions to the user-specified address segment in the register through the one-time programmable memory or the read-only memory, the method further comprises: In response to initialization program configuration operations performed by a user according to an actual application scenario, the initialization program edited by the user is stored in the one-time programmable memory or the read-only memory.

3. The method of claim 1, wherein, Based on the initialization program instructions in the address segment, initialization program execution is automatically triggered to complete power-on initialization of the chip; the initialization program execution is used to adopt a pipeline architecture to perform serial instruction parsing processing from a start address after a trigger signal is detected, and instruction parsing processing is stopped when an end address is identified. After the step of completing power-on initialization of the chip, the method further comprises:

4. The method of claim 1, wherein, In response to configuration operations of a start address and a termination address of a target program segment performed by a user on a register, and a manual trigger operation, the target program segment is executed to complete a function corresponding to the target program segment. The bit width of data stored on each address is determined according to the specific data bus width, including 8 bits, 16 bits, or 32 bits.

5. The method of claim 1, wherein, The instruction mode at least includes one of the following: serial write operation instructions, serial read operation instructions, count waiting instructions according to configuration of a corresponding clock period, waiting instructions by querying at a fixed period and comparing whether the target value is consistent, periodic cycle operation instructions, immediate number operation instructions, unconditional address jump operation instructions, and conditional address jump operation instructions.

6. The method of claim 1, wherein, The instruction content of the serial write operation instructions includes a base address, an offset address, and write data, wherein the offset address and the write data appear in pairs to indicate that the logic writes corresponding configurations to the corresponding address; or 7. The method of claim 6, wherein, The instruction content of the serial write operation instructions includes a base address, an offset address, and a storage index, wherein the offset address and the storage index appear in pairs to indicate that the logic writes corresponding configurations to the corresponding address according to data read out from the storage index; or The instruction content of the serial write operation instructions includes a base address, an offset address, and a storage index, wherein the offset address and the storage index appear in pairs to indicate that the logic writes corresponding configurations to the corresponding address according to data read out from the storage index; or The instruction content of the instruction of sequentially performing the serial write operation comprises a base address, an offset address, a read-back data storage index and a write address number; the four information only appears once in the instruction, and the logic completes corresponding configuration on the corresponding address according to the data read out from the read-back data storage index and the write address number.

8. An on-chip power-on initialization device, comprising: The device is applied to a chip; the device is used to execute the method in any one of claims 1-7, and the device comprises: a program read-back module, configured to automatically read back the pre-stored initialization program instruction to the user-specified address segment in the register through the one-time programmable memory or the read-only memory after the chip is powered on and waits for the POR reset to end; the initialization program instruction is set by the user according to the actual application scenario; an initialization module, configured to automatically trigger the initialization program execution based on the initialization program instruction written in the address segment, and complete the power-on initialization of the chip; the initialization program execution is configured to adopt a pipeline architecture, start serial instruction parsing processing from the start address after detecting a trigger signal, and stop the instruction parsing processing when the end address is recognized.

9. A chip, characterized by The chip is used to execute the power-on initialization method of the chip in any one of claims 1-7.

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