Current detection circuit, chip and electronic equipment
By introducing a compensation current module and a compensation resistor unit into the current detection circuit, the power dissipation problem caused by the input offset voltage is solved, ensuring the accuracy and consistency of current detection.
Patent Information
- Application Number
- CN202510677017.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-23
- Publication Date
- 2025-07-22
AI Technical Summary
In the current detection circuit, the power dissipation discrete problem caused by the input offset voltage affects the consistency and reliability of the circuit performance.
By introducing a compensation current module and a compensation resistor unit, a compensation voltage is formed to offset the input offset voltage of the clamp op amp, avoiding additional power consumption.
It realizes no additional power consumption under no load situation, and reduces the power dispersion between different current detection circuits, improving the accuracy and consistency of current detection.
Smart Images
Figure CN120352683A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and particularly to a current detection circuit, a chip, and an electronic device. Background Art
[0002] In modern electronic devices, chips are widely used. For many chips that need to precisely control the current of load devices, the current detection circuit plays a crucial role. For example, in a power management chip, in order to ensure the stable operation of the system and effectively protect load devices (such as power units like power transistors), it is necessary to accurately detect the current in real time, so as to achieve key functions such as overcurrent protection or current limiting. However, when the current detection circuit is in an idle state, the input offset voltage of the operational amplifier, hereinafter simply referred to as the offset voltage (VOS), will cause additional power consumption. Due to the inherent differences in chip manufacturing processes, the offset voltage (VOS) shows discreteness among different chips. This discreteness makes the power consumption of different circuits under no-load vary, resulting in a decrease in the performance consistency and reliability of the circuits. Summary of the Invention
[0003] The purpose of this application is to provide a current detection circuit, a chip, and an electronic device to avoid the power consumption discreteness problem caused by the input offset voltage.
[0004] In a first aspect, this application provides a current detection circuit, including: a power unit, a detection unit, a clamping operational amplifier, a compensation resistor unit, and a compensation current module; the power unit is connected to the detection unit; the first input terminal of the clamping operational amplifier is connected to the power unit, the second input terminal of the clamping operational amplifier is connected to the first end of the compensation resistor unit, and the second end of the compensation resistor unit is connected to the detection unit; the compensation current module is connected to the first end of the compensation resistor unit, and the compensation current module is used to provide a compensation current, and the compensation current forms a compensation voltage on the compensation resistor, wherein the compensation voltage is used to cancel the input offset voltage.
[0005] That is, in the embodiments of this application, the compensation current module and the compensation resistor unit can provide a compensation voltage for the current detection circuit, so as to cancel the input offset voltage between the first input terminal and the second input terminal of the clamping operational amplifier, to avoid generating additional power consumption, and further avoid the power consumption discreteness problem caused by the input offset voltage.
[0006] In a possible implementation of the first aspect, the power unit includes a first MOS transistor, the detection unit includes a second MOS transistor, the compensation resistor unit includes a compensation resistor, and the current detection circuit further includes a third MOS transistor; the input terminal of the third MOS transistor is connected to the control terminal of the detection unit and the second end of the compensation resistor, and the control terminal of the third MOS transistor is connected to the output terminal of the clamping operational amplifier.
[0007] In a possible implementation of the first aspect, the compensation current module includes a first mirror branch and a compensation current source. The compensation current source is connected to the first end of the first mirror branch, and the second end of the first mirror branch is connected to the first end of the compensation resistor.
[0008] In a possible implementation of the first aspect, the first mirror branch includes: a fourth MOS transistor, the input terminal of the fourth MOS transistor is connected to the compensation current source and the control terminal of the fourth MOS transistor; a fifth MOS transistor, the input terminal of the fifth MOS transistor is connected to the first end of the compensation resistor, and the control terminal of the fifth MOS transistor is connected to the control terminal of the fourth MOS transistor; a sixth MOS transistor, the input terminal of the sixth MOS transistor is connected to the output terminal of the fourth MOS transistor and the control terminal of the sixth MOS transistor, and the output terminal of the sixth MOS transistor is grounded; a seventh MOS transistor, the input terminal of the seventh MOS transistor is connected to the output terminal of the fifth MOS transistor, the control terminal of the seventh MOS transistor is connected to the control terminal of the sixth MOS transistor, and the output terminal of the seventh MOS transistor is grounded.
[0009] In a possible implementation of the first aspect, the current detection circuit further includes: a second mirror branch, the input terminal of the second mirror branch is connected to the output terminal of the third MOS transistor, and the output terminal of the second mirror branch is connected to the output terminal of the fifth MOS transistor.
[0010] In a possible implementation of the first aspect, the second mirror branch includes: a ninth MOS transistor, the input terminal of the ninth MOS transistor is connected to the output terminal of the third MOS transistor and the control terminal of the ninth MOS transistor, and the output terminal of the ninth MOS transistor is grounded; a tenth MOS transistor, the control terminal of the tenth MOS transistor is connected to the control terminal of the ninth MOS transistor, and the output terminal of the tenth MOS transistor is grounded; an eleventh MOS transistor, the output terminal of the eleventh MOS transistor is connected to the control terminal of the eleventh MOS transistor and the input terminal of the tenth MOS transistor; a twelfth MOS transistor, the input terminal of the twelfth MOS transistor is connected to the input terminal of the eleventh MOS transistor, the control terminal of the twelfth MOS transistor is connected to the control terminal of the eleventh MOS transistor, and the output terminal of the twelfth MOS transistor is connected to the output terminal of the fifth MOS transistor.
[0011] In a possible implementation of the first aspect, the compensation current module includes a compensation current source and an eighth MOS transistor; the compensation current source is connected to the output terminal of the eighth MOS transistor, and the input terminal of the eighth MOS transistor is connected to the first end of the compensation resistor unit.
[0012] In a possible implementation of the first aspect, the current detection circuit further includes a reference current module; the reference current module includes a second mirror branch, a reference current source, and a current comparator. The input end of the second mirror branch is connected to the output end of the third MOS transistor, the output end of the second mirror branch is connected to the reference current source, the input end of the current comparator is connected to the output end of the second mirror branch and the reference current source, and the output end of the current comparator is connected to the control end of the eighth MOS transistor.
[0013] In a possible implementation of the first aspect, the second mirror branch includes: a ninth MOS transistor, the input end of the ninth MOS transistor is connected to the output end of the third MOS transistor and the control end of the ninth MOS transistor, and the output end of the ninth MOS transistor is grounded; a tenth MOS transistor, the control end of the tenth MOS transistor is connected to the control end of the ninth MOS transistor, and the output end of the tenth MOS transistor is grounded; an eleventh MOS transistor, the output end of the eleventh MOS transistor is connected to the control end of the eleventh MOS transistor and the input end of the tenth MOS transistor; a twelfth MOS transistor, the input end of the twelfth MOS transistor is connected to the input end of the eleventh MOS transistor, the control end of the twelfth MOS transistor is connected to the control end of the eleventh MOS transistor, and the output end of the twelfth MOS transistor is connected to the reference current source and the control end of the eighth MOS transistor.
[0014] In a possible implementation of the first aspect, the second mirror branch further includes a thirteenth MOS transistor, the input end of the thirteenth MOS transistor is connected to the input end of the twelfth MOS transistor and the input end of the eleventh MOS transistor, and the control end of the thirteenth MOS transistor is connected to the control end of the twelfth MOS transistor and the control end of the eleventh MOS transistor.
[0015] In a possible implementation of the first aspect, the current scaling ratio of the first mirror branch is 1.
[0016] In a possible implementation of the first aspect, the current scaling ratio of the second mirror branch is 1 / k, where k > 1.
[0017] In a second aspect, the present application provides a chip, including the current detection circuit provided in the first aspect above.
[0018] In a third aspect, the present application provides an electronic device, including the chip provided in the second aspect above. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0020] Figure 1A The first schematic diagram of the current detection circuit is shown according to an embodiment of the present application;
[0021] Figure 1B The second schematic diagram of the current detection circuit is shown according to an embodiment of the present application;
[0022] Figure 2 The third schematic diagram of the current detection circuit is shown according to an embodiment of the present application;
[0023] Figure 3 The fourth schematic diagram of the current detection circuit is shown according to an embodiment of the present application;
[0024] Figure 4 The fifth schematic diagram of the current detection circuit is shown according to an embodiment of the present application. Detailed implementation manners
[0025] Exemplary embodiments of the present application include, but are not limited to, a current detection circuit, a chip, and an electronic device.
[0026] As mentioned above, in the field of electronic technology, the current detection circuit needs to detect current in real time and accurately.
[0027] However, in some embodiments, the clamping operational amplifier in the current detection circuit will generate an offset voltage (VOS), thereby resulting in an additional offset current.
[0028] It can be understood that the input terminal, output terminal, and control terminal mentioned in the embodiments of the present application can describe the interaction between a unit, module, or device and an external circuit. Among them, the input terminal represents the end of the circuit that receives an external signal or power supply, the output terminal represents the end of the circuit that transmits a signal or electrical energy to the outside, and the control terminal represents the end that controls the control state of the control module or device. In the case where the device is a MOSFET, the control terminal can refer to the gate (Gate, G). And when the input terminal refers to the source (Source, S), the output terminal can refer to the drain (Drain, D); when the input terminal refers to the drain, the output terminal can refer to the source.
[0029] Reference Figure 1A , according to some embodiments, the current detection circuit may include a first field-effect transistor (MOS transistor) M1, a second MOS transistor M2, a clamping operational amplifier A1, a third MOS transistor M3, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12. Among them, the first field-effect transistor M1 can be, for example, a power transistor, and the second MOS transistor M2 can be, for example, a detection transistor, which is used to detect the output current of the power transistor.
[0030] According to some embodiments, the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors. Its input terminal can be the source electrode, the control terminal can be the gate electrode, and the output terminal can be the drain electrode. The third MOS transistor M3 is an N-type MOS transistor. Its input terminal can be the drain electrode, the control terminal can be the gate electrode, and the output terminal can be the source electrode.
[0031] As Figure 1A shown, the control terminals of the first MOS transistor M1 and the second MOS transistor M2 are connected, the input terminals of the first MOS transistor M1 and the second MOS transistor M2 are connected, and the first MOS transistor M1 and the second MOS transistor M2 have the same input voltage PAD_VIN. The output terminals of the first MOS transistor M1 and the second MOS transistor M2 are clamped by a clamping operational amplifier A1. The input terminal of the third MOS transistor M3 is connected to the output terminal of the second MOS transistor M2, and the control terminal of the third MOS transistor M3 is connected to the output terminal of the clamping operational amplifier A1. Thus, through the clamping action of the clamping operational amplifier A1, the output voltage V OUT of the first MOS transistor M1 and the output voltage V OUT_SENSE of the second MOS transistor M2 are equal in the ideal state, making the detection current output by the second MOS transistor M2 proportional to the load current output by the first MOS transistor M1. Thus, the detection current output by the second MOS transistor M2 can reflect the magnitude of the load current, enabling the second MOS transistor M2 to be used for detecting the output current of the first MOS transistor M1.
[0032] According to some embodiments, the ninth MOS transistor M9 and the tenth MOS transistor M10 are P-type MOS transistors. Its input terminal can be the source electrode, the control terminal can be the gate electrode, and the output terminal can be the drain electrode; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are N-type MOS transistors. Its input terminal can be the drain electrode, the control terminal can be the gate electrode, and the output terminal can be the source electrode.
[0033] In some embodiments, the current detection circuit may include a mirror branch, and the mirror branch can scale the detection current. According to Figure 1AAs shown, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, and the twelfth MOS transistor M12 together form a mirror branch. Among them, the output terminal of the third MOS transistor M3 is connected to the input terminal of the ninth MOS transistor M9. The output terminal of the ninth MOS transistor M9 is grounded, and the input terminal and the control terminal of the ninth MOS transistor M9 are connected, that is, the ninth MOS transistor M9 is in a conducting state by default; the control terminal of the tenth MOS transistor M10 is connected to the control terminal of the ninth MOS transistor M9, and the output terminal of the tenth MOS transistor M10 is grounded; the output terminal of the eleventh MOS transistor M11 is connected to the input terminal of the tenth MOS transistor M10, and the output terminal and the control terminal of the eleventh MOS transistor M11 are connected, that is, the eleventh MOS transistor M11 is in a conducting state by default; the input terminal of the twelfth MOS transistor M12 is connected to the input terminal of the eleventh MOS transistor M11, and the input voltages of the twelfth MOS transistor M12 and the eleventh MOS transistor M11 are both the analog power supply voltage AVDD, and the control terminal of the twelfth MOS transistor M12 is connected to the control terminal of the eleventh MOS transistor M11.
[0034] It can be understood that the ninth MOS transistor M9 and the tenth MOS transistor M10 form a current mirror, and the eleventh MOS transistor M11 and the twelfth MOS transistor M12 form a current mirror. Exemplarily, the current scaling ratio of the current mirror formed by the ninth MOS transistor M9 and the tenth MOS transistor M10 is m:1; the current scaling ratio of the current mirror formed by the eleventh MOS transistor M11 and the twelfth MOS transistor M12 is n:1, so that the current output by the twelfth MOS transistor M12 is 1 / mn times the current output by the third MOS transistor M3, that is, a scaled detection current can be output. It should be noted that the present application does not limit the scaling ratio of each mirror branch.
[0035] As described above, in Figure 1A the current detection circuit shown, the second MOS transistor M2 can be used to detect the output current of the first MOS transistor M1. In an ideal state, the load current output by the first MOS transistor M1 and the ideal detection current output by the second MOS transistor M2 can be in a proportional relationship, for example, the ratio is K:1. Among them, the ideal detection current output by the second MOS transistor M2 can be expressed by the following formula:
[0036]
[0037] where, I SENSE represents the ideal detection current output by the second MOS transistor M2, I OUT represents the load current output by the first MOS transistor M1, R SENSE represents the impedance of the second MOS transistor M2, and R MPASS represents the impedance of the first MOS transistor M1.
[0038] According to formula (1), when the first MOS transistor M1 is unloaded, the load current I output by the first MOS transistor M1 OUT is 0. Therefore, the ideal detection current I SENSE is 0.
[0039] Reference Figure 1B , in practical applications, due to the existence of VOS in the clamping operational amplifier A1. For example, there is VOS between the negative input terminal and the positive input terminal of the clamping operational amplifier A1, which will cause an additional offset current to be generated. Considering the existence of VOS in the clamping operational amplifier A1, the output terminal voltage of the second MOS transistor M2 is lower than the output terminal voltage of the first MOS transistor M1, resulting in an offset current in the output path of the second MOS transistor M2. At this time, the actual detection current output by the second MOS transistor M2 can be expressed by the following formula:
[0040]
[0041] Among them, I SENSE represents the ideal detection current output by the second MOS transistor M2, ΔI represents the offset current, I OUT represents the load current output by the first MOS transistor M1, R SENSE represents the impedance of the second MOS transistor M2, R MPASS represents the impedance of the first MOS transistor M1, and VOS represents the offset voltage.
[0042] According to formula (2), due to the existence of VOS, an offset current ΔI exists, resulting in an error between the actual detection current I SENSE +ΔI and the ideal detection current I SENSE , causing the current detection result to be inaccurate.
[0043] To solve the above problems, the present application provides a current detection circuit. Compared with the current detection circuits shown in Figure 1A and Figure 1B , a compensation resistor and a compensation current can be introduced, so as to generate a compensation voltage that cancels out the VOS, and the problem of power consumption dispersion caused by VOS can be avoided.
[0044] Next, based on Figure 2 introduce a current detection circuit provided by an embodiment of the present application.
[0045] As shown in Figure 2 , the current detection circuit includes a power unit 1, a detection unit 2, a clamping operational amplifier 3, a compensation resistor unit 4, and a compensation current module 5.
[0046] Reference Figure 2, the input end of the power unit 1 is connected to the input end of the detection unit 2, the output end of the power unit 1 is connected to the positive-phase input end of the clamping operational amplifier 3, the output end of the detection unit 2 is connected to the second end of the compensation resistor unit 4, the first end of the compensation resistor unit 4 is connected to the negative-phase output end of the clamping operational amplifier 3, and the compensation current module 5 is connected to the first end of the compensation resistor unit 4.
[0047] It can be understood that there is a VOS between the first input end and the second input end of the clamping operational amplifier 3. The compensation current module 5 is used to form a compensation current I1. The compensation current I1 forms a compensation voltage on the compensation resistor unit 4, and the compensation voltage is used to cancel out the VOS.
[0048] It can be understood that the power unit 1 may include one or more load devices, and the detection unit 2 may include one or more detection devices, which are not limited in this application. The compensation resistor unit 4 may include at least one resistor connected in series or in parallel, and the impedance of its resistor and the connection form are not limited in the embodiments of this application.
[0049] In Figure 1A - Figure 1B the shown scheme, due to the existence of VOS, there is an offset current ΔI, resulting in the actual detection current I SENSE +ΔI and the ideal detection current I SENSE having an error, leading to inaccurate current detection results.
[0050] While in Figure 2 the shown current detection circuit, a compensation resistor unit 4 is connected in series to the negative-phase input end of the clamping operational amplifier 3. The impedance of the compensation resistor unit 4 can be expressed as R, and the compensation current I1 formed by the compensation current module 5 generates a compensation voltage I1R on the compensation resistor unit 4. The value of the compensation voltage I1R can be the same as VOS, so as to cancel out VOS, and raise the voltage V OUT_SENSE at the output end of the detection unit 2 and the second end of the compensation resistor unit 4, making V OUT_SENSE the same as the voltage V OUT at the positive-phase input end of the clamping operational amplifier 3 and the output end of the power unit 1, so that the actual detection current and the ideal detection current I SENSE are consistent, to solve the problem of inaccurate detection current.
[0051] Moreover, in Figure 1A - Figure 1B the shown scheme, in the no-load case, the ideal detection current I SENSE is 0, but due to the existence of ΔI, the actual detection current I SENSE +ΔI is not 0, so that each device in the current detection circuit generates additional power consumption under the action of the actual detection current.
[0052] While in Figure 2In the current detection circuit shown, when the power unit 1 is in an idle state, the detected current is consistent with the ideal detected current I SENSE and the magnitude of the current is 0. As a result, the current flowing through each device in the current detection circuit is 0, so the current detection circuit does not generate additional power consumption.
[0053] Furthermore, in Figure 1A - Figure 1B the scheme shown, when there are multiple different current detection circuits in the same electronic device or different electronic devices, due to the different VOS of the clamping operational amplifiers in different current detection circuits, the offset current ΔI will be different, which will further lead to the power consumption dispersion of different current detection circuits and affect the parameter consistency between current detection circuits.
[0054] However, based on Figure 2 a current detection circuit shown, different compensation current modules 5 can be configured for different VOS, for example, configured to form different compensation currents I1, and / or different compensation resistance units 4 can be configured, for example, configured to have different impedances, to cancel different VOS in different current detection circuits, thereby avoiding the problem of power consumption dispersion between multiple current detection circuits.
[0055] Next, based on Figure 3 a current detection circuit provided by an embodiment of the present application will be introduced.
[0056] In some embodiments, the power unit 1 includes a first MOS transistor M1, the detection unit 2 includes a second MOS transistor M2, the clamping operational amplifier 3 includes a clamping operational amplifier A1, the compensation resistance unit 4 includes a compensation resistance R, and the compensation current module 5 includes a connected compensation current source I REF and a first mirror branch.
[0057] As Figure 3 shown, the current detection circuit includes a power unit 1, a detection unit 2, a clamping operational amplifier A1, a compensation resistance R, a third MOS transistor M3, a compensation current source I REF a first mirror branch and a second mirror branch.
[0058] According to some embodiments, the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors, whose input terminals can be source electrodes, the control terminals can be gate electrodes, and the output terminals can be drain electrodes. The third MOS transistor M3 is an N-type MOS transistor, whose input terminal can be a drain electrode, the control terminal can be a gate electrode, and the output terminal can be a source electrode.
[0059] The input terminal of the first MOS transistor M1 is connected to the input terminal of the second MOS transistor M2, and the first MOS transistor M1 and the second MOS transistor M2 have the same input voltage PAD_VIN. The output terminal of the first MOS transistor M1 is connected to the positive-phase input terminal of the clamping operational amplifier A1. The output terminal of the second MOS transistor M2 is connected to the second terminal of the compensation resistor R. The first terminal of the compensation resistor R is connected to the negative-phase output terminal of the clamping operational amplifier A1. The input terminal of the third MOS transistor M3 is connected to the control terminal of the detection unit and the second terminal of the compensation resistor R. The control terminal of the third MOS transistor M3 is connected to the output terminal of the clamping operational amplifier A1.
[0060] The compensation current module 5 includes a connected compensation current source I REF and a first mirror branch, where the first mirror branch is connected to the first terminal of the compensation resistor R.
[0061] Exemplarily, the current amplification ratio of the first mirror branch can be 1:1, so that the current provided by the compensation current source I REF is the same as the compensation current I1. It should be noted that the amplification ratio of the first mirror branch is not limited in this application.
[0062] The first mirror branch includes a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, and a seventh MOS transistor M7.
[0063] According to some embodiments, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 are P-type MOS transistors. Their input terminals can be source electrodes, their control terminals can be gate electrodes, and their output terminals can be drain electrodes.
[0064] As Figure 3 shown, the input terminal of the fourth MOS transistor M4 is connected to the compensation current source and the control terminal of the fourth MOS transistor M4. It can be understood that since the fourth MOS transistor M4 is a P-type MOS transistor and its source electrode and gate electrode are connected, the fourth MOS transistor M4 is in a conducting state by default.
[0065] The input terminal of the fifth MOS transistor M5 is connected to the first terminal of the compensation resistor R. The control terminal of the fifth MOS transistor M5 is connected to the control terminal of the fourth MOS transistor M4.
[0066] The input terminal of the sixth MOS transistor M6 is connected to the output terminal of the fourth MOS transistor M4 and the control terminal of the sixth MOS transistor M6. The output terminal of the sixth MOS transistor M6 is grounded. It can be understood that since the sixth MOS transistor M6 is a P-type MOS transistor and its source electrode and gate electrode are connected, the sixth MOS transistor M6 is in a conducting state by default.
[0067] The input terminal of the seventh MOS transistor M7 is connected to the output terminal of the fifth MOS transistor M5, the control terminal of the seventh MOS transistor M7 is connected to the control terminal of the sixth MOS transistor M6, and the output terminal of the seventh MOS transistor M7 is grounded.
[0068] It can be understood that in the first mirror branch, the fourth MOS transistor M4 and the fifth MOS transistor M5 form a current mirror, and the sixth MOS transistor M6 and the seventh MOS transistor M7 form a current mirror. Exemplarily, the current amplification ratio of each current mirror is 1:1.
[0069] The input terminal of the second mirror branch is connected to the output terminal of the third MOS transistor M3, and the output terminal of the second mirror branch is connected to the output terminal of the fifth MOS transistor M5. It can be understood that the second mirror branch can scale the input terminal detection current I SENSE and output the current I sense from the output terminal. When the first MOS transistor M1 is not in the no-load state, the I sense output by the second mirror branch is large enough, and I sense is greater than I1, which will turn off the fifth MOS transistor M5 in the first mirror branch, so that the compensation current module 5 no longer provides compensation current, and further the compensation resistor R will not affect the current detection when the first MOS transistor M1 is in the non-no-load state.
[0070] The second mirror branch includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12. It can be understood that the input terminal of the ninth MOS transistor M9 is the input terminal of the second mirror branch, and the control terminal of the twelfth MOS transistor M12 is the output terminal of the second mirror branch.
[0071] According to some embodiments, the ninth MOS transistor M9 and the tenth MOS transistor M10 are P-type MOS transistors, whose input terminals can be source electrodes, control terminals can be gate electrodes, and output terminals can be drain electrodes; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are N-type MOS transistors, whose input terminals can be drain electrodes, control terminals can be gate electrodes, and output terminals can be source electrodes.
[0072] As Figure 3 shown, the input terminal of the ninth MOS transistor M9 (i.e., the input terminal of the second mirror branch) is connected to the output terminal of the third MOS transistor M3 and the control terminal of the ninth MOS transistor M9, and the output terminal of the ninth MOS transistor M9 is grounded. It can be understood that since the ninth MOS transistor M9 is a P-type MOS transistor and its source electrode and gate electrode are connected, the ninth MOS transistor M9 is default in the on state.
[0073] The control terminal of the tenth MOS transistor M10 is connected to the control terminal of the ninth MOS transistor M9, and the output terminal of the tenth MOS transistor M10 is grounded.
[0074] The output terminal of the eleventh MOS transistor M11, the control terminal of the eleventh MOS transistor M11, and the input terminal of the tenth MOS transistor are connected. It can be understood that since the eleventh MOS transistor M11 is an N-type MOS transistor and its source and gate are connected, the eleventh MOS transistor M11 is default in the conducting state.
[0075] The input terminal of the twelfth MOS transistor M12 is connected to the input terminal of the eleventh MOS transistor M11, and the input voltages of the twelfth MOS transistor M12 and the eleventh MOS transistor M11 are both the analog power supply voltage AVDD. The control terminal of the twelfth MOS transistor M12 is connected to the control terminal of the eleventh MOS transistor M11, and the output terminal of the twelfth MOS transistor M12 (i.e., the output terminal of the second mirror branch) is connected to the output terminal of the fifth MOS transistor M5.
[0076] It can be understood that in the second mirror branch, the ninth MOS transistor M9 and the tenth MOS transistor M10 form a current mirror, and the eleventh MOS transistor M11 and the twelfth MOS transistor M12 form a current mirror. Exemplarily, the current scaling ratio of the current mirror formed by the ninth MOS transistor M9 and the tenth MOS transistor M10 is m:1; the current scaling ratio of the current mirror formed by the eleventh MOS transistor M11 and the twelfth MOS transistor M12 is n:1. It should be noted that the present application does not limit the scaling ratio of each mirror branch.
[0077] According to some embodiments, the current detection circuit further includes a thirteenth MOS transistor M13 for outputting the detected current scaled by the second mirror branch. The scaling ratio of the second mirror branch can be, for example, 1 / k, that is, the ratio of the input current to the output current is k:1, k is m*n, and k>1. Among them, the thirteenth MOS transistor M13 can be a P-type MOS transistor, its control terminal can be connected to the control terminals of the eleventh MOS transistor M11 and the twelfth MOS transistor M12, and its input terminal can be connected to the input terminals of the eleventh MOS transistor M11 and the twelfth MOS transistor M12.
[0078] In Figure 1A - Figure 1B the shown scheme, due to the existence of VOS, there is an offset current ΔI, resulting in an error between the actual detected current I SENSE +ΔI and the ideal detected current I SENSE And in Figure 3 the shown current detection circuit, by connecting a compensation resistor R in series at the negative input terminal of the clamping operational amplifier A1, and generating a compensation voltage I1R on the compensation resistor R through the compensation current I1 formed by the compensation current module 5, where the compensation voltage I1R can cancel VOS, thereby raising the voltage V OUT_SENSE at the output terminal of the detection unit 2 and the second terminal of the compensation resistor R, so that V OUT_SENSEis the same as the voltage V at the positive input terminal of the clamping operational amplifier A1 and the output terminal of the power unit 1, OUT so that the actual detected current and the ideal detected current I SENSE are consistent.
[0079] Moreover, in Figure 1A - Figure 1B the scheme shown, when no load is present, the ideal detected current I SENSE is 0, but due to the existence of VOS and ΔI, the actual detected current I SENSE +ΔI is not 0, resulting in additional power consumption in each device in the current detection circuit under the action of the actual detected current. In Figure 2 the current detection circuit shown, when the power unit 1 is no load, the detected current and the ideal detected current I SENSE are consistent and 0, so that the current flowing through each device in the current detection circuit is 0, and thus the current detection circuit will not generate additional power consumption. When the power unit 1 is not no load, through the feedback mechanism of the second mirror branch to the first mirror branch, the first mirror branch can be turned off, that is, the I sense output by the second mirror branch is large enough to turn off the fifth MOS transistor M5 in the first mirror branch, so that the compensation current module 5 no longer forms the compensation current I1 flowing through the compensation resistor R, and further the compensation resistor R will not affect the current detection when the first MOS transistor M1 is in the non-no-load state.
[0080] Furthermore, in Figure 1A - Figure 1B the scheme shown, when there are multiple different current detection circuits in the same electronic device or different electronic devices, or when the same batch of chips all include current detection circuits, due to the different VOS of the clamping operational amplifiers in different current detection circuits, the offset current ΔI will be different, and further there will be a large power consumption dispersion among different current detection circuits, which will affect the parameter consistency between current detection circuits. Based on Figure 3 a current detection circuit shown, different compensation current sources I REF can be configured for different VOS, for example, configured to form different compensation currents I1, and / or different compensation resistors R can be configured, for example, configured to have different impedances, to cancel different VOS in different current detection circuits, thus avoiding the problem of power consumption dispersion among multiple current detection circuits.
[0081] Next, based on Figure 4 a current detection circuit provided by an embodiment of the present application will be introduced.
[0082] In some embodiments, in the current detection circuit, the power unit 1 includes a first MOS transistor M1, the detection unit 2 includes a second MOS transistor M2, the clamping operational amplifier 3 includes a clamping operational amplifier A1, the compensation resistor unit 4 includes a compensation resistor R, and the compensation current module 5 includes a connected compensation current source I REF1 and an eighth MOS transistor M8. And the current detection circuit may further include a reference current module 6, where the reference current module 6 includes a connected reference current source I REF2 and a second mirror branch.
[0083] As Figure 4 shown, the current detection circuit includes a power unit 1, a detection unit 2, a clamping operational amplifier A1, a compensation resistor R, a third MOS transistor M3, an eighth MOS transistor M8, a compensation current source I REF1 , a first mirror branch, a second mirror branch, and a reference current source I REF2 .
[0084] According to some embodiments, the first MOS transistor M1 and the second MOS transistor M2 are P-type MOS transistors, whose input terminals can be source electrodes, the control terminals can be gate electrodes, and the output terminals can be drain electrodes. The third MOS transistor M3 is an N-type MOS transistor, whose input terminal can be a drain electrode, the control terminal can be a gate electrode, and the output terminal can be a source electrode.
[0085] The input terminals of the first MOS transistor M1 and the second MOS transistor M2 are connected, and the first MOS transistor M1 and the second MOS transistor M2 have the same input voltage PAD_VIN. The output terminal of the first MOS transistor M1 is connected to the non-inverting input terminal of the clamping operational amplifier A1, the output terminal of the second MOS transistor M2 is connected to the second terminal of the compensation resistor R, the first terminal of the compensation resistor R is connected to the inverting output terminal of the clamping operational amplifier A1, the input terminal of the third MOS transistor M3 is connected to the control terminal of the detection unit and the second terminal of the compensation resistor R, and the control terminal of the third MOS transistor M3 is connected to the output terminal of the clamping operational amplifier A1.
[0086] The compensation current module 5 includes a connected compensation current source I REF1 and an eighth MOS transistor M8, where the compensation current source I REF1 is connected to the output terminal of the eighth MOS transistor M8, and the input terminal of the eighth MOS transistor M8 is connected to the first terminal of the compensation resistor R. It can be understood that the current output by the compensation current source I REF1 is the same as the compensation current I1.
[0087] The reference current module 6 includes a connected reference current source I REF2 and a second mirror branch, and a current comparator I comp . The input terminal of the second mirror branch is connected to the output terminal of the third MOS transistor M3, and the output terminal of the second mirror branch is connected to the reference current source IREF2 and the input terminal of current comparator I comp are connected. It can be understood that the second mirror branch can scale the detected current I SENSE at the input terminal and output current I sense from the output terminal. The input terminals of current comparator I comp are respectively connected to the output terminal of the second mirror branch and reference current source I REF2 . The output terminal of current comparator I comp is connected to the control terminal of the eighth MOS transistor M8. Current comparator I comp can output a high or low level at the output terminal by comparing the magnitudes of I sense and I REF2 . When the first MOS transistor M1 is not in the no-load state, the I sense output by the second mirror branch is large enough, and I sense is greater than the reference current provided by reference current source I REF2 . At this time, the output terminal of current comparator I comp outputs a low level (conversely, if I sense is less than I REF2 , the output terminal of current comparator I comp outputs a high level), so that the voltage at the control terminal of the eighth MOS transistor M8 is lower than the threshold voltage, turning off the eighth MOS transistor M8, so that the compensation current module 5 no longer provides compensation current, and further the compensation resistor R will not affect the current detection when the first MOS transistor M1 is in the non-no-load state.
[0088] The second mirror branch includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, and a twelfth MOS transistor M12. It can be understood that the input terminal of the ninth MOS transistor M9 is the input terminal of the second mirror branch, and the control terminal of the twelfth MOS transistor M12 is the output terminal of the second mirror branch.
[0089] According to some embodiments, the ninth MOS transistor M9 and the tenth MOS transistor M10 are P-type MOS transistors, whose input terminals can be the source electrodes, the control terminals can be the gate electrodes, and the output terminals can be the drain electrodes; the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are N-type MOS transistors, whose input terminals can be the drain electrodes, the control terminals can be the gate electrodes, and the output terminals can be the source electrodes.
[0090] As Figure 4 shown, the input terminal of the ninth MOS transistor M9 (i.e., the input terminal of the second mirror branch) is connected to the output terminal of the third MOS transistor M3 and the control terminal of the ninth MOS transistor M9, and the output terminal of the ninth MOS transistor M9 is grounded. It can be understood that since the ninth MOS transistor M9 is a P-type MOS transistor and its source electrode and gate electrode are connected, the ninth MOS transistor M9 is in the on state by default.
[0091] The control terminal of the tenth MOS transistor M10 is connected to the control terminal of the ninth MOS transistor M9, and the output terminal of the tenth MOS transistor M10 is grounded.
[0092] The output terminal of the eleventh MOS transistor M11 is connected to the control terminal of the eleventh MOS transistor M11 and the input terminal of the tenth MOS transistor. It can be understood that since the eleventh MOS transistor M11 is an N-type MOS transistor and its source and gate are connected, the eleventh MOS transistor M11 is in a conducting state by default.
[0093] The input terminal of the twelfth MOS transistor M12 is connected to the input terminal of the eleventh MOS transistor M11, the control terminal of the twelfth MOS transistor M12 is connected to the control terminal of the eleventh MOS transistor M11, and the input voltages of the twelfth MOS transistor M12 and the eleventh MOS transistor M11 are both the analog power supply voltage AVDD. The output terminal of the twelfth MOS transistor M12 (i.e., the output terminal of the second mirror branch) is connected to the reference current source I REF2 and the control terminal of the eighth MOS transistor M8.
[0094] It can be understood that in the second mirror branch, the ninth MOS transistor M9 and the tenth MOS transistor M10 form a current mirror, and the eleventh MOS transistor M11 and the twelfth MOS transistor M12 form a current mirror. Exemplarily, the current scaling ratio of the current mirror formed by the ninth MOS transistor M9 and the tenth MOS transistor M10 is m:1; the current scaling ratio of the current mirror formed by the eleventh MOS transistor M11 and the twelfth MOS transistor M12 is n:1. It should be noted that the present application does not limit the scaling ratio of each mirror branch.
[0095] According to some embodiments, the current detection circuit further includes a thirteenth MOS transistor M13 for outputting the detected current scaled by the second mirror branch. The scaling ratio of the second mirror branch can be, for example, 1 / k, that is, the ratio of the input current to the output current is k:1, k is m*n, and k>1. Among them, the thirteenth MOS transistor M13 can be a P-type MOS transistor, its control terminal can be connected to the control terminals of the eleventh MOS transistor M11 and the twelfth MOS transistor M12, and its input terminal can be connected to the input terminals of the eleventh MOS transistor M11 and the twelfth MOS transistor M12.
[0096] In Figure 1A - Figure 1B the shown scheme, due to the existence of VOS, there is an offset current ΔI, resulting in an error between the actual detected current I SENSE +ΔI and the ideal detected current I SENSE and causing the current detection result to be inaccurate.
[0097] While in Figure 4In the shown current detection circuit, a compensation resistor R is connected in series to the negative input terminal of the clamping operational amplifier A1, and a compensation current I1 formed by the compensation current module 5 generates a compensation voltage I1R across the compensation resistor R, where the magnitude of the compensation voltage I1R is the same as VOS, thereby canceling out VOS to raise the voltage V at the output terminal of the detection unit 2 and the second terminal of the compensation resistor R, making V OUT_SENSE the same as the voltage V OUT_SENSE at the positive input terminal of the clamping operational amplifier A1 and the output terminal of the power unit 1, so that the actual detected current is consistent with the ideal detected current I OUT SENSE SENSE .
[0098] Moreover, in the Figure 1A - Figure 1B shown solution, when no load is present, the ideal detected current I SENSE is 0, but due to the existence of VOS and ΔI, the actual detected current I SENSE +ΔI is not 0, so that each device in the current detection circuit generates additional power consumption under the action of the actual detected current. In the Figure 4 shown current detection circuit, when the power unit 1 is no load, the detected current is consistent with the ideal detected current I SENSE and is 0, so that the current flowing through each device in the current detection circuit is 0, and thus the circuit does not generate additional power consumption. When the power unit 1 is not no load, the feedback mechanism of the eighth MOS transistor M8 can be passed through the reference current module 6 to turn off the eighth MOS transistor M8, so that the compensation current module 5 no longer forms the compensation current I1, and further the compensation resistor R does not affect the current detection when the first MOS transistor M1 is in a non-no load state.
[0099] Furthermore, in the Figure 1A - Figure 1B shown solution, when there are multiple different current detection circuits in the same electronic device or different electronic devices, or when the same batch of chips all include current detection circuits, due to different VOS values of the clamping operational amplifiers in different current detection circuits, the offset current ΔI will be different, and further there will be a large power consumption dispersion among different current detection circuits, which will affect the parameter consistency between current detection circuits.
[0100] However, based on the Figure 4 shown current detection circuit, different compensation current sources I REF1 can be configured for different VOS, for example, configured to form different compensation currents I1, and / or different compensation resistors R can be configured, for example, configured to have different impedances, to cancel different VOS in different current detection circuits, thereby avoiding the problem of power consumption dispersion among multiple current detection circuits.
[0101] The present application also provides a chip, including the current detection circuit in any of the above embodiments.
[0102] The present application also provides an electronic device, including the above chip.
[0103] This specification provides methods or process operation steps as shown in the embodiments or flowcharts, but may include more or fewer operation steps based on routine or non-creative labor. The step sequences listed in the embodiments are just one way among numerous execution sequences and do not represent the only execution sequence. During actual execution, the methods or process sequences shown in the embodiments or the drawings can be executed sequentially or in parallel (such as in an environment of a parallel controller or multi-threaded processing).
[0104] The various embodiments disclosed in the present application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memories and / or storage elements), at least one input device, and at least one output device.
[0105] The program code can be applied to the input instructions to execute the various functions described in the present application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of the present application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.
[0106] The program code can be implemented in a high-level procedural language or an object-oriented programming language to communicate with the processing system. When necessary, the program code can also be implemented in assembly language or machine language. In fact, the mechanisms described in the present application are not limited to the scope of any specific programming language. In any case, the language can be a compiled language or an interpreted language.
[0107] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more transient or non-transitory machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or via other computer-readable media. Thus, machine-readable media may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to, floppy disks, optical disks, optical discs, compact disc read-only memories (CD-ROMs), magneto-optical discs, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) in electrical, optical, acoustic, or other forms using the Internet. Thus, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).
[0108] As used herein, the term "module" may refer to, as part of or including: a memory (shared, dedicated, or group) for running one or more software or firmware programs, an application specific integrated circuit (ASIC), an electronic circuit, and / or a processor (shared, dedicated, or group), combinational logic circuitry, and / or other suitable components providing the function.
[0109] In the drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or ordering is not required. Rather, in some embodiments, these features may be illustrated in a manner and / or order different from that shown in the illustrative drawings. Additionally, the structural or method features included in a particular drawing do not mean that all embodiments require such features. In some embodiments, these features may be omitted, or these features may be combined with other features.
[0110] The embodiments of the present application have been described in detail above in conjunction with the accompanying drawings. However, the use of the technical solutions of the present application is not limited to the various applications mentioned in the embodiments of this patent. Various structures and variations can be easily implemented with reference to the technical solutions of the present application to achieve the various beneficial effects mentioned herein. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes made without departing from the purpose of the present application shall fall within the scope covered by the patent of the present application.
Claims
1. A current detection circuit, characterized in that, Comprising: A power unit, a detection unit, a clamping operational amplifier, a compensation resistor unit, and a compensation current module; The power unit is connected to the detection unit; A first input terminal of the clamping operational amplifier is connected to the power unit, a second input terminal of the clamping operational amplifier is connected to a first end of the compensation resistor unit, and a second end of the compensation resistor unit is connected to the detection unit; The compensation current module is connected to the first end of the compensation resistor unit, the compensation current module is used to provide a compensation current, and the compensation current forms a compensation voltage across the compensation resistor.
2. The current detection circuit according to claim 1, wherein The power unit includes a first MOS transistor, the detection unit includes a second MOS transistor, the compensation resistor unit includes a compensation resistor, and the current detection circuit further includes a third MOS transistor; An input terminal of the third MOS transistor is connected to a control terminal of the detection unit and the second end of the compensation resistor, and a control terminal of the third MOS transistor is connected to an output terminal of the clamping operational amplifier.
3. The current detection circuit according to claim 2, characterized in that The compensation current module includes a first mirror branch and a compensation current source, the compensation current source is connected to a first end of the first mirror branch, and a second end of the first mirror branch is connected to the first end of the compensation resistor.
4. The current detection circuit according to claim 3, wherein The first mirror branch includes: A fourth MOS transistor, an input terminal of the fourth MOS transistor is connected to the compensation current source and a control terminal of the fourth MOS transistor; A fifth MOS transistor, an input terminal of the fifth MOS transistor is connected to the first end of the compensation resistor, and a control terminal of the fifth MOS transistor is connected to the control terminal of the fourth MOS transistor; A sixth MOS transistor, an input terminal of the sixth MOS transistor is connected to an output terminal of the fourth MOS transistor and a control terminal of the sixth MOS transistor, and an output terminal of the sixth MOS transistor is grounded; A seventh MOS transistor, an input terminal of the seventh MOS transistor is connected to an output terminal of the fifth MOS transistor, a control terminal of the seventh MOS transistor is connected to the control terminal of the sixth MOS transistor, and an output terminal of the seventh MOS transistor is grounded.
5. The current detection circuit according to claim 4, wherein Further comprising: A second mirror branch, an input terminal of the second mirror branch is connected to an output terminal of the third MOS transistor, and an output terminal of the second mirror branch is connected to an output terminal of the fifth MOS transistor.
6. The current detection circuit according to claim 5, characterized in that, The second mirror branch includes: A ninth MOS transistor, an input terminal of the ninth MOS transistor is connected to the output terminal of the third MOS transistor and a control terminal of the ninth MOS transistor, and an output terminal of the ninth MOS transistor is grounded; A tenth MOS transistor, a control terminal of the tenth MOS transistor is connected to the control terminal of the ninth MOS transistor, and an output terminal of the tenth MOS transistor is grounded; An eleventh MOS transistor, an output terminal of the eleventh MOS transistor is connected to a control terminal of the eleventh MOS transistor and an input terminal of the tenth MOS transistor; The twelfth MOS transistor, the input end of the twelfth MOS transistor is connected to the input end of the eleventh MOS transistor, the control end of the twelfth MOS transistor is connected to the control end of the eleventh MOS transistor, and the output end of the twelfth MOS transistor is connected to the output end of the fifth MOS transistor.
7. The current detection circuit according to claim 2, wherein The compensation current module includes a compensation current source and an eighth MOS transistor; The compensation current source is connected to the output end of the eighth MOS transistor, and the input end of the eighth MOS transistor is connected to the first end of the compensation resistor unit.
8. The current detection circuit according to claim 7, wherein It further includes a reference current module; The reference current module includes a second mirror branch, a reference current source and a current comparator, The input end of the second mirror branch is connected to the output end of the third MOS transistor, and the output end of the second mirror branch is connected to the reference current source, The input end of the current comparator is connected to the output end of the second mirror branch and the reference current source, and the output end of the current comparator is connected to the control end of the eighth MOS transistor.
9. The current detection circuit according to claim 8, wherein The second mirror branch includes: A ninth MOS transistor, the input end of the ninth MOS transistor is connected to the output end of the third MOS transistor and the control end of the ninth MOS transistor, and the output end of the ninth MOS transistor is grounded; A tenth MOS transistor, the control end of the tenth MOS transistor is connected to the control end of the ninth MOS transistor, and the output end of the tenth MOS transistor is grounded; An eleventh MOS transistor, the output end of the eleventh MOS transistor is connected to the control end of the eleventh MOS transistor and the input end of the tenth MOS transistor; A twelfth MOS transistor, the input end of the twelfth MOS transistor is connected to the input end of the eleventh MOS transistor, the control end of the twelfth MOS transistor is connected to the control end of the eleventh MOS transistor, and the output end of the twelfth MOS transistor is connected to the reference current source and the control end of the eighth MOS transistor.
10. The current detection circuit according to claim 6 or 9, characterized in that, The second mirror branch further includes a thirteenth MOS transistor, the input end of the thirteenth MOS transistor is connected to the input end of the twelfth MOS transistor and the input end of the eleventh MOS transistor, and the control end of the thirteenth MOS transistor is connected to the control end of the twelfth MOS transistor and the control end of the eleventh MOS transistor.
11. The current detection circuit according to any one of claims 3-6, characterized in that, The current scaling ratio of the first mirror branch is 1.
12. The current detection circuit according to any one of claims 5-6 and 8-9, characterized in that, The current scaling ratio of the second mirror branch is 1 / k, where k>1.
13. A chip, characterized in that, It includes the current detection circuit according to any one of claims 1-12.
14. An electronic device, characterized in that, It includes the chip according to claim 13.