Expansion equipment function configuration method and device, computer equipment and storage medium

Abstract

The invention discloses an extension equipment function configuration method and device, computer equipment and a storage medium, and relates to the technical field of data processing. According to the method, a hardware and firmware collaborative dynamic configuration framework is constructed, and a receiving queue is adopted at an extension equipment end to trigger a central processing unit firmware processing mechanism; in combination with virtualization design of a shadow configuration space and a shadow register, dynamic reconstruction of configuration parameters and an address mapping strategy during operation is realized; a host end supports configuration space access, base address register remapping and memory data transmission interaction through a transaction generation and routing mechanism driven by an event type. Hardware solidification limitation of traditional extension equipment is broken through through software and hardware decoupling design, the problems that function extension capacity is insufficient, resource dynamic allocation is difficult and protocol updating and virtualization scenes cannot be adapted are solved, and the technical effects of improving configuration reconstruction efficiency and address space utilization rate and supporting virtual function creation are achieved. And the adaptability of the equipment in cloud computing and edge computing environments is enhanced.

Description

Technical Field

[0001] The present application relates to the technical field of data processing, and in particular, to an extended device function configuration method, apparatus, computer device, and storage medium. Background Art

[0002] As the third-generation high-speed serial bus standard, the Peripheral Component Interconnect Express (PCIe) has become the core technology for high-performance device interconnection in modern computer systems. Its point-to-point serial communication architecture, multi-channel expansion ability, and full-duplex transmission characteristics have significantly improved data transmission bandwidth and efficiency, and are widely used in fields such as servers, storage devices, network interfaces, and acceleration cards. In the PCIe system architecture, terminal devices achieve system recognition and resource allocation through the configuration space, complete address space mapping relying on the base address register, and realize low-latency and high-throughput data interaction with the root complex device in combination with the DMA and efficient interrupt mechanisms (such as MSI / MSI-X). With the rapid development of heterogeneous computing, cloud computing, and edge computing scenarios, PCIe EP devices need to support diverse function customization, dynamic resource allocation, and flexible protocol adaptation capabilities, which pose higher requirements for the adaptability of the device underlying architecture.

[0003] Traditional PCIe EP devices adopt a fully hardware-cured design, resulting in significant deficiencies in flexibility and scalability. On the one hand, the configuration space and the base address register are fixed during the hardware design stage and cannot be dynamically adjusted according to the running requirements, such as function fields or address mapping strategies, making it difficult for the device to adapt to protocol updates, virtualized resource allocation, or customized scenario requirements after deployment. On the other hand, the hardware static implementation mode needs to reserve redundant resources for potential functions (such as an overly large base address register address space), resulting in low resource utilization; at the same time, any function modification or optimization requires a re-spin, leading to an extended development cycle and a sharp increase in costs. In addition, the increase in hardware complexity exacerbates the difficulty of debugging and maintenance, and does not support runtime dynamic expansion (such as resource reconfiguration in the scenario of virtual machine live migration). Summary of the Invention

[0004] The present application provides an extended device function configuration method, apparatus, computer device, and storage medium to at least solve the problems of insufficient function expansion ability, difficult dynamic resource allocation, and inability to adapt to protocol updates and virtualization scenarios caused by the hardware curing of extended devices in related technologies.

[0005] The present application provides an extended device function configuration method applied to an extended device, including:

[0006] Receive the first transaction layer packet sent by the host, write the first transaction layer packet into the receive queue in the memory, and trigger an interrupt to notify the central processor firmware;

[0007] Read the first transaction layer packet from the head of the receive queue through the central processor firmware, and access the shadow configuration space or shadow register according to the event type of the first transaction layer packet to perform corresponding read and write operations;

[0008] Generate a first response packet corresponding to the transaction layer packet according to the execution result of the read and write operation, write the first response packet into the send queue, and send it to the host by the hardware interface, where the first response packet is used to notify the host through an interrupt.

[0009] This application also provides an extended device interaction method, which is applied to the host and includes:

[0010] Obtain the current read and write requirements for the extended device;

[0011] Determine the event type according to the read and write requirements, and generate a first transaction layer packet corresponding to the event type, where the event type includes a configuration space access request, a base address register access request, and a memory access request;

[0012] Send the first transaction layer packet to the extended device, so that the extended device accesses the shadow configuration space or shadow register according to the event type of the first transaction layer packet, completes the register read and write operation or triggers the memory access data transmission.

[0013] This application also provides an extended device function configuration device, which is applied to the extended device and includes:

[0014] A receiving module, configured to receive the first transaction layer packet sent by the host, write the first transaction layer packet into the receive queue in the memory, and trigger an interrupt to notify the central processor firmware;

[0015] A reading module, configured to read the first transaction layer packet from the head of the receive queue through the central processor firmware, and access the shadow configuration space or shadow register according to the event type of the first transaction layer packet to perform corresponding read and write operations;

[0016] A first sending module, configured to generate a first response packet corresponding to the transaction layer packet according to the execution result of the read and write operation, write the first response packet into the send queue, and send it to the host by the hardware interface, where the first response packet is used to notify the host through an interrupt.

[0017] This application also provides an extended device interaction device, which is applied to the host and includes:

[0018] An obtaining module, configured to obtain the current read and write requirements for the extended device;

[0019] A generation module, configured to determine an event type according to read / write requirements and generate a first transaction layer data packet corresponding to the event type, where the event type includes a configuration space request, a base address register request, and a memory access request;

[0020] A second sending module, configured to send the first transaction layer data packet to an expansion device, so that the expansion device accesses a shadow configuration space or a shadow register according to the event type of the first transaction layer data packet, completes register read / write operations, or triggers memory access data transmission.

[0021] This application also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above methods when executing the computer program.

[0022] This application also provides a computer-readable storage medium, in which a computer program is stored, where the computer program implements the steps of any of the above methods when executed by a processor.

[0023] This application also provides a computer program product, including a computer program, where the computer program implements the steps of any of the above methods when executed by a processor.

[0024] Through this application, due to the adoption of a software-defined dynamic configuration mechanism, the conventionally hardware-fixed configuration space and register mapping are converted into a shadow configuration space and shadow registers that can be dynamically read and written, and flexible interaction between the host and the expansion device is achieved through transaction layer data packets. Therefore, the problems of insufficient function expansion ability, difficult dynamic resource allocation, and inability to adapt to protocol updates and virtualization scenarios of traditional expansion devices can be solved, and the following technical effects can be achieved: supporting runtime dynamic adjustment of configuration space fields and address mapping policies, improving system flexibility and resource utilization rate; realizing asynchronous processing of configuration parameters and memory access through transaction layer data packet interaction, supporting resource reconfiguration in complex scenarios such as virtual machine live migration; based on the hierarchical cache architecture of shadow registers, reducing the dependence on hardware design and shortening the function iteration cycle; through the collaborative work of the interrupt mechanism and transaction layer data packets, realizing low-latency configuration update and data transmission, meeting the real-time requirements in heterogeneous computing and edge computing scenarios; separating the hardware interface and software logic, providing a standardized interface for protocol extension, function customization, and adaptation to new computing architectures, and significantly enhancing the system scalability. Description of the Drawings

[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0026] Figure 1 A flowchart of an extended device function configuration method provided by an embodiment of this application;

[0027] Figure 2 A flowchart of the enumeration process of an extended device provided by an embodiment of this application;

[0028] Figure 3 A flowchart of an extended device interaction method provided by an embodiment of this application;

[0029] Figure 4 A flowchart of an extended device reading data from the host memory provided by an embodiment of this application;

[0030] Figure 5 An interaction architecture diagram of an extended device and a host provided by an embodiment of this application;

[0031] Figure 6 A structural block diagram of an extended device function configuration device provided by an embodiment of this application;

[0032] Figure 7 A structural block diagram of an extended device interaction device provided by an embodiment of this application;

[0033] Figure 8 A hardware structure diagram of a computer device provided by an embodiment of this application. Specific embodiments

[0034] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of this application.

[0035] It should be noted that in the description of this application, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0036] In order to enable those skilled in the art of this technology to better understand the solution of this application, the following further detailed description of this application will be given in conjunction with the accompanying drawings and specific embodiments.

[0037] An embodiment of this application provides an extended device function configuration method, which is applied to an extended device. Figure 1 It is a flowchart of the extended device function configuration method according to an embodiment of the present invention, as Figure 1 shown, and this process includes the following steps:

[0038] Step S11, receive the first transaction layer packet sent by the host, write the first transaction layer packet into the receive queue in the memory, and trigger an interrupt to notify the central processing unit firmware.

[0039] In an embodiment of this application, when the host sends a first transaction layer packet (TLP packet) to the EP device through the PCIe bus, the TLP packet processing bridge at the hardware level first completes the protocol parsing and verification of the physical layer and the data link layer, and then classifies and processes it according to the TLP packet type (such as configuration space read / write request, memory access request or Message packet). This processing bridge adopts a circular queue management mechanism, writes the received TLP packets into the tail of the receive queue in the memory in the order of arrival, and simultaneously updates the status of the tail pointer of the queue. During this process, the interrupt logic unit monitors the change of the write status of the receive queue in real time. When it detects that a new TLP packet has successfully entered the queue, it immediately triggers an edge-triggered interrupt signal to the CPU firmware. It should be noted that this interrupt mechanism adopts a threshold configurable design, allowing the firmware to dynamically set the interrupt trigger condition (such as single-packet trigger or batch trigger) to balance real-time performance and interrupt processing overhead. In addition, when the hardware processes the enqueue of the TLP packet, it will perform a preliminary parsing of the packet header, extract key metadata (such as request type, address field) and attach it to the queue entry descriptor to provide preprocessing information for subsequent software processing, thereby reducing the parsing overhead of the firmware. The entire receiving process adopts a double-buffer mechanism to ensure that when the firmware processes the current packet, the hardware can continue to receive subsequent TLP packets to achieve pipelined operation.

[0040] Step S12: Read the first transaction layer packet from the head of the receive queue through the central processor firmware, and access the shadow configuration space or shadow registers according to the event type of the first transaction layer packet to perform corresponding read and write operations.

[0041] It should be noted that the TLP packet processing bridge has written the TLP packet sent by the host to the tail of the receive queue and triggered the interrupt logic to send an interrupt signal to the CPU. After receiving the interrupt, the CPU enters the interrupt service routine (ISR) and identifies that the interrupt source is that the TLP receive queue is not empty. Among them, the management mechanism of the receive queue is as follows: a circular buffer (Ring Buffer) or linked list structure is adopted, and the readable position is identified by the head pointer (Head) and tail pointer (Tail). The hardware (TLP packet processing bridge) updates the tail pointer through atomic operations, and the CPU firmware moves the head pointer through atomic operations to avoid read and write conflicts.

[0042] In the embodiment of the present application, the CPU firmware obtains the position of the currently to-be-processed TLP packet through the head pointer. Read the header fields of the TLP packet (such as type, length, address, etc.) to determine the event type: for a configuration space access request, the TLP packet type is a configuration read / write request (Type field is 0x04 or 0x05); for a BAR access request, the TLP address falls within the address range mapped by the BAR (determined by the base address in the shadow register); for a memory access request, the TLP type is a Memory read / write request (Type field is 0x00 or 0x01). Subsequently, corresponding operations are performed according to the event type. Among them, for a configuration space access request, directly read and write the shadow configuration space; for a base address register access request, read and write the shadow register mapped address; for a memory access request, complete data transmission through multiple transaction layer packet interactions and send an interrupt to notify the host after completion.

[0043] In the embodiment of the present application, accessing the shadow configuration space or shadow registers according to the event type of the first transaction layer packet to perform corresponding read and write operations includes the following steps A1 - A2:

[0044] Step A1: If the event type of the first transaction layer packet is a configuration space access request, read or write the register value at the specified offset from the shadow configuration space.

[0045] Specifically, when the event type of the first transaction layer packet (TLP packet) is a configuration space access request, the CPU firmware will parse the Register Number field in the TLP packet to determine the target register offset. For read requests, the firmware extracts the register value (such as Vendor ID, Device ID, or BAR configuration parameters) from the corresponding offset in the shadow configuration space, and constructs a configuration read completion TLP packet containing this data and returns it to the host. For write requests (such as when the host performs BAR space probing), the firmware writes the Payload in the TLP packet to the shadow configuration space and performs value conversion according to the protocol semantics (for example, converting a write of all 1s to the actual address mask). This process dynamically manages the configuration space through software, allowing the device identification, capability set, or resource requirements (such as dynamically adjusting the BAR size) to be modified at runtime, breaking through the limitations of traditional hardware fixed designs. For example, during the device enumeration phase, when the host reads the Vendor ID, the firmware directly returns the preset value 0x1234 from the 0x00 offset of the shadow configuration space, without relying on the physical register circuit.

[0046] Step A2, if the event type of the first transaction layer packet is a base address register access request, read or write the data corresponding to the base address register mapped address from the shadow register.

[0047] Specifically, if the TLP packet event type is a base address register (BAR) access request, the CPU firmware first matches the TLP address field with the allocated BAR base address to calculate the register offset. For Memory mapped access, the firmware subtracts the BAR base address from the request address to obtain the logical offset within the shadow register space, and then performs read / write operations. During the read operation, data is extracted from the shadow register to generate a Memory read completion TLP (such as returning the DMA address register value); the write operation updates the shadow register and triggers subsequent logic (such as writing to the doorbell register to start a DMA transfer). This mechanism enables the BAR function to be completely defined by software - the shadow register can be dynamically reconfigured as a control register, status register, or command queue, and even mapped to the virtual address space. For example, in the DMA scenario, after the host writes to the doorbell register at the BAR0 + 0x10 offset, the firmware autonomously constructs a Memory read TLP to initiate a DMA transfer by parsing the DMA parameters (address, length) in the shadow register, achieving hardware-independent bus transaction control.

[0048] As an example, Figure 2 is a schematic diagram of the enumeration process for an extended device, such as Figure 2As shown, the process includes: First, the CPU firmware initializes the shadow configuration space, sets the Vendor ID register to 0x1234 (step ①), and the host sends a configuration space read TLP packet (step ②) to read the Vendor ID. After the EP firmware parses it, it obtains the value from the shadow configuration space and constructs a completion packet for reply. Then, the host sends a configuration space write TLP packet (step ④), obtains its size and attributes by writing 0xFFFFFFFF to the BAR0 register, and the EP firmware modifies the value to 0xFFFFF000 according to the protocol and writes it into the shadow configuration space (step ⑤), then constructs a completion packet (step ⑥). Subsequently, the host reads BAR0 to determine that it is a 4kB-sized Non-prefetchable Memory BAR. Finally, the host allocates an address space for BAR0, and configures the address for the EP device through a similar configuration write operation (steps ④, ⑤, ⑥). The EP firmware stores the BAR0 value in the shadow configuration space, completing the configuration space interaction and BAR processing during the enumeration process.

[0049] The method provided by the embodiment of the present application realizes hierarchical dynamic management of configuration parameters and address mapping by accessing the shadow configuration space and shadow registers separately according to different event types. When the host initiates a configuration space access request, it directly operates the register value of the shadow configuration space, supporting runtime modification of device function fields; while for the base address register access request, it reads and writes through the shadow register mapped address, enabling flexible adjustment of the address space allocation strategy. This design avoids the limitations of traditional hardware-fixed configuration, enabling extended devices to dynamically adapt to scenarios such as protocol updates and virtualized resource allocation according to actual needs, significantly improving the flexibility of system configuration and resource utilization.

[0050] In the embodiment of the present application, the method further includes the following steps B1 - B3:

[0051] Step B1, if the event type of the first transaction layer packet is a memory access request, read the preset cache address and preset data length from the shadow register.

[0052] Specifically, when the CPU firmware parses that the TLP packet type is a Memory read / write request, it first performs address conversion according to the BAR register mapping rule: subtracts the BAR base address from the target address in the TLP packet to obtain the register offset. By querying the storage location corresponding to the offset in the shadow register space, the DMA parameters pre-configured by the host are obtained, including the preset cache address (i.e., the DMA source address) in the host memory and the preset data length (the total amount of data to be transferred). These parameters are from the configuration process of the device doorbell register, DMA address register, and data length register by the host through the Memory write TLP packet. The shadow register converts the physical address access into access to the local storage space through the address remapping mechanism, realizing parameter transfer between the host and the device.

[0053] Step B2: Construct a second transaction layer packet according to the preset cache address and send the second transaction layer packet to the host, where the second transaction layer packet is used to read the memory access data of the host.

[0054] Specifically, the CPU firmware constructs a Memory read request TLP packet based on the obtained preset cache address. This TLP packet includes a destination address field (i.e., the host DMA cache address), a data length field (the maximum payload for a single request), and a transaction type identifier (indicating a Memory read operation). The generated TLP packet is written to the tail of the send queue in the memory and triggers the interrupt notification mechanism of the hardware interface. The TLP packet processing bridge retrieves the request packet from the head of the queue and sends it to the host RC via the PCIe link. This process adopts a block transfer mechanism. When the preset data length exceeds the maximum payload of a single TLP packet, the firmware automatically decomposes the total request into multiple sub-requests that comply with the PCIe protocol length limit.

[0055] Step B3: Receive the second response packet and the next second transaction layer packet returned by the host, and repeat the memory access data transmission process until the data length of the received memory access data reaches the preset data length, and then send a first response packet with an interrupt type of memory access completion interrupt to the host.

[0056] Specifically, after receiving the Memory read request, the host encapsulates the data at the target address into a Memory read completion TLP packet (including the actual read data payload) and returns it to the EP device. The TLP packet processing bridge writes the response packet to the receive queue and triggers an interrupt. The CPU firmware extracts the data and performs a length cumulative check. If the preset data length is not reached, the firmware continues to generate subsequent Memory read request TLP packets (the address is automatically incremented by an offset), initiating a new round of data transmission. When the cumulative data volume reaches the preset value, the firmware constructs an MSI / MSI-X interrupt TLP packet (the address and data are generated according to the shadow configuration space interrupt capability structure) and submits it to the host via the send queue to complete the DMA transfer cycle. This process realizes the closed-loop control of the transmission state, ensuring data integrity while supporting dynamic adjustment of the request granularity.

[0057] The method provided by the embodiment of the present application is directed to memory access requests. It pre-stores cache addresses and data lengths through shadow registers, and uses multiple transaction layer packet interactions to achieve data block transfer, solving the problems of low efficiency and high latency in traditional hardware's direct memory access. The expansion device actively requests data from the host by constructing a second transaction layer packet, and combines with a loop transfer mechanism until the preset data length is reached, ensuring the efficiency and integrity of large data volume transfer. At the same time, a specific interrupt is sent to notify the host after the memory access is completed, realizing the collaborative optimization of data transfer and system resource management, and is applicable to the real-time data interaction requirements in high-performance computing and heterogeneous acceleration scenarios.

[0058] Step S13: Generate a first response packet corresponding to the transaction layer packet according to the execution result of the read / write operation, write the first response packet into the send queue, and send it to the host by the hardware interface, where the first response packet is used to notify the host through an interrupt.

[0059] In the embodiment of the present application, the central processing unit firmware dynamically constructs a first response packet (TLP) that matches the event type according to the read / write operation results of the shadow configuration space or shadow registers. For example, if it is a configuration space read request, the register value at the specified offset in the shadow configuration space is encapsulated as a configuration read completion TLP; if it is a BAR register write request, a Memory write completion TLP containing the operation status code is generated. The generated response packet is written to the end of the send queue, and is extracted by the hardware interface (TLP packet processing bridge) in the queue order and sent to the host through the PCIe link. At the same time, the interrupt logic triggers an interrupt when the TLP at the head of the send queue is taken out, notifying the host that the response has been sent. This process flexibly constructs the response content through software, supports protocol extension (such as new completion packet formats), and the hardware is only responsible for passthrough, realizing the full programmability of the response logic.

[0060] The embodiment of the present application also provides an expansion device interaction method, which is applied to the host. Figure 3 It is a flowchart of the expansion device interaction method according to the embodiment of the present invention, as Figure 3 shown, and this process includes the following steps:

[0061] Step S31: Obtain the current read / write requirements for the expansion device.

[0062] In the embodiments of the present application, the read and write requirements of the host originate from system layer operations. For example, when enumerating devices, it is necessary to obtain the Vendor ID, or when performing DMA transmission, it is necessary to write to the device doorbell register. The host driver parses the resource allocation instructions issued by the operating system (such as PCIe configuration space detection) and the data transfer requirements of the application layer (such as network packet DMA transmission), and converts them into specific access intentions for the PCIe EP, clarifying the target address space type (configuration space, BAR mapped memory), operation type (read / write), and associated parameters (address offset, data payload).

[0063] Step S32, determine the event type according to the read and write requirements, and generate a first transaction layer packet corresponding to the event type, where the event type includes a configuration space access request, a base address register access request, and a memory access request.

[0064] In the embodiments of the present application, a structured TLP packet is generated according to the required event type. For example, for a configuration space access request, the TLP type needs to be set to configuration read / write, and the Register Number field is filled (such as 0x00 corresponding to the Vendor ID); for a memory access request, a Memory read / write TLP is constructed, and the address field is calculated from the BAR base address and the register offset, and the Payload carries the written value or reserves the read request bit. The host driver assembles the TLP header, data payload, and ECRC check (if enabled) according to the PCIe protocol specification to ensure that the packet format meets the requirements of the hardware link layer.

[0065] Step S33, send the first transaction layer packet to the expansion device, so that the expansion device accesses the shadow configuration space or shadow register according to the event type of the first transaction layer packet, completes the register read / write operation, or triggers the memory access data transmission.

[0066] In the embodiments of the present application, the host RC (root complex) injects the generated TLP packet into the PCIe link, and the target address points to the expansion device (EP device). After sending, the host driver may enter a blocking wait (such as a synchronous configuration read operation) or asynchronously listen for a completion interrupt (such as a DMA write). For requests that require a response (such as a Memory read), after the host receives the read completion TLP from the EP, it extracts the data from the specified memory address and returns it to the upper-layer application. This process interacts with the EP through the TLP routing mechanism of the hardware RC to achieve end-to-end transaction layer communication.

[0067] In the embodiments of the present application, the method further includes the following steps C1 - C4:

[0068] Step C1, allocate preset cache resources for the expansion device in the host memory, where the preset cache resources include a preset cache address and a preset data length.

[0069] Specifically, before starting a DMA transfer, the host needs to pre-allocate a continuous physical memory area in its own memory as a buffer for data transfer, which is called the preset cache resource. The host operating system or driver applies for a physical memory block of a specified size through a memory management module (such as the DMA API) and records its starting physical address (preset cache address) and total length (preset data length). This cache is used to temporarily store the data content to be transferred (such as the host sending data to the device in the DMA write scenario) or receive the data read by the device (such as the device obtaining data from the host in the DMA read scenario). To ensure the reliability and efficiency of the DMA transfer, the allocated cache needs to meet the PCIe address alignment requirements and avoid being swapped out of physical memory through the memory locking mechanism.

[0070] Step C2: Construct a first transaction layer packet based on the preset cache address and the preset data length and send it to the expansion device, so that the expansion device constructs a second transaction layer packet based on the first transaction layer packet.

[0071] Specifically, the host configures the preset cache address and the preset data length into the shadow register of the PCIe EP device by constructing and sending a specific Memory write TLP packet. The specific process is as follows: The host generates a Memory write TLP packet with the target address being the offset address of the DMA cache address register mapped by the EP device's BAR0, and fills the Payload field with the preset cache address. This TLP packet notifies the EP device of the target host memory address for subsequent DMA operations; The host generates a second Memory write TLP packet with the target address being the offset address of the DMA data length register mapped by BAR0, and fills the Payload field with the preset data length, indicating the total amount of data to be transferred; The host sends a third Memory write TLP packet to the offset address of the doorbell register mapped by BAR0 (the Payload value is usually a specific trigger flag). After the expansion device firmware detects the write to the doorbell register, it starts to construct a Memory read TLP packet (i.e., the second transaction layer packet) based on the cache address and length information in the shadow register and initiates a DMA data transfer request.

[0072] Step C3: Receive the second transaction layer packet sent by the expansion device.

[0073] Specifically, when the extended device (EP device) starts a DMA read operation, its firmware constructs Memory read TLP packets (second transaction layer data packets) in batches according to the preset data length, requesting to read data from the preset cache address of the host. After the host PCIeRC receives these TLP packets, it parses the address field (pointing to the preset cache address) and the read request length, reads data from the corresponding host memory location, and generates a Memory read completion TLP packet (second response data packet). In this step, the host needs to ensure that it responds to each read request in a timely manner, accurately extracts data according to the address and length in the TLP packet, and encapsulates it into a read completion packet with a payload and returns it to the EP device.

[0074] Step C4, read the corresponding memory access data according to the second transaction layer data packet, and send the memory access data as the second response data packet to the expansion device, and execute the transmission operation in a loop until a first response data packet with an interrupt type of memory access completion interrupt sent by the expansion device is received.

[0075] Specifically, the host performs the following operations for each Memory Read TLP packet (second transaction layer data packet) initiated by the EP device: according to the address and length in the TLP packet, read the data from the memory area corresponding to the preset cache address, generate a Memory Read Completion TLP packet (second response data packet) containing the data, and send it to the EP device; repeatedly receive the read request TLP packet of the EP device and return the read completion packet until the cumulative transmitted data length reaches the preset data length; when the EP device completes all data transmission, it will notify the host through the MSI / MSI-X interrupt TLP packet (first response data packet, the interrupt type is memory access completion interrupt). After receiving this interrupt, the host confirms that the DMA transfer is successful, releases the preset cache resources (such as unlocking the memory, reclaiming the physical memory), and updates the local status (such as recording the transfer results). This process ensures the atomicity of DMA transmission and the effectiveness of resource management.

[0076] The method provided in the embodiment of the present application provides clear data access instructions for the expansion device by pre-allocating cache resources and constructing a transaction layer data packet containing the cache address and length. The expansion device actively initiates a memory read request based on this information, and the host returns data in blocks according to each request, forming an efficient two-way data transmission channel. This design avoids the waste of resources caused by traditional fixed cache allocation and supports dynamic adjustment of cache size to adapt to different application scenarios. The cyclic transmission mechanism ensures data integrity, and the memory access completion interrupt realizes the timely release and recovery of resources, improving the overall resource management efficiency and stability of the system.

[0077] In the embodiment of the present application, after sending the first transaction layer data packet to the extension device, the method further includes steps D1-D2:

[0078] Step D1, receiving a first response data packet returned by the expansion device, and parsing the interrupt type in the first response data packet.

[0079] Specifically, after the host receives the first response data packet from the expansion device through the PCIe link, it first parses the interrupt identification field in its TLP packet header (such as the address and data matching rules of MSI / MSI-X). For MSI interrupts, it is necessary to compare the interrupt address range defined by the MSI Capability structure in the shadow configuration space; for MSI-X interrupts, it is matched according to the preset vector table entries in the MSI-XTable. During parsing, it is necessary to extract the interrupt type code (such as 0xA1 indicates that the memory access is completed, and 0xB0 indicates that the configuration space read and write is completed), and at the same time verify the ECRC checksum of the TLP packet to ensure the transmission integrity. If the interrupt type is a composite event (such as multi-vector interrupt aggregation), it is also necessary to parse the specific trigger event through the Pending Table bitmap.

[0080] Step D2, when the interrupt type is a memory access completion interrupt, release the preset cache resources allocated in the host memory, or, when the interrupt type is a read / write completion interrupt, store the execution result in the first response data packet into the local storage.

[0081] Specifically, if it is parsed as a memory access completion interrupt (such as the end of DMA transmission), the host calls the memory management unit (MMU) to release the physical address mapping of the DMA buffer, reclaims the cache page frame through the SLAB allocator, and updates the ATS (Address Translation Services) table entry status of the PCIe RC. For read and write completion interrupts, the host writes the Payload data to the target register according to the Byte Enable bit mask in the TLP packet: the configuration space access result is written to the PCIe topology database, and the BAR register value is updated to the RC's BAR remapping table. Atomic operations with ECC checking are used during storage to ensure that critical data (such as the upper 32 bits of the BAR base address) complete the state synchronization of the cache consistency protocol (such as MESI) before writing to the local NVDIMM persistent storage.

[0082] As an example, Figure 4As shown in the figure, the process of the expansion device reading data from the host memory includes: First, the host allocates a DMA cache in the memory (step ①), and writes the DMA cache address and data length into the corresponding registers in the EP device BAR0 shadow register through a Memory write TLP packet (step ②), and then writes the doorbell register (step ③) to trigger the operation; after the EP's CPU firmware receives the doorbell event (step ④), it reads the DMA address and length from the shadow register (step ⑤), constructs a Memory read TLP packet to request data from the host (step ⑥), repeats the reading until the data volume meets the requirements, and finally constructs an MSI / MSIX interrupt write request (step ⑦) to send a DMA completion interrupt to the host, completing the entire process of DMA data transfer from the host memory to the PCIe EP device.

[0083] The method provided by the embodiment of the present application realizes a differentiated subsequent processing strategy by parsing the interrupt type in the response data packet returned by the expansion device. When a memory access completion interrupt is received, the pre-allocated cache resources are immediately released to avoid memory leakage and improve the resource reuse rate; while the read / write completion interrupt triggers the result storage operation to ensure the correctness of the configuration parameter modification or register read / write. This mechanism closely combines the data processing result with the system resource management, not only ensuring the reliability of the operation, but also optimizing the collaborative work process between the host and the expansion device, and is applicable to complex computing scenarios that require frequent dynamic configuration and data interaction.

[0084] In the embodiment of the present application, for the interrupt triggering mechanism, a dynamic interrupt merging technology based on queue depth prediction is further introduced to optimize the interrupt efficiency. The specific implementation method is as follows: The hardware interrupt logic unit embeds a lightweight LSTM neural network prediction model (the model parameters are solidified in the hardware microcode), and the input features are the enqueue rate of the receive queue, the historical data of the interrupt response delay of the CPU firmware, and the current queue occupancy rate collected in real time. The prediction model performs forward inference every 128 clock cycles, outputs the predicted values of the queue depth for the next three time windows (Δt1 = 2μs, Δt2 = 5μs, Δt3 = 10μs), and dynamically adjusts the interrupt triggering threshold according to the prediction results - when it is predicted that the queue depth will reach 75% of the queue capacity within Δt3, an interrupt is immediately triggered to avoid overflow; if it is predicted that no new TLP will arrive during the subsequent Δt1 period, the interrupt triggering threshold is automatically increased to twice the current queue length, and the interrupt triggering is delayed to merge more TLP processing. The prediction model is implemented by fixed-point arithmetic in hardware, includes 3 layers of gating units (a total of 512 neurons), uses 8-bit quantized weights, and the inference process consumes no more than 200 clock cycles. In addition, the interrupt logic maintains a threshold adjustment register group (ThresholdAdjust Register, TAR), and the firmware can set the base threshold by writing to TAR[7:0], and the hardware prediction result is dynamically offset by ±25% based on this value. This mechanism enables the interrupt triggering to adapt to short-term traffic fluctuations and follow the global policy of the firmware. It is measured that more than 38% of redundant interrupt events can be reduced, and at the same time, 99.9% of the TLP processing delays are lower than the thresholds required by the protocol.

[0085] Figure 5 Schematic diagram of the interaction architecture between the expansion device and the host, as Figure 5 shown, including: The PCIeEP device (expansion device) includes a PCIeEP hardware interface (composed of a TLP packet processing bridge that processes the transceiver and queue maintenance of TLP packets and an interrupt logic unit that generates queue status change interrupts), a memory (stores the TLP receive / send queue, a shadow configuration space that manages configuration space data, and shadow registers that store BAR register data), and CPU firmware (cooperates to process the TLP queue, manages the shadow configuration space and registers, and initiates host DMA read / write requests and MSI / MSIX interrupt requests); The host interacts with the EP device through PCIeRC, covering various TLP packet types such as configuration space read / write, Memory read / write, etc. The EP device processes the TLP packets sent by the host according to the process, and constructs TLP packets by the CPU firmware and sends them to the host through the queue to implement functions such as configuration operations, data transmission, and interrupt interaction.

[0086] In the embodiments of the present application, the technical solution of the present invention is implemented based on a specific software-hardware collaborative architecture. Its core hardware architecture consists of three main modules: a PCIe EP hardware interface module, a shared memory module, and a CPU firmware processing module. These modules form a hierarchical processing architecture through close collaboration to support the implementation of dynamically configurable PCIe EP functions.

[0087] The PCIe EP hardware interface module, which includes a TLP packet processing bridge and an interrupt logic unit, directly interfaces with the PCIe physical layer and data link layer. The TLP packet processing bridge adopts a dual-channel DMA engine design, with a built-in receive / transmit queue controller that directly accesses the TLP queue in the shared memory through physical address mapping. The hardware implements the following key features: TLP classification engine: It can identify the TLP type (configuration space request, memory read / write, Message packet, etc.) in real time through the header parsing circuit (Parsing Engine) and attach metadata tags to the queue descriptor; circular queue management: It adopts a circular buffer structure with separated head and tail pointers. The receive queue implements hardware-level flow control (Credit-Based Flow Control) to prevent queue overflow; interrupt optimization mechanism: The interrupt logic supports programmable threshold trigger modes (such as triggering an interrupt every N received TLP packets) and immediate trigger mode, and can be dynamically switched through the configuration register.

[0088] The shared memory module adopts a multi-Bank SRAM architecture and is divided into three functional areas: TLP queue storage area: The receive / transmit queue adopts a descriptor chaining structure. Each TLP entry includes a 64B header buffer and a 4KB payload buffer, supporting a maximum single-packet transmission of 4MB; shadow configuration space: It is implemented as a 256B register file with ECC check, mapping the PCIe standard configuration space (0x000 - 0x3FF), and supporting the atomic read / write operation lock mechanism; shadow BAR register area: It provides an expandable windowed address mapping. Each BAR area is configured with independent attribute registers (including address mask, prefetch enable, type identifier), supporting dynamic remapping.

[0089] The CPU firmware processing module is built based on RISC-V or ARM Cortex-M series processors and runs a real-time operating system (RTOS). It mainly includes the following processing units: TLP distribution engine: extracts TLPs from the receive queue through an interrupt service routine (ISR) and distributes them to the corresponding processing threads according to metadata tags; virtual configuration space manager: implements the PCIe configuration space protocol state machine and supports dynamic register remapping in hot-plug scenarios; DMA engine simulation layer: realizes virtual DMA channels through TLP recombination technology, supports Scatter-Gather list processing and address translation (ATS) extension.

[0090] The system runs in a mixed-criticality execution environment and divides security domains through a hardware isolation mechanism: real-time domain, processes TLP receive / send interrupt service routines to ensure that key operations such as configuration space access meet the PCIe protocol timing requirements (e.g., configuration read / write responses need to be completed within 2 μs); non-real-time domain, runs advanced function processing logic, including DMA transfer scheduling, interrupt message generation, and BAR dynamic configuration algorithms, and uses priority pre-emptive task scheduling; secure enclave, based on TEE (Trusted Execution Environment), realizes key management and secure boot, and encrypts and stores sensitive configuration data (such as MSI-X Table).

[0091] This system architecture realizes PCIe function virtualization through a shadow register group, allowing the BAR address mapping relationship to be modified at runtime. For example, in a virtualization scenario, the fast switching of VF (Virtual Function) can be achieved by modifying the BAR attribute register. A configuration space access accelerator is integrated in the TLP packet processing bridge to implement bypass caching (Bypass Cache) for frequently accessed read-only registers such as Vendor ID / DeviceID, reducing the firmware processing latency. The interrupt logic unit incorporates an intelligent merging algorithm to automatically merge multiple completion interrupts into a single interrupt event for DMA transfer scenarios, reducing the CPU load caused by interrupt storms.

[0092] Through the decoupled design of hardware queue management and software-defined functions, this architecture achieves more than 10 times the configuration flexibility of traditional all-hardware solutions while ensuring the real-time requirements of the PCIe protocol, and the hardware resource consumption is reduced by approximately 35% (compared with the FPGA implementation solution). Tests show that in a typical NVMe-over-Fabrics application scenario, this architecture can achieve 98% protocol compatibility and an interrupt response latency of less than 5 μs.

[0093] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0094] An embodiment of the present application also provides an extended device function configuration device, which is applied to an extended device, such as Figure 6 shown, including:

[0095] A receiving module 61, configured to receive a first transaction layer data packet sent by a host, write the first transaction layer data packet into a receiving queue in a memory, and trigger an interrupt to notify a central processing unit firmware;

[0096] A reading module 62, configured to read the first transaction layer data packet from the head of the receiving queue through the central processing unit firmware, and access a shadow configuration space or a shadow register according to the event type of the first transaction layer data packet to perform corresponding read and write operations;

[0097] A first sending module 63, configured to generate a first response data packet corresponding to the transaction layer data packet according to the execution result of the read and write operation, write the first response data packet into a sending queue, and send it to the host through a hardware interface, where the first response data packet is used to notify the host through an interrupt.

[0098] Further, the reading module 63 is configured to, if the event type of the first transaction layer data packet is a configuration space access request, read or write a register value at a specified offset from the shadow configuration space; if the event type of the first transaction layer data packet is a base address register access request, read or write data corresponding to the mapped address of the base address register from the shadow register.

[0099] Further, the device further includes: a construction module, configured to, if the event type of the first transaction layer data packet is a memory access request, read a preset cache address and a preset data length from the shadow register; construct a second transaction layer data packet according to the preset cache address, and send the second transaction layer data packet to the host, where the second transaction layer data packet is used to read memory access data of the host; receive a second response data packet and a next second transaction layer data packet returned by the host, and repeatedly execute the memory access data transmission process until the data length of the received memory access data reaches the preset data length, and send a first response data packet with an interrupt type of a memory access completion interrupt to the host.

[0100] An embodiment of the present application also provides an extended device interaction device, which is applied to a host, such as Figure 7 shown, including:

[0101] An obtaining module 71, configured to obtain current read and write requirements for an extended device;

[0102] A generating module 72, configured to determine an event type according to the read and write requirements, and generate a first transaction layer data packet corresponding to the event type, where the event type includes a configuration space request, a base address register request, and a memory access request;

[0103] A second sending module 73, configured to send a first transaction layer data packet to an expansion device, so that the expansion device accesses a shadow configuration space or a shadow register according to an event type of the first transaction layer data packet, completes a register read / write operation, or triggers a memory access data transmission.

[0104] Further, the apparatus further includes: an allocation module, configured to allocate preset cache resources for the expansion device in a host memory, where the preset cache resources include a preset cache address and a preset data length; construct a first transaction layer data packet according to the preset cache address and the preset data length and send the first transaction layer data packet to the expansion device, so that the expansion device constructs a second transaction layer data packet according to the first transaction layer data packet; receive a second transaction layer data packet sent by the expansion device; read corresponding memory access data according to the second transaction layer data packet, and send the memory access data as a second response data packet to the expansion device, and loop to execute a transmission operation until a first response data packet whose interrupt type is a memory access completion interrupt sent by the expansion device is received.

[0105] Further, the apparatus further includes: a parsing module, configured to receive a first response data packet returned by the expansion device and parse an interrupt type in the first response data packet; when the interrupt type is a memory access completion interrupt, release the preset cache resources allocated in the host memory, or when the interrupt type is a read / write completion interrupt, store an execution result in the first response data packet in a local storage.

[0106] An embodiment of the present application further provides an electronic device, as Figure 8 shown, including a memory 10 and a processor 20. A computer program is stored in the memory 10, and the processor 20 is configured to run the computer program to execute steps in any one of the above-mentioned expansion device function configuration methods and an expansion device interaction method embodiment.

[0107] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, where the computer program is configured to execute steps in any one of the above-mentioned method embodiments when running.

[0108] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disc, and other media that can store a computer program.

[0109] Embodiments of the present application also provide a computer program product. The computer program product includes a computer program which, when executed by a processor, implements the steps in any of the above-described extended device function configuration methods and embodiments of an extended device interaction method.

[0110] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program which, when executed by a processor, implements the steps in any of the above-described extended device function configuration methods and embodiments of an extended device interaction method.

[0111] Those skilled in the art can further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0112] The above has introduced in detail an extended device function configuration method and an extended device interaction method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. An extended device function configuration method, applied to an extended device, characterized in that, including: Receiving a first transaction layer packet sent by a host, writing the first transaction layer packet into a receive queue in a memory, and triggering an interrupt to notify a central processor firmware; Reading, by the central processor firmware, the first transaction layer packet from the head of the receive queue, and accessing a shadow configuration space or a shadow register according to an event type of the first transaction layer packet to perform corresponding read / write operations; Generating a first response packet corresponding to the transaction layer packet according to an execution result of the read / write operation, writing the first response packet into a send queue, and sending the first response packet to the host by a hardware interface, wherein the first response packet is used to notify the host through an interrupt.

2. The method according to claim 1, wherein The accessing the shadow configuration space or the shadow register according to the event type of the first transaction layer packet to perform corresponding read / write operations includes: If the event type of the first transaction layer packet is a configuration space access request, reading or writing a register value at a specified offset from the shadow configuration space; If the event type of the first transaction layer packet is a base address register access request, reading or writing data corresponding to a mapped address of the base address register from the shadow register.

3. The method according to claim 2, wherein The method further includes: If the event type of the first transaction layer packet is a memory access request, reading a preset cache address and a preset data length from the shadow register; Constructing a second transaction layer packet according to the preset cache address, and sending the second transaction layer packet to the host, wherein the second transaction layer packet is used to read memory access data of the host; Receiving a second response packet and a next second transaction layer packet returned by the host, repeating an execution of a memory access data transmission process until a data length of the received memory access data reaches the preset data length, and sending a first response packet with an interrupt type of a memory access completion interrupt to the host.

4. An extended device interaction method, applied to a host, characterized in that, including: Obtaining current read / write requirements for an expansion device; Determining an event type according to the read / write requirements, and generating a first transaction layer packet corresponding to the event type, wherein the event type includes a configuration space access request, a base address register access request, and a memory access request; Sending the first transaction layer packet to the expansion device, so that the expansion device accesses a shadow configuration space or a shadow register according to the event type of the first transaction layer packet to complete register read / write operations or trigger memory access data transmission.

5. The method according to claim 4, wherein The method further includes: Allocating a preset cache resource for the expansion device in a host memory, wherein the preset cache resource includes a preset cache address and a preset data length; Constructing a first transaction layer packet according to the preset cache address and the preset data length, and sending the first transaction layer packet to the expansion device, so that the expansion device constructs a second transaction layer packet according to the first transaction layer packet; Receiving a second transaction layer packet sent by the expansion device; Read the corresponding memory access data according to the second transaction layer data packet, and send the memory access data to the expansion device as a second response data packet, and loop to execute the transmission operation until a first response data packet with an interrupt type of memory access completion interrupt sent by the expansion device is received.

6. The method according to claim 4, characterized in that, After sending the first transaction layer data packet to the expansion device, the method further includes: Receiving a first response data packet returned by the expansion device, and parsing the interrupt type in the first response data packet; When the interrupt type is a memory access completion interrupt, releasing the preset cache resources allocated in the host memory, or when the interrupt type is a read / write completion interrupt, storing the execution result in the first response data packet in the local storage.

7. An extended device function configuration device, applied to an extended device, characterized in that Includes: A receiving module, configured to receive a first transaction layer data packet sent by a host, write the first transaction layer data packet into a receiving queue in a memory, and trigger an interrupt to notify a central processing unit firmware; A reading module, configured to read a first transaction layer data packet from the head of the receiving queue through the central processing unit firmware, and access a shadow configuration space or a shadow register according to the event type of the first transaction layer data packet to perform corresponding read / write operations; A first sending module, configured to generate a first response data packet corresponding to the transaction layer data packet according to the execution result of the read / write operation, write the first response data packet into a sending queue, and send it to the host by a hardware interface, where the first response data packet is used to notify the host through an interrupt.

8. An extended device interaction device, applied to a host, characterized in that Includes: An obtaining module, configured to obtain the current read / write requirements for the expansion device; A generating module, configured to determine an event type according to the read / write requirements, and generate a first transaction layer data packet corresponding to the event type, where the event type includes a configuration space request, a base address register request, and a memory access request; A second sending module, configured to send the first transaction layer data packet to the expansion device, so that the expansion device accesses a shadow configuration space or a shadow register according to the event type of the first transaction layer data packet, completes a register read / write operation, or triggers a memory access data transmission.

9. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, where the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 6.

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