Timing controller for minimizing power consumption during blank period
By generating signals during the blank period detection circuit and controlling the power-down mode, the memory device in the display device is deactivated, which solves the problem of excessive power consumption during the blank period and achieves a significant reduction in power consumption.
Patent Information
- Application Number
- CN202380084070.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-12-07
- Filing Date
- 2023-12-05
- Publication Date
- 2025-07-22
AI Technical Summary
In the prior art, the power consumption of the display device during the blank period cannot be effectively reduced due to the continuous activation of the memory device.
By generating a blank period detection signal during the blank period detection circuit, the power-down control signal generation circuit is controlled to deactivate the memory device in the functional block, and the power-down mode is realized and power consumption is reduced.
The power consumption of the display device during the blank period is effectively reduced, especially in the display panel that provides the touch panel function, which significantly reduces power consumption.
Smart Images
Figure CN120359561A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a timing controller, and more particularly, to a timing control circuit capable of minimizing power consumption during a blank period by disabling the operation of a functional block included in the timing controller or a memory device included in a corresponding functional block during the blank period. Background Art
[0002] A display device includes a display panel for reproducing an image, a driving unit for driving the display panel, and a timing controller for controlling the operation of the driving unit. Here, the driving unit includes a gate driver for driving gate lines and a data driver formed on the display panel.
[0003] The timing controller receives a plurality of control signals and image data from an external driving system (not shown) and generates a plurality of control signals and a main clock signal for controlling the driving unit.
[0004] The driving unit processes the image data into a source signal in response to the control signals received from the timing controller and then outputs it to the display panel. At this time, the image data is sent from the external driving system and sent to the driving unit via the timing controller.
[0005] The display panel operates alternately in an active period or a display period of the input source signal and a blank period between each active period during which no source signal is input. During the blank period, the driving unit prevents leakage current of the display panel by supplying a single voltage to the display panel.
[0006] Among the plurality of functional blocks installed in the timing controller, there are functional blocks that operate normally during an active period (i.e., a display period) but do not need to operate during a blank period. Among these functional blocks, a functional block having a storage device (i.e., a memory) always operates in an active state even during a blank period when the functional block does not need to operate, which results in unnecessary power consumption. Summary of the Invention
[0007] Technical Problem
[0008] The technical problem to be solved by the present invention is to provide a timing controller capable of minimizing power consumption during a blank period by disabling the operation of an internal functional block or a memory device included in a corresponding functional block during the blank period.
[0009] Another technical problem to be solved by the present invention is to provide a display device including a timing controller capable of minimizing power consumption during a blank period by disabling the operation of an internal functional block or a memory device included in a corresponding functional block during the blank period.
[0010] Technical solution
[0011] According to one aspect of the present invention for solving the above technical problem, a timing controller that restores a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizes power consumption during a blank period may include: a blank period detection circuit configured to generate a blank period detection signal using the clock signal and the gate driving signal; and a functional block group including a plurality of functional blocks configured to perform operations according to a display period and a blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal.
[0012] According to another aspect of the present invention for solving the above technical problem, a timing controller that restores a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and minimizes power consumption during a blank period may include: a blank period detection circuit that generates a blank period detection signal using the clock signal and the gate driving signal; a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal; and a functional block group including a plurality of functional blocks configured to perform operations according to a display period and a blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal.
[0013] According to one aspect of the present invention for solving the above another technical problem, a display device that minimizes power consumption during a blank period may include: a display panel; a driving unit configured to drive the display panel; and a timing controller including: a blank period detection circuit configured to restore a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal using the clock signal and the gate driving signal, and a functional block group including a plurality of functional blocks configured to perform operations according to a display period and a blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal and configured to control the operation of the driving unit.
[0014] According to another aspect of the present invention for solving the above-mentioned another technical problem, a display device may include: a display panel; a driving unit that drives the display panel; and a timing controller that includes: a blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal using the clock signal and the gate driving signal, a power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal, and a functional block group that includes a plurality of functional blocks configured to perform operations according to a display period and a blank period in response to the gate driving signal, the data driving signal, and the power-down control signal, and configured to control the operation of the driving unit.
[0015] Advantages of the Invention
[0016] The display device according to the present invention that minimizes power consumption during the blank period as described above has the following advantages: minimizing the power required to drive the display panel by operating the functional blocks themselves and / or storage devices (memory cells) related to the functional blocks that typically consume power during the display period but do not need to operate during the blank period in the power-down mode. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 is an embodiment of a timing controller that minimizes power consumption during the blank period according to the present invention.
[0018] Figure 2 is a timing diagram of an operation mode according to the type of the display panel of the display panel.
[0019] Figure 3 Illustrates waveforms of a plurality of power-down control signals applied to a display panel that does not provide a touch panel function.
[0020] Figure 4 Illustrates waveforms of a plurality of power-down control signals applied to an AIT (VBS) display panel.
[0021] Figure 5 Illustrates waveforms of a plurality of power-down control signals applied to an AIT (LHB) display panel.
[0022] Figure 6 Illustrates waveforms of an operation control signal and a power-down control signal of a CABC unit that constitutes a driving unit for driving a display panel that does not provide a touch panel function. DETAILED DESCRIPTION
[0023] Figure 1This is an example of a timing controller that minimizes power consumption during blank periods according to the present invention.
[0024] Reference Figure 1 , a timing controller 100 that minimizes power consumption during blank periods according to the present invention includes a blank period detection circuit 110, a power-down control signal generation circuit 120, and a functional block group 130 including a plurality of functional blocks.
[0025] The timing controller 100 uses a clock signal recovery circuit (not shown) to recover a clock signal (CLK), a gate drive signal (Gate_D), and a data drive signal (DATA_D) from a control signal (CON) received from an external system (not shown).
[0026] The blank period detection circuit 110 uses the clock signal (CLK) and the gate drive signal (Gate_D) to generate a blank period detection signal (BLANK_Dur). If the display period is a period during which a source signal is sent to the display, the blank period is a period during which the source signal is not sent to the display, and this will be described in detail later.
[0027] The blank period detection signal (BLANK_Dur) is a signal that is inactive during the display period and active during the blank period. Here, the activation of the blank period detection signal (BLANK_Dur) means that the blank period detection signal (BLANK_Dur) maintains a voltage level indicating an inactive state and transitions to a voltage level indicating an active state. For example, when the blank period detection signal (BLANK_Dur) has a logical low value, it is determined as the display period, and when it transitions to a logical high value, it is determined as the blank period.
[0028] The blank period detection circuit 110 according to the present invention accurately generates the blank period detection signal (BLANK_Dur) by using the clock signal (CLK) and the gate drive signal (Gate_D) so that it is synchronized with the clock signal (CLK). For example, by using a logic circuit such as a NAND gate, the blank period detection signal (BLANK_Dur) synchronized with the clock signal (CLK) can be generated by using the clock signal (CLK) and the gate drive signal (Gate_D).
[0029] The power-down control signal generation circuit 120 generates a plurality of power-down control signals (BIST mem_pd, CABC mom_pd, Block1 mem_pd) in response to a blank period detection signal (BLANK_Dur), so that each of the plurality of functional blocks included in the functional block group 130 operates in one of a normal operation mode and a power-down mode, or so that the memory devices included in the plurality of functional blocks operate in one of a normal operation mode and a power-down mode.
[0030] Preferably, a plurality of power-down control signals (BIST mem_pd, CABC mom_pd, Block1 mem_pd) are generated for each of the plurality of functional blocks included in the functional block group 130. For example, the power-down control signal BIST mem_pd indicates whether a memory device (not shown) included in the BIST execution unit 131 described below operates in the power-down mode.
[0031] The functional block group 130 includes a plurality of functional blocks, and may include, for example, a BIST execution unit 131, CABC 132, DGA 133, DITHER 134, an image quality IP 135, and a plurality of other functional blocks 136 to 138.
[0032] When operating in the display mode, the gate drive signal (Gate_D) must be activated, and when operating in the blank mode, the gate drive signal (Gate_D) must be deactivated. The present invention proposes to use the blank period detection circuit 110 to generate a blank period detection signal (BLANK_Dur) that is activated and deactivated in response to the display mode and the blank mode, respectively, according to the state of the gate drive signal (Gate_D).
[0033] Here, the normal operation mode refers to a state in which the plurality of functional blocks included in the functional block group 130 and the memory devices included in the functional blocks execute their assigned functions while consuming a certain amount of power, and the power-down mode refers to an operation state in which the power consumption is minimized by preventing a specific functional block from operating.
[0034] The normal operation mode may be an operation state in the active section or the display section, and the power-down mode may be an operation state in the blank section. That is, in the display section operating in the normal operation mode, the plurality of functional blocks constituting the functional block group 130 execute normal functions according to the state of the blank section detection signal (BLANK_Dur), or cause at least one of the functional blocks 131 to 138 to operate in an idle state, or minimize the power consumption of the storage device included in the corresponding functional block.
[0035] There are various methods for consuming minimum power in the power-down mode. For example, power supply to all or a part of the relevant functional blocks is cut off, or the circuit is configured to shift the output voltage level of a specific circuit stage constituting the functional block to the power-down mode voltage level so that the subsequent-stage circuits electrically connected to the stage outputting the power-down mode voltage level do not operate. This also applies to the memory devices included in the relevant functional blocks so that the memory devices included in the relevant functional blocks consume minimum power.
[0036] Figure 1 The functional blocks included in the illustrated functional block group 130 are interpreted as examples, and the technology of the present invention is not limited thereto. However, for the purpose of helping to understand this technology, Figure 1 The functions of the illustrated functional blocks are explained as follows.
[0037] The BIST execution unit 131 is a functional block that can execute the function of testing for defects between memory cells using a built-in self-test (BIST) circuit.
[0038] The CABC 132 executes a content-based adaptive control (CABC: content-based adaptive brightness control) function, which analyzes the original image data to adjust the set gamma curve value and adjusts the brightness of the backlight (LED) to improve the energy efficiency of power consumption.
[0039] The digital gamma control unit 133 generates positive gamma voltages and negative gamma voltages with different values through a plurality of gamma blocks (not shown), and generates gamma voltages according to 256 gray levels.
[0040] The DITHER unit 134 performs dithering on the image data played on a display (not shown).
[0041] The image quality IP 135 is an image processing processor (image processor) for improving the image quality of a display panel (not shown).
[0042] The other functional blocks 136-138 are examples of functional blocks that can be added by the designer of the timing controller 100 as needed.
[0043] The above-mentioned multiple functional blocks 131-138 have their own storage devices necessary for executing corresponding functions or utilize separate storage devices, and the test in the BIST execution unit 131 tests for defects between the storage devices (i.e., memory cells) associated with the multiple functional blocks 132-135.
[0044] In addition to the simple function of playing back images, the operation of the display panel can also provide a means for receiving user touch information. Depending on whether the display panel only plays back images and whether the display panel concurrently executes the function of receiving touch information, the operation of the display panel can be distinguished as follows.
[0045] According to the configuration, display touch panels can be classified into add-on mode touch panels, on-cell touch panels, and in-cell touch panels. Specifically, in-cell touch panels have the following advantages: allowing the display module to be thinner, and significantly reducing the production cost of the touch panel since the touch electrodes of the touch panel are embedded inside the display panel.
[0046] Figure 1 Each of the functional blocks included in the functional block group 130 shown can be a semiconductor IP that implements a circuit or chip layout design, which has an independent function and can be reused. When designing a system-on-chip (SoC) and a field-programmable gate array (FPGA) circuit, a microprocessor, a memory, a digital signal processor, an analog signal processor, and various input / output circuits can be examples of semiconductor IP.
[0047] Figure 2 is a timing diagram of the operation mode according to the type of the display panel of the display panel.
[0048] The display panel can be classified into a display panel that only plays images (non-AIT) and an advanced in-cell touch (AIT) panel (AIT(VBS) and AIT(LHB)). Here, VBS is an abbreviation for vertical blank stretch, and LHB is an abbreviation for long horizontal blank.
[0049] Reference Figure 2 , in the case of a display panel that does not provide a touch panel function (non-AIT), the blank period (blank) per frame is less than 5%, while in the case of an AIT display panel (AIT(VBS), AIT(LHB)), the display period:blank period ratio is approximately 5:5 to 8:2.
[0050] Since the power consumption of the timing controller of the present invention is minimized during the blank period, the effect of the present invention is better when applied to an AIT display panel (AIT(VBS), AIT(LHB)) than when applied to a display panel that does not provide a touch panel function (non-AIT).
[0051] The present invention describes a plurality of power-down control signals (BIST mem_pd, CABC mom_pd, Block1mem_pd), which adaptively correspond to Figure 2 each of the three types of display modes shown, as described below.
[0052] Figure 3Illustrates the waveforms of a plurality of power-down control signals applied to a display panel that does not provide a touch panel function.
[0053] Figure 4 Illustrates the waveforms of a plurality of power-down control signals applied to an AIT (VBS) display panel.
[0054] Figure 5 Illustrates the waveforms of a plurality of power-down control signals applied to an AIT (LHB) display panel.
[0055] Reference Figures 3 to 5 , it can be seen that the timing controller 100 according to the present invention operates in the same manner as a conventional display device during the display period (display), but operates the memory devices of the function blocks that do not need to operate among the plurality of function blocks included in the function block group 130 in a power-down mode during the blank period (blank), thereby minimizing the power consumption during the blank period (blank).
[0056] The above-mentioned technology of the present invention minimizes the power consumption during the blank period (blank) by deactivating the memory devices included in the function blocks that do not need to operate during the blank period (blank). However, depending on the implementation, the power consumption during the blank period (blank) can be further reduced by deactivating the operations of the circuits included in the corresponding function blocks.
[0057] For example, in order to operate the circuit of the function block including the memory device determined to operate in the power-down mode, it can be achieved by cutting off the power supply to the relevant function block, or when the relevant function block is divided into multiple stages, shifting the voltage of the output of the frontmost stage to limit the operation of the subsequent stages.
[0058] In addition, the clock signal supplied to the relevant function block is deactivated during the blank period. For example, this can be achieved by the following operation: maintaining a specific voltage level during the blank period of the clock signal operating at a certain period so that it acts like a DC voltage rather than a clock signal during the blank period.
[0059] Figure 6 Illustrates the waveforms of the operation control signal and the power-down control signal of the CABC that constitutes the driving unit for driving a display panel that does not provide a touch panel function.
[0060] The first waveform (Clock_CABC(no)) according to the above is the clock signal supplied to the internal circuit of the conventional CABC 132 when the present invention is not applied, the second waveform (Clock_CABC(yes)) according to the above is the clock signal supplied to the internal circuit of the CABC 132 when the present invention is applied, and the third waveform (CABC mem_pd) according to the above represents the power-down control signal that determines the operation of the internal memory device of the CABC 132 when the present invention is applied.
[0061] Reference Figure 6 , the conventional display device without applying the present invention supplies a clock signal (Clock_CABC) during the display period (display) and the blank period (blank). However, the timing controller 100 applying the present invention supplies a clock signal (Clock_CABC) in the same manner as the conventional display device during the display period (display), but the difference is that it deactivates the clock signal during the blank period (blank).
[0062] Specifically, it can be seen that the timing controller 100 applying the present invention allows the memory device included in the CABC 132 to perform the normal function of the storage device during the display period (display), but causes the memory device included in the CABC 132 to operate in the power-down mode during the blank period (blank).
[0063] For simplicity of explanation, among multiple display playback modes, Figure 6 a display panel without a touch panel function is used as an example, but this can also be applied to an AIT display panel.
[0064] Specifically, the multiple clock signals supplied to each functional block (for example, the clock signal (Clock_CABC(yes)) supplied to the CABC 132) are related to the power-down control signal output from the power-down control signal generation circuit 120, so it can be generated by using the logical combination of the existing clock signal (Clock_CABC(no)) and multiple power-down control signals (BISTmem_pd, CABC mom_pd, Block1 mem_pd).
[0065] The clock signal (Clock_CABC(yes)) supplied to the CABC 132 can be generated by the power-down control signal generation circuit 120, or it can be generated using a separate functional block.
[0066] Specifically, the power-down control signal generation circuit 120 can generate the power-down control signal and the clock signal simultaneously, but it can also generate the power-down control signal and the clock signal separately.
[0067] For example, a power-down control signal can be generated only to operate memory cells only in the power-down mode, a clock signal can be generated only to operate corresponding functional blocks only in the power-down mode, and both the power-down control signal and the clock signal can be generated to operate both the functional blocks and the corresponding memory cells in the power-down mode.
[0068] Industrial applicability
[0069] The display device that minimizes power consumption during a blank period according to the present invention operates, in the power-down mode, functional blocks that normally consume power during a display period but do not need to operate during the blank period and / or storage devices (memory cells) associated with the corresponding functional blocks, thereby minimizing the power required to drive the display panel, and thus has industrial applicability in the field of display technology, particularly in the field of timing controllers.
Claims
1. A timing controller that recovers clock signals, gate drive signals, and data drive signals using control signals received from an external system and minimizes power consumption during blank periods, the timing controller comprising: A blank period detection circuit configured to generate a blank period detection signal using the clock signal and the gate drive signal; And A functional block group including a plurality of functional blocks configured to perform operations according to a display period and the blank period in response to the gate drive signal, the data drive signal, and the blank period detection signal.
2. The timing controller according to claim 1, wherein, The blank period detection signal remains inactive during the display period and transitions to an active state during the blank period.
3. The timing controller according to claim 1, wherein, The plurality of functional block groups are at least one of the following: A built-in self-test (BIST) execution unit that performs the function of testing for defects between memory cells using a BIST circuit; Content-adaptive brightness control (CABC) that performs the CABC function; A digital gamma control unit configured to generate positive and negative gamma voltages with different values through a plurality of gamma blocks; A DITHER unit configured to perform dithering on image data reproduced on a display panel; and Image quality IP that is an image processor for improving the quality of the display panel.
4. The timing controller according to claim 3, wherein, Each of the plurality of functional blocks included in the functional block group includes a memory unit for signal processing, wherein the memory unit included in at least one of the plurality of functional blocks operates in a power-down mode during the blank period.
5. The timing controller according to claim 4, wherein, The memory unit has the BIST execution unit, the CABC, the digital gamma control unit, the DITHER unit, and the image quality IP itself or as a separate storage device.
6. A timing controller that recovers clock signals, gate drive signals, and data drive signals using control signals received from an external system and minimizes power consumption during blank periods, the timing controller comprising: A blank period detection circuit that generates a blank period detection signal using the clock signal and the gate drive signal; A power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal; And A functional block group including a plurality of functional blocks configured to perform operations according to a display period and the blank period in response to the gate drive signal, the data drive signal, and the blank period detection signal.
7. The timing controller according to claim 6, wherein, The blank period detection signal includes information for minimizing power consumption during the blank period synchronized with the display period and the clock signal.
8. The timing controller according to claim 7, wherein, The power-down control signal remains inactive during the display period and transitions to an active state during the blank period.
9. A display device that minimizes power consumption during blank periods, the display device comprising: A display panel; A driving unit configured to drive the display panel; And A timing controller, the timing controller comprising: A blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal using the clock signal and the gate driving signal, and A functional block group including a plurality of functional blocks configured to perform operations according to a display period and the blank period in response to the gate driving signal, the data driving signal, and the blank period detection signal, and configured to control the operation of the driving unit.
10. A display device, the display device comprising: A display panel; A driving unit that drives the display panel; And A timing controller, the timing controller comprising: A blank period detection circuit configured to recover a clock signal, a gate driving signal, and a data driving signal using a control signal received from an external system and generate a blank period detection signal, A power-down control signal generation circuit configured to generate a power-down control signal using the blank period detection signal, and A functional block group including a plurality of functional blocks configured to perform operations according to a display period and the blank period in response to the gate driving signal, the data driving signal, and the power-down control signal, and configured to control the operation of the driving unit.