Storage module, storage system and electronic system

Abstract

The invention discloses a storage module, a storage system and an electronic system. The storage module comprises a CXL controller and N heterogeneous dual in-line memory modules, wherein N is greater than 1; the CXL controller comprises a memory driving module, and the memory driving module is connected with N heterogeneous dual in-line memory modules through memory interfaces; the heterogeneous dual in-line memory module comprises a dual in-line interface, a dynamic random access memory, a control unit and a nonvolatile memory; the dynamic random access memory is connected with the memory interface through a dual in-line interface and is used for storing an access command; the control unit is connected with the dual in-line interface, the dynamic random access memory and the nonvolatile memory; the control unit controls data transfer between the dynamic random access memory and the nonvolatile memory according to the access command. The invention provides a scheme capable of realizing both capacity expansion and universal standard interface adaptation.

Description

Technical Field

[0001] The present invention relates to the field of electronic technologies, and particularly to a storage module, a storage system, and an electronic system. Background Art

[0002] With the development of electronic technologies, the demand for memory capacity in various electronic products is increasing day by day.

[0003] In view of the general demand, existing open industry standard interconnect (Compute Express Link, CXL) modules use the standard double data rate (DDR) interface defined by JEDEC to externally connect memories to increase capacity. However, the capacity and bandwidth of the dynamic random access memory (DRAM) connected by the DDR interface are both limited, making it difficult to meet the demand for capacity expansion. Moreover, the cost of stacked DRAM particles prepared based on the through-silicon via (TSV) stacking technology between boards is relatively high, posing challenges to large-scale applications. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a storage module, a storage system, and an electronic system that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, a storage module is provided, which is characterized by comprising: a CXL controller and N heterogeneous dual in-line memory modules, where N is greater than 1; the CXL controller includes a memory driving module, and the memory driving module is connected to the N heterogeneous dual in-line memory modules through a memory interface; the heterogeneous dual in-line memory module includes: a dual in-line interface, a dynamic random access memory, a control unit, and a non-volatile memory; wherein, the dynamic random access memory is connected to the memory interface through the dual in-line interface and is used for storing the access commands issued by the CXL controller; wherein, the control unit is connected to the dual in-line interface, the dynamic random access memory, and the non-volatile memory; the control unit controls the data transfer between the dynamic random access memory and the non-volatile memory according to the access commands.

[0006] Optionally, the dynamic random access memory includes a data area and a command area, the data area is used for storing cached data, and the command area is used for storing the access commands issued by the CXL controller.

[0007] Optionally, both the dual in-line interface and the memory interface are standard double data rate interfaces.

[0008] Optionally, the dynamic random access memory serves as a cache unit controlled by the memory drive module, and the control unit is further configured to upload the storage capacity information of the non-volatile memory to the CXL controller.

[0009] Optionally, during a transfer period, the control unit controls data transfer between the dynamic random access memory and the non-volatile memory; wherein, the transfer period is within the address refresh cycle of the dynamic random access memory, and the address refresh cycle is a preset cycle period for performing a refresh operation on the dynamic random access memory; within the address refresh cycle, the CXL controller stops performing data operations on the dynamic random access memory.

[0010] Optionally, within each maximum refresh interval cycle of the dynamic random access memory, it is divided into an address refresh cycle and a CXL controller operable cycle; within the address refresh cycle, it is divided into a refresh execution period and an extended period, and the refresh execution period is a period for performing the refresh operation, and the transfer period is within the extended period.

[0011] Optionally, the control unit is further configured to read an access command stored in the dynamic random access memory; when the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory; when the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the CXL controller to read.

[0012] Optionally, the dual in-line interface, the dynamic random access memory, the control unit, and the non-volatile memory are all stacked using three-dimensional heterogeneous stacking technology to form the heterogeneous dual in-line memory module with a three-dimensional structure.

[0013] In a second aspect, a storage system is provided, including: a CXL converter and any one of the storage modules in the first aspect, where M>1; the CXL converter includes a plurality of CXL interfaces for connecting M storage modules.

[0014] In a third aspect, an electronic system is provided, including: a main control device and any one of the storage modules in the first aspect; the main control device is connected to the CXL controller of the storage module through a CXL interface.

[0015] In a fourth aspect, an electronic system is provided, comprising: a main control device and the storage system described in the second aspect; the main control device is connected to the CXL converter of the storage system via a CXL interface.

[0016] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage module, storage system and electronic system provided by the embodiment of the present invention are provided with a memory driver module added to the CXL controller of the storage module, and the DRAM in the heterogeneous dual in-line memory module (DIMM) is provided to store the access command issued by the memory driver module, and the control unit controls the data transfer between the DRAM and the non-volatile memory according to the access command, so the memory driver module does not need to be connected to other types of memory and perform data transmission, and only needs to control the DRAM to achieve data access, so the connection between the CXL controller and the heterogeneous DIMM can be achieved based on the standard DDR interface, and the versatility is strong. Further, based on the extended function of the CXL controller, multiple heterogeneous DIMMs can be connected through multiple standard DDR interfaces, thereby taking into account the versatility of the DDR interface and the capacity expansion of the storage module. Furthermore, a CXL converter is also provided to connect multiple aforementioned storage modules through multiple CXL interfaces, further realizing an ultra-large capacity memory storage system.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings: Figure 1 Schematic diagram of the structure of a storage module in an embodiment of the present invention; Figure 2 The structure of the heterogeneous dual in-line memory module in the embodiment of the present invention is shown in FIG. Figure 1 ; Figure 3 A schematic diagram of the structure of a dynamic random access memory in an embodiment of the present invention; Figure 4 A schematic diagram of a refresh timing of a dynamic random access memory in an embodiment of the present invention; Figure 5Schematic structure of the heterogeneous dual in-line memory module in the embodiment of the present invention Figure 2 ; Figure 6 Schematic structure diagram of the storage system in the embodiment of the present invention; Figure 7 Schematic structure diagram of the electronic system in the embodiment of the present invention; Figure 8 Schematic structure diagram of the electronic system in the embodiment of the present invention. Detailed implementation manners

[0019] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0020] Various schematic structure diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0021] Please refer to Figure 1 and Figure 2 , an embodiment of the present application provides a storage module, as Figure 1 shown, including: a CXL controller 1 and N heterogeneous dual in-line memory modules 2, where N is greater than 1. The CXL controller 1 includes a memory driving module 11, and the memory driving module 11 is connected to the N heterogeneous dual in-line memory modules 2 through a memory interface 12.

[0022] The heterogeneous dual in-line memory module 2 is as Figure 2 shown, including: a dual in-line interface 21, a dynamic random access memory 22, a control unit 23, and a non-volatile memory 24. The dynamic random access memory 22 is connected to the memory interface 12 through the dual in-line interface 21 and is used to store the access commands issued by the CXL controller 1. Among them, the control unit 23 is connected to the dual in-line interface 21, the dynamic random access memory 22, and the non-volatile memory 24. The control unit 23 controls the data transfer between the dynamic random access memory 22 and the non-volatile memory 24 according to the access commands.

[0023] It should be noted that a memory driving module 11 is set in the CXL controller 1. Through the memory driving module 11, access control and management of the dynamic random access memory 22 in the heterogeneous dual in-line memory module 2 can be realized. Combining with the expansion performance of the CXL controller 1, the CXL controller 1 can be connected to multiple heterogeneous dual in-line memory modules 2 to realize capacity expansion.

[0024] Moreover, by setting that the dynamic random access memory 22 is connected to the CXL controller 1 through a dual in-line interface 21, and the dynamic random access memory 22 is controlled for access by the memory driving module 11, while the non-volatile memory 24 is not directly accessed by the memory driving module 11. The access commands issued by the memory driving module 11 are all stored in the dynamic random access memory 22 (the access commands can be sent by a master device such as a CPU or a motherboard to the CXL controller 1, and then forwarded by the memory driving module 11 to the dynamic random access memory 22). The control unit 23 controls the data transfer between the dynamic random access memory 22 and the non-volatile memory 24 according to the access commands. Thus, the memory driving module 11 does not need to be connected to the non-volatile memory 24 and perform data transmission to realize data writing and reading. Therefore, the memory interface 12 of the CXL controller 1 and the dual in-line interface 21 of the heterogeneous dual in-line memory module 2 can both be standard DDR interfaces defined by JEDEC, and no adaptation modification is required. The CXL controller 1 can be connected to the heterogeneous dual in-line memory module 2 based on the standard DDR interface, taking into account the general requirements and capacity expansion requirements.

[0025] Furthermore, considering the current mainstream Non-volatile dualin-line memory module (NVDIMM), after the NVDIMM-N is connected to the CXL controller 1, the CXL controller 1 can only recognize the storage capacity of its DRAM by default, and the storage capacity of its flash memory (Negative-AND Flash Memory, NAND) cannot be recognized, thus affecting the overall capacity of the system. For NVDIMM-F and NVDIMM-P, since their non-volatile memories need to be connected to the interface, they cannot be directly connected to the standard DDR interface, and the interface needs to be adapted and modified, resulting in poor versatility. In the embodiment of the present application, the dynamic random access memory 22 can also be set as the cache unit controlled by the memory drive module 11, and the control unit 23 is further configured to upload the storage capacity information of the non-volatile memory 24 to the CXL controller 1. Therefore, the memory drive module 11 can use the non-cache as the storage capacity it recognizes, so that the capacity of the non-volatile memory 24 can be obtained and recognized through the control unit 23 as the storage capacity of the storage module, taking into account the requirements of storage capacity recognition and adaptation to the general standard DDR interface.

[0026] Next, the structure of the heterogeneous dual in-line memory module 2 will be introduced in detail.

[0027] As Figure 2 shown, the heterogeneous dual in-line memory module 2 includes: a dual in-line interface 21, a dynamic random access memory 22, a control unit 23, and a non-volatile memory 24. The dynamic random access memory 22 is connected to the CXL controller 1 through the dual in-line interface 21 and is used to store the access commands issued by the CXL controller 1. Among them, the control unit 23 is connected to the dual in-line interface 21, the dynamic random access memory 22, and the non-volatile memory 24. The control unit 23 controls the data transfer between the dynamic random access memory 22 and the non-volatile memory 24 according to the access commands.

[0028] In an alternative embodiment, as Figure 3 shown, the dynamic random access memory 22 can be divided into a data area 2201 and a command area 2202. The data area 2201 is used to store cache data, and the command area 2202 is used to store the access commands issued by the CXL controller 1.

[0029] Specifically, the access commands (at least including read commands and write commands) sent by the CXL controller 1 to the heterogeneous dual in-line memory module 2 will be stored in the command area 2202 of the dynamic random access memory 22. The data sent by the CXL controller 1, or the data transferred from the non-volatile memory 24 to the dynamic random access memory 22 by the control unit 23 will be stored as cached data in the data area 2201. Dividing the dynamic random access memory 22 in this way can improve the efficiency of the subsequent control unit 23 in obtaining access commands and transferring data, and can also avoid interference with the storage of cached data when the control unit 23 obtains access commands due to mixed storage, as well as avoid interference with the storage state of access commands when transferring data, effectively ensuring efficiency and reliability.

[0030] In an alternative embodiment, the control unit 23 can read the access commands stored in the dynamic random access memory 22. Specifically, the control unit 23 will read the access commands stored in the dynamic random access memory 22 in a triggered manner (the triggering factor can be detecting that the control device has sent an access command, or receiving a transfer instruction) or periodically, and control the data transfer between the dynamic random access memory 22 and the non-volatile memory 24 according to the access commands.

[0031] For example, when the access command is to write write data to the non-volatile memory 24, the control unit 23 transfers the write data cached in the dynamic random access memory 22 to the non-volatile memory 24.

[0032] Specifically, when the CXL controller 1 sends an access command (the access command carries the address information of the non-volatile memory 24 and the write data) for writing write data to the heterogeneous dual in-line memory module 2, the access command will be stored in the command area 2202 of the dynamic random access memory 22, and the write data carried by the access command will be stored as cached data in the data area 2201 of the dynamic random access memory 22. The control unit 23 accesses the command area 2202 to obtain the unprocessed access command, and transfers the corresponding write data in the data area 2201 to the corresponding address of the non-volatile memory 24 for storage according to the address information carried by the access command. In this way, the CXL controller 1 can accurately write write data without accessing the non-volatile memory 24.

[0033] For another example, when the access command is to read read data from the non-volatile memory 24, the control unit 23 transfers the read data from the non-volatile memory 24 to the dynamic random access memory 22 for the CXL controller 1 to read.

[0034] Specifically, when the CXL controller 1 issues an access command (the access command carries address information) to read read data to the heterogeneous dual in-line memory module 2, the access command will be stored in the command area 2202 of the dynamic random access memory 22. If the address information read by the CXL controller 1 is in the dynamic random access memory 22, the corresponding read data can be directly read from the data area 2201 of the dynamic random access memory 22. If the address information read by the CXL controller 1 is in the non-volatile memory 24, the control unit 23 accesses the command area 2202 to obtain the unprocessed access command, and transfers the read data at the corresponding address of the non-volatile memory 24 to the data area 2201 of the dynamic random access memory 22 for storage according to the address information carried by the access command. Then the CXL controller 1 reads and obtains the read data from the dynamic random access memory 22. In this way, the CXL controller 1 can accurately read the read data without accessing the non-volatile memory 24.

[0035] In an alternative embodiment, after the access command of the CXL controller 1 is executed, the corresponding access command stored in the command area 2202 of the dynamic random access memory 22 can be deleted, so that the control unit 23 only reads the commands that still need to be processed from the command area 2202.

[0036] In an alternative embodiment, as Figure 4 shown ( Figure 4 where the abscissa is time t), the dynamic random access memory 22 needs to be refreshed to maintain the stored data, and the longest time interval for each refresh is the maximum refresh interval period tREFI. The maximum refresh interval period tREFI is the interval between two adjacent refresh commands. Within each maximum refresh interval period tREFI of the dynamic random access memory 22, it is divided into an address refresh period tRFC and a CXL controller operable period. That is to say, the CXL controller 1 will only perform data operations on the dynamic random access memory 22 during the period outside the address refresh period tRFC.

[0037] The control unit 23 controls the data transfer between the dynamic random access memory 22 and the non-volatile memory 24 during the transfer period. The transfer period is within the address refresh period tRFC of the dynamic random access memory 22, and the address refresh period tRFC is a preset cycle period for the dynamic random access memory 22 to perform the refresh operation. During the address refresh period tRFC, the CXL controller 1 stops performing data operations on the dynamic random access memory 22. In this way, performing data transfer between the dynamic random access memory 22 and the non-volatile memory 24 during the address refresh period tRFC can effectively avoid conflicts between data transfer and the data operations of the CXL controller 1, thus ensuring the reliability of the data.

[0038] In an alternative embodiment, it can also be set that within the address refresh period tRFC, it is further divided into a refresh execution period t1 and an extended period t2. The refresh execution period t1 is the period for performing the refresh operation of the dynamic random access memory 22, and the data transfer period between the dynamic random access memory 22 and the non-volatile memory 24 is within the extended period t2. In this way, it can effectively avoid conflicts between data transfer and refresh operations and further ensure the reliability of data.

[0039] In an alternative embodiment, the control unit 23 is further configured to upload the storage capacity information of the non-volatile memory 24 to the CXL controller 1. Since the CXL controller 1 controls the dynamic random access memory 22 as its cache unit rather than the terminal storage unit, the CXL controller 1 does not recognize the capacity of the dynamic random access memory 22 as the storage capacity of the storage module. The control unit 23 uploads the storage capacity information of the non-volatile memory 24 to the CXL controller 1 in a timely manner through the dual in-line interface 21, so that the CXL controller 1 can recognize the real-time storage capacity of the non-volatile memory 24 and use it as the storage capacity of the storage module, thereby enabling a larger-capacity non-volatile storage module.

[0040] In an alternative embodiment, it can be set that the dual in-line interface 21, the dynamic random access memory 22, the control unit 23, and the non-volatile memory 24 are all stacked using three-dimensional heterogeneous stacking technology to form a heterogeneous dual in-line memory module 2 with a three-dimensional structure. For example, the dual in-line interface 21, the dynamic random access memory 22, the control unit 23, and the non-volatile memory 24 can be respectively set on each wafer, and the wafers with the dual in-line interface 21, the wafers with the dynamic random access memory 22, the wafers with the control unit 23, and the wafers with the non-volatile memory 24 are stacked through three-dimensional heterogeneous stacking technology to form a chip of the heterogeneous dual in-line memory module 2 with a three-dimensional structure. Since the interaction between the dual in-line interface 21, the dynamic random access memory 22, the control unit 23, and the non-volatile memory 24 is completed inside the chip, it saves the transmission speed between them and improves the storage access efficiency.

[0041] Please refer to Figure 5 , it can be set that the heterogeneous dual in-line memory module 2 further includes a driving unit 25, connected between the dual in-line interface 21 and the dynamic random access memory 22, for enhancing the strength of the signal sent by the CXL controller 1 to the heterogeneous dual in-line memory module 2. The signal can include one or a combination of an address signal, a clock signal, and a data signal. By re-driving and enhancing the signal through the driving unit 25, the processing efficiency and reliability of the signal can be effectively improved.

[0042] Based on the same inventive concept, an embodiment of the present application further provides a storage system, as Figure 6 shown, including: a CXL converter 601 and M storage modules 602 provided in any one of the foregoing embodiments, where M is greater than 1. The CXL converter 601 includes a plurality of CXL interfaces 603 for connecting the M storage modules 602.

[0043] By setting the CXL converter 601 to carry and connect multiple storage modules 602, the connection between the device and the modules can be expanded to further implement an ultra-large-capacity memory storage system.

[0044] Since the storage module 602 included in the storage system introduced in the embodiment of the present application is exactly the storage module introduced in the foregoing embodiments of the present application, the principle and structure of this storage module have been described in detail above, so it will not be repeated here. Any storage system including the storage module of the embodiment of the present application falls within the scope of protection of the present invention.

[0045] Based on the same inventive concept, an embodiment of the present application further provides an electronic system, as Figure 7 shown, including: a main control device 701 and the storage module 602 provided in any one of the foregoing embodiments. The main control device 701 is connected to the CXL controller 1 of the storage module 602 through the CXL interface 603.

[0046] The main control device 701 may be a CPU or a motherboard, etc. The main control device 701 is further configured to send an access command to the CXL controller 1 of the storage module 602, and the CXL controller 1 forwards the access command to the heterogeneous dual in-line memory module 2, and the access command is stored in the dynamic random access memory. The control unit reads the access command stored in the dynamic random access memory. When the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory. When the access command is to read the read data in the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the CXL controller 1 to read and upload to the main control device 701.

[0047] Based on the same inventive concept, an embodiment of the present application further provides an electronic system, as Figure 8 shown, including: a main control device 701 and the storage system 801 provided in any one of the foregoing embodiments. The main control device 701 is connected to the CXL converter 601 of the storage system 801 through the CXL interface 603.

[0048] The master control device 701 may be a CPU or a motherboard, etc. The master control device 701 is also used to send access commands to the CXL converter 601 of the storage system 801, which is forwarded to the CXL controller of the storage module 602 via the CXL converter 601. The CXL controller forwards the access commands to the heterogeneous dual in-line memory module, and the access commands are stored in the dynamic random access memory. The control unit reads the access commands stored in the dynamic random access memory. When the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory. When the access command is to read the read data in the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory, so that the CXL controller can read and upload the read data to the master control device 701 via the CXL converter 601.

[0049] Since the storage module 602 and / or storage system 801 included in the electronic system introduced in the embodiment of the present application is exactly the storage module and storage system introduced in the previous embodiment of the present application, the principle and structure of the storage module and storage system have been described in detail above, so they will not be repeated here. Any electronic system including the storage module or storage system of the embodiment of the present application belongs to the scope of protection of the present invention.

[0050] The technical solution provided in the embodiments of the present invention has at least the following technical effects or advantages: The storage module, storage system and electronic system provided by the embodiment of the present invention are provided with a memory driver module added to the CXL controller of the storage module, and the DRAM in the heterogeneous dual in-line memory module (DIMM) is provided to store the access command issued by the memory driver module, and the control unit controls the data transfer between the DRAM and the non-volatile memory according to the access command, so the memory driver module does not need to be connected to other types of memory and perform data transmission, and only needs to control the DRAM to achieve data access, so the connection between the CXL controller and the heterogeneous DIMM can be achieved based on the standard DDR interface, and the versatility is strong. Further, based on the extended function of the CXL controller, multiple heterogeneous DIMMs can be connected through multiple standard DDR interfaces, thereby taking into account the versatility of the DDR interface and the capacity expansion of the storage module. Furthermore, a CXL converter is also provided to connect multiple aforementioned storage modules through multiple CXL interfaces, further realizing an ultra-large capacity memory storage system.

[0051] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. A variety of general-purpose systems may also be used in conjunction with the teachings presented herein. The structure required to construct such systems will be apparent from the above description. Additionally, the present invention is not directed to any particular programming language. It should be understood that the teachings of the present invention described herein can be implemented in a variety of programming languages, and the description of specific languages above is provided to disclose the best mode of the present invention.

[0052] In the specification provided herein, numerous specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of the present specification.

[0053] Similarly, it should be understood that, in order to streamline the present disclosure and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together in a single embodiment, figure, or description thereof.

[0054] Those skilled in the art will appreciate that the modules in the devices of the embodiments can be adaptively changed and disposed in one or more devices different from those of the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the abstract and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying abstract and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0055] In addition, those skilled in the art will be able to understand that although some embodiments herein include certain features included in other embodiments but not other features, the combination of the features of different embodiments is meant to be within the scope of the present invention and forms different embodiments.

[0056] It should be noted that the above embodiments are illustrative of the present invention and not restrictive thereof. Any reference signs between parentheses shall not be construed as limiting the invention. The word "comprising" does not exclude the presence of elements or steps not listed in the present invention. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In embodiments listing several means, several of these means can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A storage module, characterized in that, Including: A CXL controller and N heterogeneous dual in-line memory modules, where N is greater than 1; The CXL controller includes a memory driving module, and the memory driving module is connected to the N heterogeneous dual in-line memory modules through a memory interface; The heterogeneous dual in-line memory module includes: a dual in-line interface, a dynamic random access memory, a control unit, and a non-volatile memory; wherein, the dynamic random access memory is connected to the memory interface through the dual in-line interface and is used to store the access commands issued by the CXL controller; Wherein, the control unit is connected to the dual in-line interface, the dynamic random access memory, and the non-volatile memory; the control unit controls the data transfer between the dynamic random access memory and the non-volatile memory according to the access command.

2. The storage module according to claim 1, wherein The dynamic random access memory includes a data area and a command area, the data area is used to store cache data, and the command area is used to store the access commands issued by the CXL controller.

3. The storage module according to claim 1, wherein: Both the dual in-line interface and the memory interface are standard double data rate interfaces; The dynamic random access memory serves as a cache unit controlled by the memory driving module, and the control unit is further used to upload the storage capacity information of the non-volatile memory to the CXL controller.

4. The storage module according to claim 1, wherein: The control unit controls the data transfer between the dynamic random access memory and the non-volatile memory during a transfer period; Wherein, the transfer period is within the address refresh cycle of the dynamic random access memory, and the address refresh cycle is a preset cycle period for performing a refresh operation on the dynamic random access memory; within the address refresh cycle, the CXL controller stops performing data operations on the dynamic random access memory.

5. The storage module according to claim 4, wherein: Within each maximum refresh interval cycle of the dynamic random access memory, it is divided into the address refresh cycle and the CXL controller operable cycle; within the address refresh cycle, it is divided into a refresh execution period and an extended period, and the refresh execution period is the period for performing the refresh operation, and the transfer period is within the extended period.

6. The storage module according to claim 1, wherein: The control unit is further used to read the access commands stored in the dynamic random access memory; When the access command is to write write data to the non-volatile memory, the control unit transfers the write data cached in the dynamic random access memory to the non-volatile memory; When the access command is to read read data from the non-volatile memory, the control unit transfers the read data from the non-volatile memory to the dynamic random access memory for the CXL controller to read.

7. The storage module according to claim 1, wherein: The dual in-line package interface, the dynamic random access memory, the control unit, and the non-volatile memory are all stacked using three-dimensional heterogeneous stacking technology to form the heterogeneous dual in-line memory module with a three-dimensional structure.

8. A storage system, characterized in that, Comprising: A CXL converter and M storage modules as described in any one of claims 1 to 7, where M is greater than 1; The CXL converter includes a plurality of CXL interfaces for connecting the M storage modules.

9. An electronic system, characterized in that, Comprising: A master device and a storage module as described in any one of claims 1 to 7; The master device is connected to the CXL controller of the storage module through a CXL interface.

10. An electronic system, characterized in that, Comprising: A master device and the storage system as described in claim 8; The master device is connected to the CXL converter of the storage system through a CXL interface.

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