PI-free high-speed serial port transmitter clock distribution network

Abstract

A high-speed serial port transmitter clock distribution network without a phase interpolator (PI) is characterized in that a multi-phase clock generation module generates a four-phase high-speed clock, and the four-phase high-speed clock is subjected to frequency division to generate a multi-stage clock; a four-phase clock phase converter dynamically selects a reference phase and reconstructs a phase sequence, and drives a two-stage combiner: the first stage compensates data path delay by using frequency division clock delay, and the second stage reconstructs a time sequence based on a high-speed clock, and synchronizes a sampling window through non-overlapping unit pulses; and the phase locking module calculates a clock-data phase difference in real time in combination with a theoretical model, dynamically configures phase logic, and realizes cross-clock-domain accurate alignment. Under a 12nm FinFET process, through four-phase clock phase conversion, time sequence violation caused by PVT disturbance can be effectively suppressed without PI, and simulation verification shows that the area and the power consumption of the device are remarkably optimized compared with those of a traditional scheme. The method can be expanded to various scenes needing clock phase adjustment, and a low-complexity and high-energy-efficiency clock network solution is provided for an advanced process.

Description

Technical Field

[0001] The present invention relates to the field of high-speed digital integrated circuit design, and particularly to a clock distribution network for a high-speed serial transmitter without a phase interpolator (PI). Background Art

[0002] There are delay differences between the data path and the clock path of a high-speed serial transmitter, resulting in the actual sampling point in the circuit deviating from the ideal sampling point (usually the exact middle of the data) guaranteed by the phase margin. With the continuous development of semiconductor technology and the increasing advancement of the process technology, the data rate that needs to be processed by the high-speed serial port is gradually increasing, resulting in a gradual reduction of the phase margin in the entire data path of the high-speed serial transmitter in units of the minimum UI, a gradual decrease in the proportion in the total timing margin, and an increasing influence of the delay mismatch on the combined sampling point. If not carefully considered and controlled, it will lead to timing violations. A relatively traditional method is to use a phase interpolator (PI) in conjunction with a complex adaptive algorithm for high-precision phase adjustment. For example, the patent CN118138019A adopts this solution and has achieved relatively good results in the 65nm process. However, in more advanced processes, this traditional method will bring additional circuit power consumption and area overhead. Especially in advanced processes below 28nm, the power consumption and area overhead brought by using a PI will account for an increasingly large proportion of the total circuit.

[0003] It should be noted that the information disclosed in the above background art section is only used for understanding the background of the present application, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The main purpose of the present invention is to overcome the defects existing in the above background art, and provide a clock distribution network for a high-speed serial transmitter without a PI.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A clock distribution network for a high-speed serial transmitter without a PI, comprising:

[0007] A multi-phase clock generation module, configured to generate a four-phase high-speed clock signal and generate a multi-stage divided clock based on a reference phase through a frequency divider;

[0008] A four-phase clock phase converter, connected to the multi-phase clock generation module, configured to dynamically select a target phase among the four-phase clocks as the reference phase and reorder the remaining phases to generate a clock sequence with reconfigurable phases;

[0009] A multi-stage combiner control module, comprising:

[0010] a. The first-stage combiner is driven by the divided clock, and a fixed clock sequence controls data sampling and combining timing;

[0011] b. The second stage combiner is driven by the high-speed clock and completes high-speed data combining based on the reordered clock sequence;

[0012] The unit pulse generator is linked with the four-phase clock phase converter to generate non-overlapping pulse signals to complete the circuit combining action.

[0013] The present invention has the following beneficial effects:

[0014] The main technical advantage of the present invention is that the power consumption and area overhead of the clock distribution network of the high-speed serial port transmitter are significantly optimized under advanced processes through the innovative phase-free interpolator (PI) design. The traditional solution relies on high-precision PI and complex adaptive algorithms to adjust the clock phase. Although it is effective in mature processes (such as 65nm), the power consumption and area share are greatly increased due to the additional circuits of the PI module in advanced processes below 28nm. In response to this problem, the present invention proposes an open-loop control architecture based on four-phase clock phase conversion technology, which dynamically selects the reference phase in the four-phase clock and reconstructs the clock sequence to achieve phase alignment across clock domains, and combines the multi-stage combiner control module with the unit pulse generator to accurately compensate for the delay difference between the data path and the clock path. In the actual design under the 12nm FinFET process, the scheme uses the inherent phase resources of the four-phase clock, verifies the fixed phase difference calculation of the clock-data path through the theoretical model, and dynamically configures the sampling window to eliminate timing violations. Finally, the anti-PVT (process, voltage, temperature) disturbance capability comparable to the traditional scheme is achieved without the need for PI. In addition, by minimizing clock load matching and simplifying phase lock logic, the circuit complexity is greatly reduced and the scalability of the design is improved. Simulation verification shows that this technology is not only suitable for high-speed serial port transmitters, but can also be extended to all application scenarios that require clock phase adjustment to meet the timing requirements of D flip-flops, providing an efficient solution for low-power, high-density integrated circuit design under advanced processes.

[0015] Other beneficial effects of the embodiments of the present invention will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is an architecture diagram of a transmitter (TX) according to an embodiment of the present invention.

[0017] Figure 2 4 is a theoretical timing diagram of a clock network according to an embodiment of the present invention.

[0018] Figure 3 This is an actual timing diagram of the clock network according to an embodiment of the present invention.

[0019] Figure 4 Area comparison of the embodiments of the present invention.

[0020] Figure 5 Power consumption comparison of the embodiments of the present invention. Detailed implementation manners

[0021] The following makes a detailed description of the implementation manners of the present invention. It should be emphasized that the following description is merely exemplary and not intended to limit the scope of the present invention and its applications.

[0022] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element. In addition, the connection can be for a fixing function or for a coupling or communicating function.

[0023] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0024] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0025] Refer to Figure 1, an embodiment of the present invention provides a high-speed serial transmitter clock distribution network without a phase interpolator (PI), including: a multi-phase clock generation module for generating a four-phase high-speed clock signal and generating multi-stage divided clocks based on a reference phase through a frequency divider; a four-phase clock phase converter connected to the multi-phase clock generation module for dynamically selecting a target phase among the four-phase clocks as the reference phase and reordering the remaining phases to generate a phase-reconfigurable clock sequence; a multi-stage multiplexer control module including: a. a first-stage multiplexer driven by the divided clock to control data sampling and multiplexing timing through a fixed-phase clock sequence; b. a second-stage multiplexer driven by the high-speed clock to complete high-speed data multiplexing based on the reordered clock sequence; a unit pulse generator linked with the four-phase clock phase converter to generate non-overlapping pulse signals to complete the multiplexing operation; in this clock distribution network, the four-phase clock output by the multi-phase clock generation module is generated into multi-stage clock signals through a frequency divider and input to the four-phase clock phase converter for phase reordering; the phase-locked control module dynamically selects the reference phase according to the theoretical model, so that the non-overlapping pulses generated by the unit pulse generator precisely control the sampling window of the multi-stage multiplexer; the first-stage multiplexer compensates for the data path delay with the delayed phase of the divided clock, and the second-stage multiplexer eliminates timing violations through phase reconstruction of the high-speed clock, and finally realizes the stable output of high-speed serial data under the condition of no PI.

[0026] In some embodiments, the multi-phase clock generation module includes a frequency divider that performs frequency division by 4 based on the 2_180 phase of the high-speed clock, generating a low-speed clock 1 including phases 1_0, 1_90, 1_180, and 1_270, and there is a fixed phase difference td1 between the frequency divider and the 2_0 phase of the high-speed clock 2.

[0027] In some embodiments, the phase selection logic of the four-phase clock phase converter is configured to: select any one of the four-phase clocks as the new reference phase, and the remaining phases are cyclically arranged in the original order to form a continuous clock sequence with a phase offset of 90°.

[0028] In some embodiments, the width of the pulse signal generated by the unit pulse generator is 1 / 4 of the corresponding clock period, and a non-overlapping protection interval is set between adjacent pulses, and the pulse signal directly drives the multi-stage multiplexer.

[0029] In some embodiments, the sampling clock of the first-stage multiplexer uses the 1_180 phase of the divided clock, which is delayed by T / 2 cycles relative to the data source control clock 1_0, so that the setup time t of the data path c-q1 meets the sampling requirements.

[0030] In some embodiments, the phase-locked control module calculates the model T d =td1 +T1 / 2 + t c-q2 +t c-q3 Determine the reference phase selection of the second - stage combiner, where t c-q2 is the sampling delay of the first - stage combiner, and t c-q3 is the output delay of the first - stage combination.

[0031] In some embodiments, the second - stage combiner integrates a 1UI generator.

[0032] In some embodiments, the multi - phase clock generation module includes a four - phase high - speed clock, which is the reference clock for the second level, and its initial phases are 2_0, 2_90, 2_180, and 2_270.

[0033] In some embodiments, the phase selection operation of the four - phase clock phase converter is performed at most 3 times, and the timing margin is optimized by traversing the non - reference phases in the four - phase clock.

[0034] In some embodiments, it further includes an SPI configuration interface for dynamically setting the initial reference phase selection parameters of the four - phase clock phase converter and the guard interval width of the unit pulse generator.

[0035] In view of the problems of high power consumption, large area overhead, and design complexity caused by traditional phase interpolators (PIs) and adaptive algorithms in the clock distribution network of high - speed serial transmitters under advanced processes, the present invention proposes an innovative solution based on four - phase clock phase conversion technology. Under the 12nm FinFET process, this technology successfully realizes the co - serialization operation with the transmitter data path through a PI - free open - loop control architecture, significantly optimizing the circuit performance. Compared with the PI - combined with adaptive loop scheme in the background technology CN118138019A, the present invention can dynamically reconstruct the clock sequence and flexibly adjust the phase of the sampling points of the combiner only by relying on the four - phase clock (2_0, 2_90, 2_180, 2_270) in the existing 1 / 4 - rate architecture through theoretical modeling and deep utilization of four - phase clock resources, so as to offset the impact of process, voltage, and temperature (PVT) perturbations on timing. Specifically, the four - phase clock phase conversion technology dynamically selects the reference phase and circularly arranges the remaining phases, combines with the unit pulse generator to generate non - overlapping control signals, and precisely matches the sampling windows of multi - stage combiners; the four - phase clock minimum load matching technology reduces the phase offset error by optimizing the load distribution of the clock path; while the multi - stage combiner clock - data phase locking technology relies on theoretical models (such as T_d = t_d1+T / 4+t_c - q2+t_c - q3) to dynamically calculate the fixed phase difference between the clock and data paths, achieving precise alignment across clock domains.

[0036] Actual verification shows (which will be further elaborated later) that this solution not only achieves PVT resistance comparable to traditional PI solutions under the 12nm FinFET process, but also significantly reduces power consumption and area consumption with a simplified circuit structure. For example, by replacing the complex PI module and adaptive algorithm with the open-loop control logic of a four-phase clock phase converter, the circuit design complexity is significantly reduced, and the collaborative optimization of the frequency divider and phase selection module further improves the utilization rate of the timing margin. The simulation results show that this technology can effectively suppress the timing violations and the increase in bit error rate in high-speed data transmission, and is superior to the PI solution of the same process in terms of area and power consumption indicators. In addition, the universality of this technology has been verified through theoretical expansion and can be widely applied to various scenarios that require clock phase adjustment to meet the setup / hold time of D flip-flops, providing an efficient and reliable technical path for low-power and high-density integrated circuit design under advanced processes.

[0037] The following further describes the specific embodiments and experimental results of the present invention.

[0038] The present invention proposes a PI-free high-speed clock distribution network under the SMIC 12nm FinFET process and proves its feasibility. In a traditional high-speed serial interface (SerDes) transmitter (TX), it usually includes multiple levels of multiplexers (MUX) and feed-forward equalizers (FFE), where the multiple-level MUX is used to combine multiple low-speed parallel data to obtain high-speed serial data. During the process of data serialization, multiple clocks with different frequencies are often required as control signals to control each MUX to successfully complete data sampling and data combination. In the TX, due to the different directions of the clock frequency from high to low and the data rate from low to high, there may be a problem that the setup time of the sampling flip-flop of the subsequent MUX may not be satisfied between two adjacent levels of MUX. To solve this problem, the traditional method is to perform precise control of the clock phase through a high-precision phase interpolator combined with a complex adaptive algorithm, and this solution has been very common under relatively mature processes. However, under relatively advanced FinFET processes, the additional area and power consumption costs brought by the high-precision phase interpolator and complex adaptive algorithm circuits will account for an increasing proportion, and designers often need to spend more time and effort in this regard for complex cost control. To address this problem, this design has developed an open-loop control type clock distribution network without PI and without an adaptive loop under the SMIC 12nm FinFET process, achieving an effect equivalent to that of the traditional solution with an area and power consumption overhead much smaller than that of the traditional solution.

[0039] The design of this clock distribution network is based on a 1 / 4 rate TX architecture. Figure 1It is the architecture diagram of the TX. In the order of data flow from left to right, there are two low-speed data source parts composed of a PRBS data source and a modeselect module. This part is controlled by a differential low-speed clock 1. Then there is the first-stage combiner, which is controlled by a four-phase low-speed clock 2. Before the low-speed clock 2 is sent into the first-stage combiner, it will first pass through an open-loop controlled four-phase clock phase converter and a unit pulse generator. The four-phase clock phase converter can select a certain phase of the four-phase clock as the 0th-phase clock to meet the setup and hold times required for sampling. The remaining phases of the clock are sequentially used as the 1st, 2nd, and 3rd-phase clocks. The first-stage MUX is controlled in this new phase order after conversion to sample the data output from the data source. After that, the four-phase clock after phase conversion, under the control of the unit pulse generator, generates four non-overlapping unit pulse signals, which serve as the first-stage combiner and the combining control signal to control it to complete data combining. Thus, the first-stage data combining is completed.

[0040] After the first-stage data combining is completed, the second-stage combiner performs the second combining. This part is controlled by a four-phase high-speed clock 3. Before the high-speed clock 3 is sent into the second-stage combiner, the same operations as those for the low-speed clock 2 are also performed on it to ensure the stability of sampling and combining of the second-stage combiner.

[0041] The theoretical proof of the above circuit is as follows, which can support the feasibility of the circuit: After the circuit is powered on and works, a four-phase high-speed clock 2 is first generated by an on-chip built-in clock source, and its four phases are respectively denoted as 2_0, 2_90, 2_180, and 2_270. Then, based on 3_0 and 2_180, four phases of the low-speed clock 1 are generated through a frequency divider, which are respectively denoted as 1_0, 1_90, 1_180, and 1_270. Thus, the control clocks at all levels have been generated. Among them, 2_0 serves as the reference for the highest-speed clock and is also the clock source of the low-speed clock 1. When the frequency divider circuit is fixed, there is a fixed phase relationship between the phase of 2_0 and 1_0. Denote the phase difference by which 2_0 leads 1_0 as t d1 .

[0042] After the phase relationships of the clocks at all levels are determined, the data path starts to work. First, based on 1_0 and 1_180 of the low-speed clock 1, the PRBS data source is controlled to generate multiple low-speed parallel data signals, denoted as D a , the data D a The phase difference by which the data D lags behind 1_0 is denoted as t c-q1 , and then, the first-stage combiner combines the D aPerform multiplexing processing. At this time, if 1_0 is still used as the sampling reference of the first-stage multiplexer, it will inevitably lead to the problem that the setup time of the sampling trigger of the first-stage multiplexer cannot be satisfied, which will cause serious duty cycle distortion or directly lead to a large number of data bit errors. Therefore, here 1_180 is used as the sampling reference clock of the first-stage MUX, which can ensure that the setup time and hold time of the sampling trigger of the first-stage multiplexer are satisfied. After that, the first-stage multiplexer uses the low-speed clock 1_180 as the reference to complete the sampling of data D a to obtain data D a ’ . Denote the phase difference between data D a ’ and the low-speed clock 1180 as t c-q2 . After that, based on the low-speed data 1_270, multiplex data D a ’ to obtain data D b , and denote the phase difference between data D b and the low-speed clock 1_270 as t c-q3 . Then, the second-stage multiplexer is controlled by the high-speed clock 2 to complete the sampling and multiplexing of data D b . At this time, on the second-stage multiplexer, the data D b participating in multiplexing and the reference clock 2_0 controlling multiplexing already have a fixed phase relationship. From the above analysis, the phase difference between the initial valid edge of 2_0 and the initial valid edge of D b is: T d =t d1 +T1 / 2+t c-q2 +t c-q3 . Here is a prerequisite, that is, t c-q1 is much smaller than T1 / 2, which holds in digital circuits under conventional processes. This design also verifies this prerequisite condition under the advanced process adopted.

[0043] Through the above analysis, the fixed phase relationship T b between the sampling reference clock 2_0 of the second-stage multiplexer and the data D d to be sampled can be found. After that, the four-phase clock phase converter on the high-speed clock 2 can be used to reselect the phase order of the high-speed clock 2. At most 3 operations are performed to select a certain phase clock that meets the setup and hold time requirements as the new phase 0 clock as the reference clock to complete the sampling and multiplexing of data D b . This method can not only make full use of the four clock phases provided by the architecture itself to fully and effectively ensure the stability of sampling of the second-stage multiplexer under different PVT conditions, but also has a great optimization in power consumption and area compared with the traditional PI-based clock network, providing a certain reference value for the design of the TX clock distribution network under the advanced process.

[0044] The above theoretical analysis can prove the feasibility of the circuit. Figure 2 It is the timing diagram of the above process. In actual simulation, the stability of the circuit in function is also verified. And in terms of area and power consumption, compared with the TX structure using PI and adaptive loop under the same process, this scheme can obtain better results. Figure 3 Actual timing diagram of the clock network. Figure 4 Show the area comparison. Figure 5 Show the power consumption comparison.

[0045] The clock distribution network of the high-speed serial transmitter without PI designed by the present invention under the 12nm FinFET process, compared with the technology of combining phase interpolator and adaptive loop adopted in CN118138019A mentioned in the background art, this invention can achieve the anti-PVT effect of the combiner clock sampling point similar to it under a more advanced process with smaller power consumption and area consumption. The present invention theoretically proves that under the 1 / 4-speed clock architecture, a high-speed serial transmitter with an internal data source can flexibly convert the clock sampling points of each stage of the combiner only using 4 existing clock phases to adapt to the influence of timing disturbances under different PVTs on the bit error rate of the final transmitter. Combining with the theoretical proof, the present invention also realizes the specific design of this circuit under the 12nm FinFET process and conducts sufficient simulation verification, and finally achieves good technical effects.

[0046] Compared with the technology of combining phase interpolator and adaptive loop adopted in CN118138019A, this invention can achieve the anti-PVT effect of the combiner clock sampling point similar to it under a more advanced process with smaller power consumption and area consumption. The present invention theoretically proves that under the 1 / 4-speed clock architecture, a high-speed serial transmitter with an internal data source can flexibly convert the clock sampling points of each stage of the combiner only using 4 existing clock phases to adapt to the influence of timing disturbances under different PVTs on the bit error rate of the final transmitter. Combining with the theoretical proof, the present invention also realizes the specific design of this circuit under the 12nm FinFET process and conducts sufficient simulation verification, and finally achieves good technical effects.

[0047] Before the present invention, similar technologies to those in CN118138019A were adopted in most transmitter designs, that is, generating more clock phases based on a phase interpolator to fully ensure phase redundancy to overcome potential timing violation problems in extreme cases. The reason for not using the 4-phase clock conversion technology adopted in the present invention is most likely that previous designs were mostly carried out under planar processes with relatively low speeds, and power consumption and area overhead were not the main contradictions to be considered in transmitter design. The focus was still on ensuring the realization of the functions of the transmitter circuit itself as much as possible, so a technology based on a phase interpolator with a larger margin and relatively more mature was adopted. However, under the advanced FinFET process adopted in the present invention, power consumption and area overhead are a major contradiction that must be solved. Therefore, with sufficient theoretical proof, the feasibility of sacrificing a part of the margin in clock phases in exchange for smaller power consumption and area overhead was demonstrated, and finally the effectiveness of the invention was proven in actual design.

[0048] In all application backgrounds where clock phase adjustment is required to meet the sampling setup / hold time of D flip-flops, the phase conversion technology proposed by the present invention can be attempted.

[0049] The above content is a further detailed description of the present invention in combination with specific / preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several alternatives or variations can be made to these described embodiments, and these alternative or variation methods should all be regarded as belonging to the protection scope of the present invention. In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "preferred embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. Without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples. Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made to the present invention without departing from the protection scope of the patent application.

Claims

1. A high-speed serial transmitter clock distribution network without PI, characterized in that include: A multi-phase clock generation module is used to generate a four-phase high-speed clock signal and generate a multi-level frequency-divided clock through a frequency divider based on a reference phase; A four-phase clock phase converter, connected to the multi-phase clock generation module, for dynamically selecting a target phase in the four-phase clock as a reference phase and reordering the remaining phases to generate a phase-reconfigurable clock sequence; Multi-stage combiner control module, including: a. The first-stage combiner is driven by the divided clock and controls data sampling and combining timing through a fixed-phase clock sequence; b. The second stage combiner is driven by the high-speed clock and completes high-speed data combining based on the reordered clock sequence; The unit pulse generator is linked with the four-phase clock phase converter to generate non-overlapping pulse signals to complete the circuit combining action.

2. The clock distribution network of the high-speed serial transmitter without PI according to claim 1, characterized in that: The multi-phase clock generation module includes a frequency divider that divides the high-speed clock 2_180 phase by 4 to generate a low-speed clock 1 including phases 1_0, 1_90, 1_180, and 1_270, and there is a fixed phase difference td1 between the frequency divider and the 2_0 phase of the high-speed clock 2.

3. The clock distribution network of the high-speed serial transmitter without PI as described in claim 1, characterized in that: The phase selection logic of the four-phase clock phase converter is configured to select any one phase from the four-phase clock as a new reference phase, and the remaining phases are cyclically arranged in the original order to form a continuous clock sequence with a phase offset of 90°.

4. The clock distribution network of the high-speed serial transmitter without PI as described in claim 1, characterized in that: The width of the pulse signal generated by the unit pulse generator is 1 / 4 of the corresponding clock cycle, and a non-overlapping protection interval is set between adjacent pulses. The pulse signal directly drives the multi-stage combiner.

5. The clock distribution network of the high-speed serial transmitter without PI according to claim 1, characterized in that: The sampling clock of the first-stage combiner uses the divided clock 1_180 phase, which is delayed by T / 2 cycles relative to the data source control clock 1_0, so that the setup time t of the data path c-q1 meets the sampling requirements.

6. The clock distribution network of the PI-less high-speed serial transmitter according to claim 1, characterized in that: The phase-locked control module determines the reference phase selection of the second-stage combiner by calculating the model T d = t d1 + T1 / 2 + t c-q2 + t c-q3 where t c-q2 is the sampling delay of the first-stage combiner, and t c-q3 is the output delay of the first-stage combination.

7. The clock distribution network of the high-speed serial transmitter without PI as described in claim 1, characterized in that: The second-stage combiner integrates a 1UI generator.

8. The clock distribution network of the high-speed serial transmitter without PI according to claim 1, characterized in that: The multi-phase clock generation module includes a four-phase high-speed clock, whose initial phases are 2_0, 2_90, 2_180, and 2_270.

9. The PI-less high-speed serial transmitter clock distribution network according to claim 3, wherein: The phase selection operation of the four-phase clock phase converter is performed at most three times, and the timing margin optimization is completed by traversing the non-reference phases in the four-phase clock.

10. The clock distribution network of the high-speed serial transmitter without PI according to claim 1, characterized in that: It also includes an SPI configuration interface for dynamically setting the initial reference phase selection parameters of the four-phase clock phase converter and the protection interval width of the unit pulse generator.

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