Clock circuit of programmable logic device and clock circuit configuration method

Abstract

The application discloses a clock circuit of a programmable logic device and a clock circuit configuration method. The clock circuit of the programmable logic device comprises a clock network comprising a plurality of clock paths, the plurality of clock paths having the same input clock signal and being respectively used for transmitting the clock signal to corresponding programmable logic; the number of inverters on each clock path is zero, one or more; a plurality of clock polarity selectors are respectively arranged on the plurality of clock paths, each clock polarity selector is used for performing inversion output or original polarity output on the received clock signal according to a preset polarity selection control signal; wherein each polarity selection control signal is determined based on the number of inverters on the corresponding clock path, so that the clock signals received by each programmable logic have the same polarity. Thus, the application can reduce the influence of clock signal duty cycle deterioration and ensure the consistency of clock polarity without limiting the parity of inverters.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a clock circuit for a programmable logic device and a clock circuit configuration method. Background Technology

[0002] In high-speed system design, synchronous timing design places high demands on the quality of clock signals, and timing calculations typically use a stable clock signal as a reference. However, factors such as physical routing, manufacturing process mismatches, and power supply can all affect clock performance. As the size of FPGA (Field Programmable Gate Array) chips gradually increases, the clock path becomes correspondingly longer, making clock duty cycle issues more sensitive. For applications requiring dual-edge sampling, such as DDR and SerDes interfaces, clock duty cycle has a significant impact.

[0003] Common FPGA global clocks are typically driven by cascaded clock buffers, but the deterioration of the clock duty cycle increases with the number of buffer stages. Existing technologies also employ clock driving via inverters, but to ensure clock polarity consistency, the number of inverters must be even, which introduces additional power consumption and area requirements, and limits the flexibility of clock circuit design. Summary of the Invention

[0004] In view of the above problems, this application provides a clock circuit for a programmable logic device and a clock circuit configuration method to solve the above technical problems.

[0005] In a first aspect, this application provides a clock circuit for a programmable logic device, comprising: A clock network includes multiple clock paths, each having the same input clock signal, and each used to transmit a clock signal to a corresponding programmable logic device; wherein the number of inverters on each clock path is zero or one or more. Multiple clock polarity selectors are respectively set on the multiple clock paths. Each clock polarity selector is used to invert the received clock signal or maintain the original polarity output according to a preset polarity selection control signal. Each polarity selection control signal is determined based on the number of inverters on the corresponding clock path, so that the clock signals received by each programmable logic have the same polarity.

[0006] In some embodiments, when the clock update received by each of the programmable logic blocks is configured to have the same polarity as the input clock signal, the polarity selection control signal is configured as follows: If the number of inverters on the corresponding clock path is even, the corresponding clock polarity selector is controlled to maintain the original polarity of the received clock signal output, so that the clock signals received by each programmable logic have the same polarity. If the number of inverters on the corresponding clock path is odd, the corresponding clock polarity selector is controlled to invert the received clock signal and output it, so that the clock signals received by each programmable logic have the same polarity.

[0007] In some embodiments, the clock polarity selector includes an inverter and a selector; The input terminal of the inverter and the first input terminal of the selector are both used to receive clock signals from the corresponding clock path; The output of the inverter is connected to the second input of the selector; The control terminal of the selector is used to receive the polarity selection control signal, and the output terminal of the selector is used to output the inverted clock signal or the clock signal that retains the original polarity.

[0008] In some embodiments, each clock polarity selector is located at the end of the corresponding clock path, and the output of each clock polarity selector is connected to the corresponding programmable logic.

[0009] In some embodiments, at least one of the clock polarity selectors is located at a preset position on the corresponding clock path, excluding the end.

[0010] In some embodiments, the inverters in the clock network have the same electrical characteristics, and the load traces driven by each inverter have the same physical length.

[0011] In a second aspect, this application provides a clock circuit configuration method for a programmable logic device, used to configure the clock circuit of the programmable logic device described in the first aspect, comprising: During the logic routing stage of the programmable logic device, the total number of inverters on each clock path is identified. Based on the parity of each total quantity, a corresponding polarity selection control signal is generated. Each of the polarity selection control signals is configured to a corresponding clock polarity selector, so that each of the clock polarity selectors inverts or maintains the original polarity of the received clock signal according to the polarity selection control signal, so that the clock signals received by each of the programmable logics have the same polarity.

[0012] In some embodiments, the step of identifying the total number of inverters on each clock path includes: Parse the model file describing the clock circuit of the programmable logic device; Identify attribute annotations or keywords related to the inverter in the model file; The total number of inverters on each clock path is determined based on the attribute labels or keywords.

[0013] In some embodiments, the step of configuring each of the polarity selection control signals to a corresponding clock polarity selector includes: Each of the polarity selection control signals is written into the bit stream file of the programmable logic device; The bitstream file is loaded into the programmable logic device to configure each of the clock polarity selectors.

[0014] Thirdly, this application provides a programmable logic device, comprising: Multiple programmable logic; and Clock circuit for a programmable logic device as described in the first aspect.

[0015] The clock circuit and clock circuit configuration method for programmable logic devices provided in this application, by including multiple clock paths with the same input clock signal in the clock network, and setting the number of inverters on each clock path to zero or one or more, removes the restriction that the number of inverters on the clock path must be even. Simultaneously, by setting multiple clock polarity selectors on each of the multiple clock paths, each clock polarity selector inverts or maintains the original polarity of the received clock signal according to a preset polarity selection control signal. Each polarity selection control signal is determined based on the number of inverters on the corresponding clock path. Therefore, even when the number of inverters on each clock path is inconsistent, the clock signals received by each programmable logic device can still have the same polarity. This solves the problems in the prior art where cascaded clock buffers easily lead to clock duty cycle degradation, and the design constraints caused by limiting the number of inverters to an even number to ensure clock polarity consistency when using inverters. It has the technical effect of reducing the impact of cascaded clock buffers on the clock duty cycle and ensuring the polarity consistency of multiple clock paths without forcibly limiting the number of inverters on each clock path to an even number.

[0016] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the clock circuit of the programmable logic device provided in an embodiment of this application is shown.

[0019] Figure 2 A schematic diagram of a clock polarity selector provided in an embodiment of this application is shown.

[0020] Figure 3 This illustration shows yet another schematic diagram of the clock circuit of the programmable logic device provided in an embodiment of this application.

[0021] Figure 4 A flowchart illustrating a clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown.

[0022] Figure 5 A flowchart of step S100 of the clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown.

[0023] Figure 6 A flowchart of step S300 of the clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown. Detailed Implementation

[0024] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0027] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0028] The clock circuit for programmable logic devices provided in this application is applicable to the design and configuration of global clock networks for field-programmable logic devices, such as field-programmable gate arrays. In this application scenario, the clock circuit is located between the clock source of the programmable logic device and multiple programmable logic units. It is responsible for transmitting the original clock signal provided by the clock source to the corresponding programmable logic units through multiple clock paths, and uniformly controlling the polarity of the clock signal on each path during transmission to ensure that the clock signal received by each programmable logic unit has the same polarity.

[0029] Figure 1 A schematic diagram of the clock circuit of the programmable logic device provided in an embodiment of this application is shown, as follows: Figure 1 As shown, the clock circuit of the programmable logic device provided in this application embodiment includes a clock network and multiple clock polarity selectors.

[0030] The clock network comprises multiple clock paths, each sharing the same input clock signal and used to transmit clock signals to corresponding programmable logic devices. Each clock path contains either zero or one or more inverters. Multiple clock polarity selectors are correspondingly positioned on each clock path. Each clock polarity selector, based on a preset polarity selection control signal, either inverts the received clock signal or maintains its original polarity. Each polarity selection control signal is determined based on the number of inverters on the corresponding clock path, ensuring that the clock signals received by each programmable logic device have the same polarity.

[0031] Optionally, a clock network is used to carry and distribute the input clock signal CLKIN within the programmable logic device. The clock network includes multiple clock paths, each receiving the same input clock signal CLKIN and transmitting it to its corresponding programmable logic. Since the multiple programmable logics may be located at different positions within the programmable logic device, the transmission distance, routing direction, and number of inverters traversed by each clock path may differ. Therefore, the number of inverters on each clock path can be set to zero, one, or more, depending on the clock transmission requirements of the corresponding programmable logic.

[0032] Inverters on the clock path are used to invert the clock signal transmitted along the corresponding clock path. During the clock signal's passage through the inverter, due to factors such as manufacturing process mismatches, the propagation delays for the rising and falling edges may differ. For example, if the duty cycle of the input clock signal CLKIN is 50%, and the rising edge propagation delay is BASE_VALUE+Δ and the falling edge propagation delay is BASE_VALUE when CLKIN passes through the first inverter, then as the clock signal continues through subsequent inverters, the duty cycle offset caused by the difference in rising and falling edge delays in the previous inverter can be compensated for during the subsequent inversion process because the inverter changes the polarity of the clock signal. Taking CLKIN passing through one inverter to obtain CLK_A, and then through two inverters to obtain CLK_B as an example, the total propagation delay of the rising edge and the total propagation delay of the falling edge from CLKIN to CLK_B are both BASE_VALUE + Δ + BASE_VALUE. Therefore, the duty cycle of CLK_B can be restored to close to 50%. When inverters are used in clock signal transmission, the polarity of the clock signal changes after each inverter. When the number of inverters on different clock paths is different, the clock signals arriving at the corresponding clock polarity selector may have different polarities. If these clock signals are directly provided to the corresponding programmable logic, it may result in inconsistent clock signal polarities received by multiple programmable logics; if polarity consistency is maintained simply by limiting the number of inverters on each clock path, it will impose constraints on the hardware layout of the clock paths.

[0033] Based on this, embodiments of this application provide a clock polarity selector. The clock polarity selector is located in the clock signal transmission link of the corresponding clock path and is used to participate in adjusting the output polarity of the corresponding clock path. Each clock polarity selector receives the clock signal CLKIN transmitted along the corresponding clock path, and its output polarity is controlled by the corresponding polarity selection control signal SEL. The polarity selection control signal SEL is determined based on the number of inverters on the corresponding clock path, enabling the clock polarity selector to perform corresponding polarity processing on the received clock signal according to the influence of the inverters on the clock signal polarity in that clock path, thereby ensuring that the clock signals output from different paths maintain consistent polarity.

[0034] Understandable, Figure 1 This diagram illustrates the clock circuit of a programmable logic device using only 5 clock paths as an example. In practical applications, the number of clock paths is not limited to this. Figure 1 The number shown can be increased depending on the number and location of the programmable logic and the deployment requirements of the clock network.

[0035] The clock circuit of the programmable logic device provided in this application carries the same input clock signal through multiple clock paths in the clock network, and allows each clock path to have a different number of inverters according to hardware deployment needs. At the same time, through multiple clock polarity selectors set corresponding to each clock path and a polarity selection control signal determined based on the corresponding number of inverters, the polarity of the clock signal transmitted on each clock path is processed. Thus, while using inverters to participate in clock transmission to reduce the impact of clock buffer cascading on the clock duty cycle, it can solve the problem of inconsistent polarity of multiple clocks caused by differences in the number of inverters, and reduce the restrictions on clock path design caused by requiring the number of inverters to meet fixed conditions.

[0036] In some embodiments, in the clock circuit of the programmable logic device provided in this application, when the clock signal received by each programmable logic is configured to have the same polarity as the input clock signal, the polarity selection control signal is configured as follows: If the number of inverters on the corresponding clock path is even, the corresponding clock polarity selector will be controlled to maintain the original polarity of the received clock signal output, so that the clock signals received by each programmable logic have the same polarity. If the number of inverters on the corresponding clock path is odd, the corresponding clock polarity selector will be controlled to invert the received clock signal and output it, so that the clock signals received by each programmable logic have the same polarity.

[0037] Optionally, when the design requires the clock signal received by the programmable logic to have the same polarity as the input clock signal, the polarity selection control signal SEL can be determined based on the parity of the number of inverters on the corresponding clock path. Since the polarity of the clock signal flips once for each inverter, when the number of inverters on the corresponding clock path is even, the clock signal undergoes an even number of polarity flips relative to the input clock signal after transmission along that clock path, maintaining the same polarity as the input clock signal. In this case, the polarity selection control signal SEL controls the corresponding clock polarity selector to output the received clock signal with its original polarity. When the number of inverters on the corresponding clock path is odd, the clock signal undergoes an odd number of polarity flips relative to the input clock signal after transmission along that clock path, resulting in the opposite polarity to the input clock signal. In this case, the polarity selection control signal SEL controls the corresponding clock polarity selector to invert the received clock signal, ensuring that the clock signal processed by the clock polarity selector on that clock path has the same polarity as the input clock signal. Therefore, in this embodiment, the clock signals received by each programmable logic unit can have the same polarity as the input clock signal, thereby ensuring that the clock signals received by each programmable logic unit have the same polarity.

[0038] It should be noted that when the number of inverters on the corresponding clock path is zero, it is a case where the number of inverters is even. The clock signal is not flipped by the inverters, so the corresponding clock polarity selector also maintains its original polarity output.

[0039] It is understood that the above configuration method, which uses the input clock signal as the target polarity, is only one optional implementation. In other implementations, it is not required that the clock signals received by each programmable logic unit have the same polarity as the input clock signal, but only that the clock signals received by each programmable logic unit have the same polarity; in this case, the polarity selection control signal can be determined based on the number of inverters on the corresponding clock path, so that the clock signals received by each programmable logic unite to the same polarity.

[0040] In some embodiments, Figure 2 A schematic diagram of a clock polarity selector provided in an embodiment of this application is shown, as follows: Figure 2 As shown, the clock polarity selector includes an inverter and a selector.

[0041] The input terminal of the inverter and the first input terminal of the selector are both used to receive clock signals from the corresponding clock path; the output terminal of the inverter is connected to the second input terminal of the selector; the control terminal of the selector is used to receive the polarity selection control signal, and the output terminal of the selector is used to output the inverted clock signal or output the clock signal that retains the original polarity.

[0042] Optionally, in this clock polarity selector structure, the clock signal CLK from the corresponding clock path is simultaneously fed into two input branches: one input branch is directly connected to the first input terminal of the selector, and the other input branch is first connected to the second input terminal of the selector after passing through an inverter. Thus, the first input terminal of the selector receives a clock signal that maintains its original polarity, and the second input terminal receives a clock signal processed by the inverter. These two correspond to the two polarity states that the clock polarity selector can output. The selector can choose between the first and second input terminals based on the polarity selection control signal SEL received at its control terminal. When the polarity selection control signal SEL indicates that the original polarity output is maintained, the selector selects the first input terminal, allowing the clock signal CLK from the corresponding clock path to be output without passing through the inverter inside the clock polarity selector; when the polarity selection control signal SEL indicates that the output is inverted, the selector selects the second input terminal, allowing the clock signal CLK from the corresponding clock path to be inverted by the inverter inside the clock polarity selector before being output. With the above structure, the clock polarity selector can select the output clock signal that retains the original polarity or the inverted clock signal based on the polarity selection control signal without changing other hardware structures of the corresponding clock path.

[0043] In terms of hardware implementation, inverters can be formed using logic units within programmable logic devices capable of inverting, and selectors can be formed using selection circuits that can select different input terminals under the action of control signals. Inverters, selectors, and the connections between them together constitute the polarity selection path of a clock polarity selector. This allows clock signals from corresponding clock paths to form a signal path that maintains its original polarity and an inverted signal path after entering the clock polarity selector. The selector then outputs one of the clock signals according to the polarity selection control signal.

[0044] In some embodiments, such as Figure 1 As shown, each clock polarity selector is located at the end of the corresponding clock path, and the output of each clock polarity selector is connected to the corresponding programmable logic.

[0045] Optionally, in this configuration, the clock polarity selector is located at the end of the corresponding clock path closest to the programmable logic. The clock signal from the corresponding clock path is first transmitted along that clock path to the clock polarity selector, and then output by the clock polarity selector to the corresponding programmable logic. Since the output of each clock polarity selector is connected to the corresponding programmable logic, the clock signal output by the clock polarity selector can be directly used as the clock signal received by the corresponding programmable logic. Therefore, even when the number of inverters on each clock path may differ, by controlling the output polarity of the corresponding clock signal through the clock polarity selectors located at the ends of each clock path, the clock signals received by multiple programmable logics can maintain consistent polarity. This configuration facilitates polarity adjustment before the clock signal enters the programmable logic, allowing the number of inverters at the front end of each clock path to be set according to clock transmission needs, rather than being limited to a fixed number simply to maintain polarity consistency.

[0046] In some embodiments, Figure 3 Another schematic diagram of the clock circuit of the programmable logic device provided in the embodiments of this application is shown, such as... Figure 3 As shown, at least one clock polarity selector is set at a preset position on the corresponding clock path, except at the end.

[0047] Optionally, in this configuration, the clock polarity selector is not necessarily located at the end of the corresponding clock path. Instead, it can be placed at a preset position on the corresponding clock path, excluding the end, according to the hardware layout requirements of the clock path. This preset position is the location the clock signal passes through during transmission along the corresponding clock path. After reaching this preset position, the clock signal enters the corresponding clock polarity selector, which then inverts or maintains the original polarity output according to the polarity selection control signal. Since at least one clock polarity selector can be placed at a preset position other than the end, the clock polarity selector in this embodiment is not limited to being placed near the input of the programmable logic. It can also be deployed in conjunction with the routing position of the corresponding clock path, thereby ensuring that the clock signals received by each programmable logic have the same polarity while improving the flexibility of the clock polarity selector's deployment on the clock path.

[0048] In some embodiments, in the clock circuit of the programmable logic device provided in this application, the inverters in the clock network have the same electrical characteristics, and the load traces driven by each inverter have the same physical length.

[0049] Optionally, the inverters in the clock network have the same electrical characteristics, which can be achieved by using inverters of the same specification. Each inverter drives a load trace of the same physical length, ensuring consistent load trace conditions for each inverter within the clock network. This configuration makes the transmission conditions of the clock signal more consistent as it passes through each inverter and its corresponding load trace, thereby reducing the impact of inverter specification differences or load trace differences on clock signal transmission.

[0050] It is understood that the above-mentioned configuration of inverters having the same electrical characteristics and each inverter driving a load trace with the same physical length is merely an optional implementation of this application and is not intended to limit the number of clock inverters, inverter specifications, or load trace conditions driven by the inverters in this application embodiment. In other embodiments, the number of clock inverters may differ from the number shown in the figures, the inverters in the clock network may not use exactly the same specifications, and the load traces driven by each inverter may not be completely identical, as long as the corresponding clock polarity selector and polarity selection control signal can be combined to ensure that the clock signals received by each programmable logic have the same polarity.

[0051] This application also provides a clock circuit configuration method for a programmable logic device, used to configure the clock circuit of the programmable logic device described in the above embodiments. Figure 4 A flowchart illustrating the clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown, such as... Figure 4 As shown, the clock circuit configuration method includes: S100: During the logic routing stage of the programmable logic device, the total number of inverters on each clock path is identified. Optionally, the clock topology of the programmable logic device is generated during the logic routing stage. In this embodiment, each clock path can be identified at this stage, and the total number of inverters participating in clock signal transmission on each clock path can be counted. This total number is used to characterize the number of times the clock signal passes through the inverter in the corresponding clock path, and serves as the basis for subsequently generating the polarity selection control signal.

[0052] S200: Generate corresponding polarity selection control signals based on the parity of each total number. Optionally, after obtaining the total number of inverters on each clock path, this embodiment of the application determines the polarity state of the clock signal after transmission on the corresponding clock path based on the parity of each total number. Since the clock signal undergoes a polarity flip once after passing through each inverter, different total numbers of inverters will result in different polarity states of the clock signals transmitted on different paths. Generating corresponding polarity selection control signals based on this parity allows each polarity selection control signal to match the total number of inverters on the corresponding clock path.

[0053] S300: Each polarity selection control signal is configured to its corresponding clock polarity selector, so that each clock polarity selector inverts or maintains the original polarity of the received clock signal according to the polarity selection control signal, ensuring that the clock signals received by each programmable logic device have the same polarity. Optionally, after generating each polarity selection control signal, each polarity selection control signal is configured to the clock polarity selector corresponding to the corresponding clock path, so that each clock polarity selector can select the output polarity according to the corresponding polarity selection control signal. When the programmable logic device is operating, the clock polarity selector receives the clock signal from the corresponding clock path and, under the control of the polarity selection control signal, inverts or maintains the original polarity of the clock signal. Therefore, even if the total number of inverters on different clock paths is different, the output polarity can be adjusted through their respective corresponding clock polarity selectors, ensuring that the clock signals received by each programmable logic device have the same polarity.

[0054] Understandably, in the actual design flow of programmable logic devices, the design software typically first parses the user's design code, calls the software's cell library to complete code synthesis, and then determines the number and location of the programmable logic units to be used based on the synthesis results to complete the logic placement. After the logic placement is completed, the design software further completes the connection relationship between the programmable logic units and forms the corresponding clock topology during the logic routing stage. The clock circuit configuration method for programmable logic devices provided in this application embodiment can be executed in the above-mentioned logic routing stage, so that, based on the determined clock path, the total number of inverters on each clock path can be identified, and the corresponding polarity selection control signal can be generated and configured accordingly. After completing the relevant processing, including clock circuit configuration, the design software can also generate configuration data for configuring the programmable logic device and load the configuration data into the programmable logic device to drive the programmable logic device to operate according to the configured hardware logic. The above-described user design code parsing, code synthesis, logic layout, configuration data generation and loading process is a complete process typically involved in the configuration of programmable logic device design software. It is used to illustrate the application process environment in which the clock circuit configuration method provided in this application embodiment is located. The clock circuit configuration method in this application embodiment focuses on identifying the total number of inverters on each clock path during the logic routing stage, and generating and configuring the corresponding polarity selection control signal based on the parity of the total number. Therefore, the general processing process in the above complete design flow is not taken as a necessary limitation for implementing clock polarity configuration.

[0055] In some embodiments, Figure 5 A flowchart of step S100 of the clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown, as follows: Figure 5As shown, step S100: the step of identifying the total number of inverters on each clock path, includes: S110: Parse the model file describing the clock circuit of the programmable logic device. Optionally, the model file is used to represent the hardware functional behavior of the clock circuit in the programmable logic device. The model file may include port definitions and functional descriptions. During the routing process, the design software can parse the model file to obtain port information and functional description information related to the clock circuit, providing a data basis for subsequent identification of inverters on the clock path.

[0056] S120: Identify attribute labels or keywords related to the inverter in the model file. Optionally, the model file can use attribute labels or keywords to represent functional information related to the inverter. For example, attribute labels can be set on the input clock port or output clock port in the inverter model file. After parsing the model file, the design software can identify the attribute labels or keywords to determine the information related to the inverter.

[0057] S130: Determine the total number of inverters on each clock path based on attribute labels or keywords. Optionally, after identifying the attribute labels or keywords related to inverters in the model file, the design software can count the attribute labels or keywords on each clock path during the routing process to determine the total number of inverters on each clock path. This total number is used as the basis for subsequently generating the corresponding polarity selection control signal.

[0058] It is understood that the method described above for setting attribute annotations through the input or output clock ports of the inverter model file is merely an example of identifying inverter-related information and is not intended to limit the specific representation of inverter-related information in the model file. In other implementations, the design software can also identify inverter-related information through other identifiers or keywords in the model file and determine the total number of inverters on each clock path accordingly.

[0059] In some embodiments, Figure 6 A flowchart of step S300 of the clock circuit configuration method for a programmable logic device provided in an embodiment of this application is shown, as follows: Figure 6 As shown, step S300: the step of configuring each polarity selection control signal to the corresponding clock polarity selector, includes: S310: Write each polarity selection control signal into the bit stream file of the programmable logic device. Optionally, after generating each polarity selection control signal, each polarity selection control signal can be written into the bit stream file as configuration information for configuring the corresponding clock polarity selector, so that the bit stream file contains polarity selection control information for configuring each clock polarity selector.

[0060] S320: Loads the bitstream file into the programmable logic device to configure each clock polarity selector. Optionally, after loading the bitstream file into the programmable logic device, the information in the bitstream file is written into the programmable logic device's memory array, thereby completing the configuration of each clock polarity selector. Thus, when the programmable logic device is operating, each clock polarity selector can, according to the corresponding polarity selection control signal, invert the received clock signal or maintain its original polarity.

[0061] This application also provides a programmable logic device, including: a plurality of programmable logic blocks; and a clock circuit for the programmable logic device as described in the above embodiments. Optionally, the plurality of programmable logic blocks can be distributed in different locations within the programmable logic device and are used to implement corresponding logic functions respectively. The clock circuit of the programmable logic device is connected to the plurality of programmable logic blocks and is used to provide the clock signals required for the operation of the plurality of programmable logic blocks. When the programmable logic device is operating, the input clock signal is transmitted to the corresponding programmable logic block via the clock circuit of the programmable logic device, enabling the plurality of programmable logic blocks to operate based on the same input clock signal, and ensuring, through the aforementioned clock circuit, that the clock signals received by each programmable logic block have the same polarity.

[0062] The above description, in conjunction with specific embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications and substitutions should be considered within the scope of protection of this application.

Claims

1. A clock circuit for a programmable logic device, characterized in that, include: A clock network includes multiple clock paths, each having the same input clock signal, and each used to transmit a clock signal to a corresponding programmable logic device; wherein the number of inverters on each clock path is zero or one or more. Multiple clock polarity selectors are respectively set on the multiple clock paths. Each clock polarity selector is used to invert the received clock signal or maintain the original polarity output according to a preset polarity selection control signal. Each polarity selection control signal is determined based on the number of inverters on the corresponding clock path, so that the clock signals received by each programmable logic have the same polarity.

2. The clock circuit of the programmable logic device according to claim 1, characterized in that, When the clock signal received by each of the programmable logic modules is configured to have the same polarity as the input clock signal, the polarity selection control signal is configured as follows: If the number of inverters on the corresponding clock path is even, the corresponding clock polarity selector is controlled to maintain the original polarity of the received clock signal output, so that the clock signals received by each programmable logic have the same polarity. If the number of inverters on the corresponding clock path is odd, the corresponding clock polarity selector is controlled to invert the received clock signal and output it, so that the clock signals received by each programmable logic have the same polarity.

3. The clock circuit of the programmable logic device according to claim 1, characterized in that, The clock polarity selector includes an inverter and a selector; The input terminal of the inverter and the first input terminal of the selector are both used to receive clock signals from the corresponding clock path; The output of the inverter is connected to the second input of the selector; The control terminal of the selector is used to receive the polarity selection control signal, and the output terminal of the selector is used to output the inverted clock signal or the clock signal that retains the original polarity.

4. The clock circuit of the programmable logic device according to claim 1, characterized in that, Each clock polarity selector is located at the end of the corresponding clock path, and the output of each clock polarity selector is connected to the corresponding programmable logic.

5. The clock circuit of the programmable logic device according to claim 1, characterized in that, At least one of the clock polarity selectors is set at a preset position on the corresponding clock path, excluding the end.

6. The clock circuit of the programmable logic device according to claim 1, characterized in that, The inverters in the clock network have the same electrical characteristics, and the load traces driven by each inverter have the same physical length.

7. A method for configuring a clock circuit of a programmable logic device, used to configure the clock circuit of the programmable logic device according to any one of claims 1 to 5, characterized in that, include: During the logic routing stage of the programmable logic device, the total number of inverters on each clock path is identified. Based on the parity of each total quantity, a corresponding polarity selection control signal is generated. Each of the polarity selection control signals is configured to a corresponding clock polarity selector, so that each of the clock polarity selectors inverts or maintains the original polarity of the received clock signal according to the polarity selection control signal, so that the clock signals received by each of the programmable logics have the same polarity.

8. The clock circuit configuration method for a programmable logic device according to claim 7, characterized in that, The step of identifying the total number of inverters on each clock path includes: Parse the model file describing the clock circuit of the programmable logic device; Identify attribute annotations or keywords related to the inverter in the model file; The total number of inverters on each clock path is determined based on the attribute labels or keywords.

9. The clock circuit configuration method for a programmable logic device according to claim 7, characterized in that, The step of configuring each of the polarity selection control signals to the corresponding clock polarity selector includes: Each of the polarity selection control signals is written into the bit stream file of the programmable logic device; The bitstream file is loaded into the programmable logic device to configure each of the clock polarity selectors.

10. A programmable logic device, characterized in that, include: Multiple programmable logic; as well as The clock circuit of the programmable logic device as described in any one of claims 1 to 6.

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