Dynamic power consumption optimization method, electronic equipment and storage medium

Abstract

The invention belongs to the technical field of electronic design automation, and provides a dynamic power consumption optimization method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a circuit design, and determining a starting point of a specific type in the circuit design; performing backward traversal on the circuit design along a signal propagation direction from the starting point to determine circuit branch structure information and a specific type of termination point in the circuit design; starting from the termination point, establishing an ODC expression, performing forward traversal on the circuit design in an inverse signal propagation direction, and in the forward traversal process, based on the circuit branch structure information, propagating the ODC expression in the circuit design until ODC distribution of the circuit design is determined; based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. According to the method, the ODC expression can be quickly and efficiently propagated in the whole circuit design, so that a designer can conveniently optimize the dynamic power consumption through ODC distribution.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology, and particularly to a dynamic power consumption optimization method, an electronic device, and a storage medium. Background Art

[0002] With the progress of manufacturing technology and design technology, the design method of electronic systems has undergone a profound transformation. From computer-aided design (CAD), computer-aided engineering (CAE) to electronic design automation (EDA), the degree of design automation is getting higher and higher, and the design complexity is also getting stronger.

[0003] Integrated circuit (IC) EDA refers to a design method that uses electronic design automation software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of very large scale integrated circuit chips. At present, EDA technology has become a powerful tool for modern electronic design. Without the support of EDA technology, it is unthinkable to complete the design and manufacturing of very large scale integrated circuits. IC designers need to use EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors to reduce design deviations, improve the success rate of tape-out, and save tape-out costs.

[0004] With the improvement of chip design process, the power consumption problem has become more and more important. The power consumption of a chip mainly consists of static power consumption and dynamic power consumption. The static power consumption mainly comes from leakage current, which can be optimized through the transistor manufacturing process and power management. The dynamic power consumption is the power consumption generated during the operation of the chip, including the power consumption generated when the input state of the logic gate changes, during signal transmission, and when driving the load. Usually, the dynamic power consumption accounts for most of the total power consumption. Therefore, the primary goal of improving the chip power consumption is to reduce the dynamic power consumption.

[0005] The industry has always been trying to further explore ways to save dynamic power consumption at a lower cost. In related technologies, the optimization of dynamic power consumption generally has the following methods:

[0006] Method 1: Dynamic voltage and frequency scaling. Dynamically adjust the voltage and frequency according to the workload. Reducing the frequency and voltage can significantly reduce power consumption. When the load is low, reduce the frequency and voltage to improve energy efficiency.

[0007] Method 2: Multi-voltage domain management. Dynamically monitor the working states of different modules and adjust the voltage dynamically according to the load demand. In this way, when a module is in the idle state, the voltage can be reduced, and when needed, the voltage can be increased;

[0008] Method 3: Reduce switching activities through circuit design, such as optimizing the number of logic gates, eliminating redundant logic, optimizing data paths, etc., to reduce the dynamic power consumption caused by logic changes.

[0009] However, the above traditional dynamic power consumption optimization schemes have the following problems:

[0010] For Method 1, dynamic voltage and frequency adjustment requires integrating a voltage regulation module and a dynamic clock generator, which will increase the chip area and design cost. At the same time, frequent voltage / frequency adjustment may cause temperature changes, affecting the stability of the thermal design;

[0011] For Method 2, multi-voltage domain management makes the circuit design more complex. Designers need to consider issues such as the mutual relationship, timing matching, and signal integrity between different voltage domains, increasing the difficulty of design and verification;

[0012] For Method 3, the method of reducing switching activities by changing the circuit design may cause new timing problems when changing the logic on the data path. Therefore, this method will also increase the new design difficulty. Summary of the Invention

[0013] The present invention provides a dynamic power consumption optimization method, an electronic device, and a storage medium to at least solve the problems of low efficiency and high difficulty in reducing the dynamic power consumption of chips in the related art. The technical solution of the present invention is as follows:

[0014] According to the first aspect of the present invention, there is provided a dynamic power consumption optimization method applied to electronic design automation software, including: obtaining a circuit design and determining a starting point of a specific type in the circuit design; starting from the starting point, performing a backward traversal of the circuit design along the signal propagation direction to determine the circuit branch structure information and a termination point of the specific type in the circuit design; starting from the termination point, establishing an ODC expression, performing a forward traversal of the circuit design in the reverse signal propagation direction, and during the forward traversal, based on the circuit branch structure information, propagating the ODC expression in the circuit design until the ODC distribution of the circuit design is determined; based on the ODC distribution, performing dynamic power consumption optimization on the circuit design.

[0015] According to a second aspect of the present invention, there is provided an electronic device, comprising: a processor; a memory for storing processor-executable instructions, wherein, when the processor-executable instructions are run by the processor, the processor is caused to execute the dynamic power consumption optimization method according to the present invention.

[0016] According to a third aspect of the present invention, there is provided a computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enabling the electronic device to execute the dynamic power consumption optimization method according to the present invention.

[0017] The technical solution provided by the present invention at least brings the following beneficial effects:

[0018] The present invention can first perform backward traversal at the starting point of circuit design to find all termination points in the design, then perform forward propagation on the ODC expressions starting from these termination points, and finally, after the forward propagation is completed throughout the design, the ODC distribution of the entire design can be obtained, thereby providing an optimization direction for dynamic power consumption to the designer.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention and do not constitute an improper limitation to the present invention.

[0021] Figure 1 is a flowchart showing a dynamic power consumption optimization method according to an exemplary embodiment of the present invention;

[0022] Figure 2 is a schematic diagram showing backward traversal according to an exemplary embodiment of the present invention;

[0023] Figure 3 is a schematic diagram showing forward traversal according to an exemplary embodiment of the present invention;

[0024] Figure 4 is a flowchart showing the process of propagating ODC expressions according to an exemplary embodiment of the present invention;

[0025] Figure 5 is a schematic diagram showing the principle of ODC generation points according to an exemplary embodiment of the present invention;

[0026] Figure 6 is a schematic diagram showing a specific logic device according to an exemplary embodiment of the present invention;

[0027] Figure 7is another schematic diagram showing a specific logic device according to an exemplary embodiment of the present invention;

[0028] Figure 8 is a structural schematic diagram showing an ODC expression according to an exemplary embodiment of the present invention;

[0029] Figure 9 is a schematic diagram showing a non-specific logic device according to an exemplary embodiment of the present invention;

[0030] Figure 10 is a schematic diagram showing a combinational logic device of a fan-out type according to an exemplary embodiment of the present invention;

[0031] Figure 11 is a block diagram showing an electronic device according to an exemplary embodiment of the present invention. Detailed implementation manners

[0032] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] It should be noted that the steps in the description and drawings of the present invention are not limited to the specific order or sequence described. It should be understood that these steps can be interchanged when appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present invention. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0034] RTL (Register Transfer Level) is an important abstraction level in digital circuit design. At this level, the design mainly focuses on the transfer of data between registers and its operations, rather than the specific circuit implementation details. In addition to the methods for reducing dynamic power consumption in the above related technologies, for RTL-level chip design, by enabling or disabling the clock signal as needed through clock gating, unnecessary dynamic power consumption can be effectively reduced. For example, a wide flop is a flip-flop with a wide data bus in RTL, or a wide-bit (or multi-bit) flip-flop. Here, wide usually refers to the bit width of the flip-flop, that is, the number of bits it can store. If it can be reasonably switched on and off by using clock gating, the dynamic power consumption can be reduced.

[0035] ODC (Observability Don’t Care) is a state where the output of a register cannot be observed by subsequent paths. Under specific conditions, if the data is not visible at the output, it becomes a don't care or non-observable condition, which is called the ODC condition. By reasonably controlling the switches through the ODC conditions of related logic devices, it provides the possibility to effectively reduce dynamic power consumption. For example, when there is an ODC condition on the working path in a wide flop, if the switch of the wide flop can be controlled through the ODC condition, the dynamic power consumption on the wide flop path can be effectively reduced. In order to reasonably use dynamic clock gating to switch the wide flop, it is necessary to find all the ODC conditions in the design. However, in the face of today's complex designs with hundreds of millions of gates, how to efficiently and quickly obtain the ODC conditions in the design and save dynamic power consumption based on this has become a major problem, and the industry has been trying to find ways to further explore lower-cost methods.

[0036] In view of the above problems, an exemplary embodiment of the present invention proposes a dynamic power consumption optimization method, an electronic device, and a computer-readable storage medium, to find the ODC conditions in a circuit design through a new method and propagate them throughout the design, facilitating the effective reduction of the dynamic power consumption of the design, providing ideas for designers to optimize the chip, and thus being able to solve or at least alleviate the above problems.

[0037] In the first aspect of the exemplary embodiment of the present invention, a dynamic power consumption optimization method is provided, which will be described in detail below with reference to Figures 1 to 11 this.

[0038] According to the exemplary embodiment of the present invention, the dynamic power consumption optimization method is applicable to electronic design automation (EDA) software. The user terminal can load the EDA software, enabling the user terminal to obtain the circuit design and determine the starting points of a specific type in the circuit design; starting from the starting points, perform a backward traversal of the circuit design along the signal propagation direction to determine the circuit branch structure information and the termination points of a specific type in the circuit design; starting from the termination points, establish an ODC expression, perform a forward traversal of the circuit design in the reverse signal propagation direction, and during the forward traversal, based on the circuit branch structure information, propagate the ODC expression in the circuit design until the ODC distribution of the circuit design is determined; based on the ODC distribution, perform dynamic power consumption optimization on the circuit design.

[0039] This method can first perform a backward traversal at the starting point of the circuit design to find all the termination points in the design, then start a forward propagation of the ODC expression from these termination points, and finally, after the forward propagation is completed throughout the design, the ODC distribution of the entire design can be obtained, thereby providing the designer with the optimization direction for dynamic power consumption.

[0040] The above user terminal can be, for example, a tablet computer, a laptop computer, a digital assistant, a wearable device, etc. However, the implementation scenario of the above-described dynamic power consumption optimization method is only an example scenario. The dynamic power consumption optimization method according to the exemplary embodiments of the present invention can also be applied to other application scenarios. For example, it can also be that the user requests to access relevant data from the server through the network on the user terminal (such as a mobile phone, a desktop computer, a tablet computer, etc.), and the server can access the data by executing the dynamic power consumption optimization method according to the exemplary embodiments of the present invention and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform, a virtualization center, etc.

[0041] Next, it will be referred to Figure 1 to describe the specific steps of a dynamic power consumption optimization method according to an exemplary embodiment of the present invention. As Figure 1 shown, the dynamic power consumption optimization method may include the following steps:

[0042] In step S110, a circuit design can be obtained, and the starting points of a specific type in the circuit design can be determined.

[0043] Here, the designer usually uses HDL (Hardware Description Language) to complete the circuit design. It describes the structure and behavior of the digital system hardware in text form, can represent logic circuit diagrams, logic expressions, and the logic functions completed by digital logic systems, etc., so as to model multiple abstract design levels such as the algorithm level, the register transfer level, the gate level, and the switch level. Further, the starting points of a specific type can be the primary inputs of the circuit design. The primary inputs are used to receive the main input signals in the circuit, generally the interfaces of modules or circuit units, representing the input terminals of the entire circuit. These inputs can be signals from other circuit modules or control signals from external systems. In addition to the primary inputs, the starting points of a specific type can also be the input / output terminals of other specified logic devices, etc., to traverse the specified area of the circuit according to actual needs. The present invention does not limit this.

[0044] Next, in step S120, starting from the starting point, a backward traversal of the circuit design can be performed along the signal propagation direction to determine the circuit branch structure information and the termination points of a specific type in the circuit design.

[0045] Here, the circuit design can be traversed backward by, but not limited to, DFS (Depth-First Search). DFS is a method for traversing or searching a tree or graph. It traverses nodes as deep as possible along the depth of the tree or graph, and then backtracks to the previous node to find unexplored nodes and continue the search. Further, a specific type of termination point can be the primary output of the circuit design. The primary output is used to transmit the main output signals in the circuit. These output signals are the results or responses directly generated from the function of the circuit design after it is completed, and are usually related to the logical operations or processing of the input signals. In addition to the primary output, a specific type of termination point can also be the input / output terminals of other specified logic devices, etc., to traverse a specified area of the circuit according to actual needs. The present invention places no restrictions on this.

[0046] According to an exemplary embodiment of the present invention, the circuit design can include multiple logic devices. Any two logic devices with a signal association relationship can be connected through a net. Here, the characteristic of a logic device is that it has only one output terminal, and the input terminal can have only one or multiple, and often has more than one input terminal. In addition, the input and output terminals of the logic device include two states: a high-level state, represented by 1 at this time; a low-level state, represented by 0 at this time. In addition to the input terminal of the logic device having multiple, the output terminal of the logic device can also be connected to the input terminals of multiple other logic devices through a net with a branch structure, which makes the entire circuit design usually have a complex circuit branch structure. Thus, during the process of traversing the circuit design backward, information about these circuit branch structures can be obtained simultaneously. Further, during the process of traversing backward, type checking operations to be described later can be not performed on the logic device before encountering the termination point to speed up the execution speed of the backward traversal.

[0047] For ease of understanding, the backward traversal will be described below with reference to Figure 2 is a schematic diagram showing the backward traversal according to an exemplary embodiment of the present invention. As shown in Figure 2 shown, the exemplary circuit design includes multiple primary inputs and primary outputs, such as primary input 1, primary input 2, primary output 1, primary output 2, and primary output 3. There are multiple logic devices between the primary inputs and primary outputs, and each logic device is connected through a net according to the signal association relationship. Figure 2 The arrow direction in Figure 2 indicates the signal propagation direction, and the backward traversal is performed along this signal propagation direction.

[0048] Returning to the reference Figure 1, Next, in step S130, starting from the termination point, an ODC expression can be established, and a forward traversal of the circuit design can be performed in the reverse signal propagation direction. During the forward traversal, based on the circuit branch structure information, the ODC expression is propagated in the circuit design until the ODC distribution of the circuit design is determined.

[0049] In a possible implementation, the termination point can be the main output of the circuit design. At this time, starting from the termination point, the initial ODC expression is null, that is, a null ODC expression is established starting from the termination point. In other possible implementations, if the termination point is not the main output, the initially established ODC expression is determined according to the actual ODC conditions of the logic device.

[0050] Figure 3 is a schematic diagram showing the forward traversal according to an exemplary embodiment of the present invention, Figure 3 The arrow direction in indicates the reverse direction of signal propagation, and the forward traversal is performed along the reverse direction of the signal propagation.

[0051] Figure 4 is a flowchart showing the propagation of the ODC expression according to an exemplary embodiment of the present invention. Propagating the ODC expression in the circuit design can be achieved through the steps in Figure 4 as follows.

[0052] As Figure 4 shown, in step S410, the first ODC expression corresponding to the output terminal of the current logic device can be determined; next, in step S420, a first type check can be performed on the current logic device to determine whether the current logic device is a specific logic device.

[0053] According to an exemplary embodiment of the present invention, during the forward traversal, a first type check can be performed on each logic device. When the logic device contains an ODC generation point, the ODC condition of the logic device can be added to the propagated ODC expression. Here, if the logic device contains a control signal, when the control signal is in a certain state, the signal change on the selection branch in the other state will not affect the subsequent circuit. Then, the other state of the control signal at this time can be called an ODC generation point.

[0054] Figure 5 is a schematic diagram showing the principle of the ODC generation point according to an exemplary embodiment of the present invention. As Figure 5As shown, the exemplary logic device includes an input terminal S1 for a control signal, input terminals d0 and d1 for data signals, and an output terminal O. Assume that the control signal includes two states, S1 and!S1. When S1 == 1, O = d1. At this time, the signal change on the branch d0 selected by!S1 will not affect the output terminal. Therefore, the ODC condition corresponding to the input terminal d1 is!S1. When S1 == 0, O = d0. At this time, the signal change on the branch d1 selected by S1 will not affect the output terminal. Therefore, the ODC condition corresponding to the input terminal d0 is S1.

[0055] According to an exemplary embodiment of the present invention, a specific logic device may include an input terminal for receiving a control signal and at least one input terminal for receiving a data signal. That is, a specific logic device is a device including an ODC generation point, such as a multiplexer and a tri-state gate, etc., which are devices including a control signal. Such devices have separate input terminals as control signals. For example, when the control signal state of the multiplexer is 1, it indicates that its output is determined only by one of the input signals. At this time, the other signal is in the ODC state.

[0056] Return reference Figure 4 , in step S430, when the current logic device is a specific logic device, the ODC condition corresponding to each input terminal of the current logic device can be generated. Here, the ODC condition corresponding to each input terminal is determined separately by the function of the current logic device in the design.

[0057] Next, in step S440, the ODC condition corresponding to each input terminal can be combined with the first ODC expression respectively to obtain the second ODC expression corresponding to each input terminal, and the second ODC expression is recorded in the net connected to the corresponding input terminal.

[0058] Figure 6 is a schematic diagram showing a specific logic device according to an exemplary embodiment of the present invention, as Figure 6 shown. Assume that the current logic device is a multiplexer, its control signal is S1, the first ODC expression corresponding to the output terminal is ODC1, the ODC conditions corresponding to the two data signal input terminals are S1 and!S1 respectively, and there is no corresponding ODC condition for the control signal input terminal. Then, after combination, the second ODC expressions corresponding to the two data signal input terminals are ODC1|S1 and ODC1|!S1 respectively, and the second ODC expression corresponding to the control signal input terminal is still ODC1.

[0059] Figure 7 is another schematic diagram showing a specific logic device according to an exemplary embodiment of the present invention, as Figure 7As shown, assuming that the current logic device is a three-state gate, when there are two adjacent three-state gates on the propagation path, their control signals are S1 and S2 respectively. At this time, the ODC conditions corresponding to the input ends of the two three-state gates are !S1 and !S2 respectively. If the first ODC expression propagated is ODC1, then the second ODC expression generated by combining it with the ODC conditions corresponding to the input ends of the two three-state gates is !S2|!S1|ODC1.

[0060] According to an exemplary embodiment of the present invention, ODC expressions can be stored through an N-ary tree structure to facilitate efficient propagation during the traversal process. Here, each node in the traditional binary tree has one data item and at most two child nodes. If each node of the tree is allowed to have more than two child nodes, then the tree is called an N-order multi-way tree, or an N-ary tree. Further, according to an exemplary embodiment of the present invention, the leaf nodes of the N-ary tree can correspond to the control signals of the ODC conditions, and the non-leaf nodes of the N-ary tree can correspond to logical operators, such as & for logical operators, | for logical operators, and ! for non-logical operators. Whenever a new ODC condition needs to be inserted into the original ODC expression, its logical operator node and control signal node are inserted in sequence through its logical relationship with the original ODC expression.

[0061] According to an exemplary embodiment of the present invention, when the ODC condition corresponding to each input terminal is respectively combined with the first ODC expression, the following steps can be performed: for any input terminal of each input terminal, determine the logical relationship between the target ODC condition corresponding to the input terminal and the first ODC expression; insert the logical operator corresponding to the logical relationship as the first root node into the N-ary tree corresponding to the first ODC expression, so that the root node of the N-ary tree corresponding to the first ODC expression is transformed into a child node of the first root node; create another child node of the first root node, so that the other child node corresponds to the control signal of the target ODC condition. As an example, the ODC condition corresponding to each input terminal can be combined with the first ODC expression through OR logic, so that the operator of OR logic can be inserted as the first root node into the N-ary tree corresponding to the first ODC expression.

[0062] Figure 8 is a schematic diagram showing the structure of an ODC expression according to an exemplary embodiment of the present invention, such as Figure 8As shown, when the original ODC expression A passes through the ODC occurrence point B during propagation, B needs to be inserted into the expression. Specifically, the logical relationship between A and B is first inserted as a new root node, then the original root node becomes a child node, and B is inserted as a new child node, thus obtaining the N-ary tree of the new ODC expression A|B. As the ODC expression continues to propagate forward, the expression is updated in the same way: a new root node is created, the root node of the original N-ary tree is used as its child node, and the ODC expression to be combined is used as a new child node to generate a new N-ary tree. When the new ODC expression is generated, it is recorded on the corresponding wire net, and during the forward traversal, the expression propagates forward accordingly, thus obtaining the N-ary tree of the ODC expression ((A|B)&C&D)&(E&F).

[0063] In addition, return reference Figure 4 , in step S450, when the current logic device is a non-specific logic device, the first ODC expression can be respectively recorded in the wire nets connected to each input terminal of the current logic device. Here, the non-specific logic device does not include the input terminal for receiving control signals, that is, there is no new ODC generation point in the non-specific logic device.

[0064] Figure 9 is a schematic diagram showing a non-specific logic device according to an exemplary embodiment of the present invention. As Figure 9 shown, when there is no new ODC generation point in the logic device, it is only necessary to propagate the ODC expression on the output path along the input path. Here, when a series of non-specific logic devices form a multi-input single-output structure, assuming that the ODC expression at the output terminal is ODC1, it is only necessary to split and propagate the ODC expression on the output path along each input path. At this time, the ODC expression at each input terminal is still ODC1.

[0065] Return reference Figure 4, as described above, in step S410, the first ODC expression corresponding to the output terminal of the current logic device can be determined. Here, step S410 can be implemented in the following specific manner: perform a second type of check on the current logic device to determine whether the current logic device is a fan-out type of combinational logic device; in the case where the current logic device is a fan-out type of combinational logic device, merge the multiple ODC expressions recorded in the netlist connected to the output terminal of the current logic device, so as to obtain the first ODC expression. Further, the output terminal of the fan-out type of combinational logic device is connected to the input terminals and / or termination points of multiple other logic devices through a netlist. Furthermore, when merging the multiple ODC expressions recorded in the netlist connected to the output terminal of the current logic device, the multiple ODC expressions can be merged through an AND logic, so as to create a second root node, such that the second root node corresponds to the logic operator of the AND logic; transform the root node of each ODC expression in the multiple ODC expressions into a child node of the second root node.

[0066] Figure 10 is a schematic diagram showing a fan-out type of combinational logic device according to an exemplary embodiment of the present invention, as Figure 10 shown, for a fan-out type of combinational logic device, it means that the signal of a single path will become multiple paths containing the same signal after propagation. Assuming that the ODC expressions of its three output terminals are ODC1, ODC2, and ODC3 respectively, the ODC expression of its input terminal at this time is the result of merging the ODC expressions on these three paths, that is, ODC1 & ODC2 & ODC3.

[0067] In addition, according to an exemplary embodiment of the present invention, in the case where the current logic device is a non-fan-out type of combinational logic device, the ODC expression recorded in the netlist connected to the output terminal of the current logic device can be used as the first ODC expression. Here, the output terminal of the non-fan-out type of combinational logic device is connected to an input terminal or a termination point of another logic device through a netlist.

[0068] Returning to Figure 1 , in step S140, based on the ODC distribution, dynamic power consumption optimization can be performed on the circuit design.

[0069] In a possible implementation, the design level of the circuit design can be the register transfer level, the specific type of starting point can be the primary input of the circuit design, and the specific type of termination point can be the primary output of the circuit design. Therefore, clock gating logic can be inserted into the circuit design based on the ODC distribution between the primary input and the primary output of the circuit design, thereby optimizing the dynamic power consumption of the entire circuit design. As an example, when all the forward traversals are completed, the ODC distribution of the entire design can be obtained. Subsequently, the ODC expression at the output of the wide flop can be converted into enable logic, which can turn off the wide flop in a state that meets the ODC condition, thereby improving the circuit structure and saving dynamic power consumption.

[0070] According to an exemplary embodiment of the present invention, still taking the wide flop as an example, backward propagation can be first performed in the design to find all the starting points in the design, and then forward propagation can be performed starting from these starting points. During the propagation process, the traversed logic devices are judged. If it is a specific logic device, its ODC condition is inserted into the ODC expression, and this expression will continue to analyze each logic device during the forward propagation. When a wide flop is encountered, the ODC expression is stored in the corresponding container, indicating that the wide flop can be controlled by this ODC expression. Finally, when the forward propagation is completed in the entire design, the ODC distribution of the entire design can be obtained, so that the designer can control the switching of the wide flop through the ODC distribution, thus effectively reducing the dynamic power consumption on the wide flop path.

[0071] According to the dynamic power consumption optimization method of the exemplary embodiment of the present invention, backward traversal can be started from a specific type of starting point until a specific type of termination point is encountered. After the termination point is encountered during the backward traversal, forward traversal is performed; during the forward traversal, the ODC condition of the specific logic device is obtained, that is, during the forward traversal starting from the termination point, the type of each traversed logic device is judged. If it is a specific logic device, its ODC condition is stored in the ODC expression and continues to be passed; when the ODC expression is propagated during the forward traversal, the ODC expression can be updated according to the type of the encountered logic device; when the forward traversal of all termination points is completed, the ODC distribution of the entire design can be obtained, thereby providing the designer with the optimization direction of dynamic power consumption.

[0072] In a second aspect of the exemplary embodiment of the present invention, an electronic device is provided. The electronic device includes: a processor; a memory for storing processor-executable instructions, wherein when the processor-executable instructions are run by the processor, the processor is caused to execute the dynamic power consumption optimization method according to the exemplary embodiment of the present invention.

[0073] Figure 11 is a block diagram showing an electronic device according to an exemplary embodiment of the present invention. As Figure 11 shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when the processor-executable instructions are run by the processor, they cause the processor to execute a dynamic power consumption optimization method according to an exemplary embodiment of the present invention.

[0074] As an example, the electronic device 10 does not have to be a single device, and can also be any assembly of devices or circuits that can execute the above instructions (or instruction sets) individually or jointly. The electronic device 10 can also be part of an integrated control system or system manager, or can be configured to interface with a server locally or remotely (e.g., via wireless transmission).

[0075] In the electronic device 10, the processor 101 can include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller or a microprocessor. As an example and not a limitation, the processor 101 can also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0076] The processor 101 can run instructions or code stored in the memory 102, where the memory 102 can also store data. The instructions and data can also be sent and received via a network interface device over a network, where the network interface device can use any known transmission protocol.

[0077] The memory 102 can be integrated with the processor 101, for example, by arranging RAM or flash memory within an integrated circuit microprocessor, etc. In addition, the memory 102 can include a separate device, such as an external disk drive, a storage array, or other storage devices that can be used by any database system. The memory 102 and the processor 101 can be operatively coupled, or can communicate with each other, for example, through an I / O port, a network connection, etc., so that the processor 101 can read files stored in the memory 102.

[0078] In addition, the electronic device 10 can also include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.). All components of the electronic device 10 can be connected to each other via a bus and / or a network.

[0079] In an exemplary embodiment, a computer-readable storage medium may also be provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device can execute the dynamic power consumption optimization method as described in the above exemplary embodiment. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: read-only memory (ROM), random access memory (RAM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc memory, hard disk drive (HDD), solid state drive (SSD), cartridge memory (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and provide the computer program and any associated data, data files, and data structures to a processor or computer such that the processor or computer can execute the computer program. The computer program in the above computer-readable storage medium may run in an environment deployed in computer devices such as clients, hosts, proxy devices, servers, etc. In addition, in one example, the computer program and any associated data, data files, and data structures are distributed on a networked computer system such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0080] Those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include known common knowledge or conventional technical means in the technical field not disclosed by the present invention. The specification and embodiments are only to be considered as exemplary, and the true scope and spirit of the present invention are pointed out by the claims.

[0081] In addition, it should be noted that although several examples of the steps are described above with reference to specific drawings, it should be understood that the embodiments of the present invention are not limited to the combinations given in the examples. Steps appearing in different drawings may be combined, and no exhaustive listing is made here.

[0082] It should be understood that the present invention is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is limited only by the claims.

Claims

1. A dynamic power consumption optimization method, applied to electronic design automation software, characterized in that, Including: Obtain a circuit design and determine a starting point of a specific type in the circuit design; Starting from the starting point, perform a backward traversal of the circuit design along the signal propagation direction to determine circuit branch structure information and a termination point of the specific type in the circuit design; Starting from the termination point, establish an ODC expression, perform a forward traversal of the circuit design in the reverse signal propagation direction, and during the forward traversal, based on the circuit branch structure information, propagate the ODC expression in the circuit design until the ODC distribution of the circuit design is determined; Based on the ODC distribution, perform dynamic power consumption optimization on the circuit design.

2. The dynamic power consumption optimization method according to claim 1, wherein The circuit design includes a plurality of logic devices, wherein any two logic devices having a signal association relationship are connected by a net; Wherein, propagating the ODC expression in the circuit design includes: Determine a first ODC expression corresponding to the output end of the current logic device; Perform a first type check on the current logic device to determine whether the current logic device is a specific logic device, wherein the specific logic device includes an input end for receiving a control signal and at least one input end for receiving a data signal; In the case that the current logic device is a specific logic device, generate an ODC condition corresponding to each input end of the current logic device; Combine the ODC condition corresponding to each input end with the first ODC expression respectively to obtain a second ODC expression corresponding to each input end, and record the second ODC expression in the net connected to the corresponding input end.

3. The dynamic power consumption optimization method according to claim 2, wherein Propagating the ODC expression in the circuit design further includes: In the case that the current logic device is a non-specific logic device, record the first ODC expression in the net connected to each input end of the current logic device, wherein the non-specific logic device does not include an input end for receiving a control signal.

4. The dynamic power consumption optimization method according to claim 2, wherein Determining a first ODC expression corresponding to the output end of the current logic device includes: Perform a second type check on the current logic device to determine whether the current logic device is a combinational logic device of a fan-out type, wherein the output end of the combinational logic device of the fan-out type is connected to the input ends of a plurality of other logic devices and / or the termination point through a net; In the case that the current logic device is a combinational logic device of a fan-out type, merge the plurality of ODC expressions recorded in the net connected to the output end of the current logic device to obtain the first ODC expression.

5. The dynamic power consumption optimization method according to claim 4, wherein Determining a first ODC expression corresponding to the output end of the current logic device further includes: In the case that the current logic device is a non-fan-out type combinational logic device, use the ODC expression recorded in the net connected to the output end of the current logic device as the first ODC expression, wherein the output end of the non-fan-out type combinational logic device is connected to an input end of one other logic device or one termination point through a net.

6. The dynamic power consumption optimization method according to claim 4, characterized in that The ODC expression is stored in the structure of an N-ary tree, where the leaf nodes of the N-ary tree correspond to the control signals of the ODC conditions, and the non-leaf nodes of the N-ary tree correspond to logical operators.

7. The dynamic power consumption optimization method according to claim 6, wherein Combining the ODC conditions corresponding to each input terminal with the first ODC expression respectively, includes: For any one of the input terminals in each of the input terminals, determining the logical relationship between the target ODC condition corresponding to this input terminal and the first ODC expression; Inserting the logical operator corresponding to the logical relationship as the first root node into the N-ary tree corresponding to the first ODC expression, so that the root node of the N-ary tree corresponding to the first ODC expression becomes a child node of the first root node; Creating another child node of the first root node, so that the other child node corresponds to the control signal of the target ODC condition.

8. The dynamic power consumption optimization method according to claim 6, wherein The multiple ODC expressions are merged through an AND logic, wherein, merging the multiple ODC expressions recorded in the wire network connected to the output terminal of the current logic device, includes: Creating a second root node, so that the second root node corresponds to the logical operator of the AND logic; Changing the root nodes of the N-ary trees corresponding to each of the multiple ODC expressions into child nodes of the second root node.

9. The dynamic power consumption optimization method according to any one of claims 1 to 8, characterized in that, The design level of the circuit design is the register transfer level, the specific type of starting point is the main input of the circuit design, and the specific type of ending point is the main output of the circuit design, wherein, based on the ODC distribution, performing dynamic power consumption optimization on the circuit design, includes: Based on the ODC distribution between the main input and the main output of the circuit design, inserting clock gating logic into the circuit design, so as to optimize the dynamic power consumption of the entire circuit design.

10. An electronic device, characterized in that, Includes: A processor; A memory for storing processor-executable instructions, wherein, when the processor-executable instructions are run by the processor, the processor is caused to execute the dynamic power consumption optimization method according to any one of claims 1 to 9.

11. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is enabled to execute the dynamic power consumption optimization method according to any one of claims 1 to 9.

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